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[Qemu-commits] [qemu/qemu] a431ab: hw/arm: Use TYPE_ARM_SMMUV3
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] a431ab: hw/arm: Use TYPE_ARM_SMMUV3 |
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Date: |
Fri, 03 Feb 2023 10:54:55 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a431ab0e4ef7fcff4349fd8453d0ea5f06ec2617
https://github.com/qemu/qemu/commit/a431ab0e4ef7fcff4349fd8453d0ea5f06ec2617
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
Log Message:
-----------
hw/arm: Use TYPE_ARM_SMMUV3
Use the macro instead of two explicit string literals.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d2617ac7d3139d870ba14204aedd74395990192
https://github.com/qemu/qemu/commit/9d2617ac7d3139d870ba14204aedd74395990192
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix physical address resolution for Stage2
Conversion to probe_access_full missed applying the page offset.
Cc: qemu-stable@nongnu.org
Reported-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d88935cb19f8f8e7291026efe23862316ff2510
https://github.com/qemu/qemu/commit/9d88935cb19f8f8e7291026efe23862316ff2510
Author: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/char/pl011.c
M include/hw/char/pl011.h
Log Message:
-----------
hw/char/pl011: refactor FIFO depth handling code
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.
One functional (albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 13ea96fa34bcb6076f42a41194ab363c945e4b07
https://github.com/qemu/qemu/commit/13ea96fa34bcb6076f42a41194ab363c945e4b07
Author: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: add post_load hook for backwards-compatibility
Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single-register-deep FIFO now. Then we changed it to always store data
at pos 0.
If guest disables FIFO and the proceeds to read data, it will work out
fine, because we still read from current read_pos before setting it to
0.
However, to make code less fragile, introduce a post_load hook for
PL011State and move fixup read FIFO state when FIFO is disabled. Since
we are introducing a post_load hook, also do some sanity checking on
untrusted incoming input state.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b7a165e8c94b1f7eee326fa6b68eb45f0324ea1
https://github.com/qemu/qemu/commit/3b7a165e8c94b1f7eee326fa6b68eb45f0324ea1
Author: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: implement a reset method
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 23dcbfc080eb8a8e8395d753f07adbb0ab761143
https://github.com/qemu/qemu/commit/23dcbfc080eb8a8e8395d753f07adbb0ab761143
Author: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: better handling of FIFO flags on LCR reset
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a2260983c65539010310b7105da284026cfceba4
https://github.com/qemu/qemu/commit/a2260983c65539010310b7105da284026cfceba4
Author: Alexander Graf <agraf@csgraf.de>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M target/arm/hvf/hvf.c
M target/arm/hvf/trace-events
Log Message:
-----------
hvf: arm: Add support for GICv3
We currently only support GICv2 emulation. To also support GICv3, we will
need to pass a few system registers into their respective handler functions.
This patch adds support for HVF to call into the TCG callbacks for GICv3
system register handlers. This is safe because the GICv3 TCG code is generic
as long as we limit ourselves to EL0 and EL1 - which are the only modes
supported by HVF.
To make sure nobody trips over that, we also annotate callbacks that don't
work in HVF mode, such as EL state change hooks.
With GICv3 support in place, we can run with more than 8 vCPUs.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-id: 20230128224459.70676-1-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a3495d11c4970c6cac05da516439a4f74ff6db01
https://github.com/qemu/qemu/commit/a3495d11c4970c6cac05da516439a4f74ff6db01
Author: Alexander Graf <agraf@csgraf.de>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Consolidate GIC finalize logic
Up to now, the finalize_gic_version() code open coded what is essentially
a support bitmap match between host/emulation environment and desired
target GIC type.
This open coding leads to undesirable side effects. For example, a VM with
KVM and -smp 10 will automatically choose GICv3 while the same command
line with TCG will stay on GICv2 and fail the launch.
This patch combines the TCG and KVM matching code paths by making
everything a 2 pass process. First, we determine which GIC versions the
current environment is able to support, then we go through a single
state machine to determine which target GIC mode that means for us.
After this patch, the only user noticable changes should be consolidated
error messages as well as TCG -M virt supporting -smp > 8 automatically.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20221223090107.98888-2-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5e91b9e03f6cbb0f8333e60422ef44c15b4775c7
https://github.com/qemu/qemu/commit/5e91b9e03f6cbb0f8333e60422ef44c15b4775c7
Author: Alexander Graf <agraf@csgraf.de>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Make accels in GIC finalize logic explicit
Let's explicitly list out all accelerators that we support when trying to
determine the supported set of GIC versions. KVM was already separate, so
the only missing one is HVF which simply reuses all of TCG's emulation
code and thus has the same compatibility matrix.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221223090107.98888-3-agraf@csgraf.de
[PMM: Added qtest to the list of accelerators]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ed65e32cf52a91c620c925faa90049b8e35365e1
https://github.com/qemu/qemu/commit/ed65e32cf52a91c620c925faa90049b8e35365e1
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
sbsa-ref: remove cortex-a76 from list of supported cpus
Cortex-A76 supports 40bits of address space. sbsa-ref's memory
starts above this limit.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3999d2d290a5c722c15bac9272e47090a95a0554
https://github.com/qemu/qemu/commit/3999d2d290a5c722c15bac9272e47090a95a0554
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions). Fix the names.
(This has no guest-visible effect as the names are for debug purposes
only.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org
Commit: ce9a8863b2c465a7227984bdadf743786f7a1849
https://github.com/qemu/qemu/commit/ce9a8863b2c465a7227984bdadf743786f7a1849
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct syndrome for ATS12NSO* at Secure EL1
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64). We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should report the 0x3 syndrome, not the
0x0 'uncategorized' syndrome. This is clear in the access pseudocode
for these instructions.
Fix the syndrome value for these operations by correcting the
returned value from the ats_access() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
Commit: 80ea70f2e53469b468598508513d50c5f80d6bb9
https://github.com/qemu/qemu/commit/80ea70f2e53469b468598508513d50c5f80d6bb9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
the ats_access() function, but doing so was incorrect (a bug fixed in
a previous commit). There aren't any cases where we want an access
function to be able to request a trap to EL2 or EL3 with a zero
syndrome value, so remove these enum values.
As well as cleaning up dead code, the motivation here is that
we'd like to implement fine-grained-trap handling in
helper_access_check_cp_reg(). Although the fine-grained traps
to EL2 are always lower priority than trap-to-same-EL and
higher priority than trap-to-EL3, they are in the middle of
various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
must always for us have the same syndrome (ie that an access
function will return CP_ACCESS_TRAP_EL2 and there is no other
kind of trap-to-EL2 enum value) means we don't have to try
to choose which of the two syndrome values to report if the
access would trap to EL2 both for the fine-grained-trap and
because the access function requires it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
Commit: 9ada333982c3d5ae4c15b8ba8dcfd7cb6cd6cb44
https://github.com/qemu/qemu/commit/9ada333982c3d5ae4c15b8ba8dcfd7cb6cd6cb44
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Move do_coproc_insn() syndrome calculation earlier
Rearrange the code in do_coproc_insn() so that we calculate the
syndrome value for a potential trap early; we're about to add a
second check that wants this value earlier than where it is currently
determined.
(Specifically, a trap to EL2 because of HSTR_EL2 should take
priority over an UNDEF to EL1, even when the UNDEF is because
the register does not exist at all or because its ri->access
bits non-configurably fail the access. So the check we put in
for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
going to have to be done before the check "is the ARMCPRegInfo
pointer NULL".)
This commit is just code motion; the change to HSTR_EL2
handling that will use the 'syndrome' variable is in a
subsequent commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org
Commit: cccc104bbfc02c741d4535be0184a6425399345d
https://github.com/qemu/qemu/commit/cccc104bbfc02c741d4535be0184a6425399345d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/op_helper.c
Log Message:
-----------
target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
The HSTR_EL2 register has a collection of trap bits which allow
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
registers. The specification of these bits is that when the bit is
set we should trap
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit is 0
In other words, all UNDEF traps from EL0 to EL1 take precedence over
the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind
of trap-to-EL1 is the UNDEF.)
Our implementation doesn't quite get this right -- we check for traps
in the order:
* no such register
* ARMCPRegInfo::access bits
* HSTR_EL2 trap bits
* ARMCPRegInfo::accessfn
So UNDEFs that happen because of the access bits or because the
register doesn't exist at all correctly take priority over the
HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
accessfn we are incorrectly always taking the HSTR_EL2 trap. There
aren't many of these, but one example is the PMCR; if you look at the
access pseudocode for this register you can see that UNDEFs taken
because of the value of PMUSERENR.EN are checked before the HSTR_EL2
bit.
Rearrange helper_access_check_cp_reg() so that we always call the
accessfn, and use its return value if it indicates that the access
traps to EL0 rather than continuing to do the HSTR_EL2 check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org
Commit: 049edada5e93df096c66a059e1171942238fc472
https://github.com/qemu/qemu/commit/049edada5e93df096c66a059e1171942238fc472
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/op_helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit is 0
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
HSTR_EL2 traps from EL0 are priority 15.)
However, we don't get this right for EL1 accesses which UNDEF because
the register doesn't exist at all or because its ri->access bits
non-configurably forbid the access. At EL1, check for the HSTR_EL2
trap early, before either of these UNDEF reasons.
We have to retain the HSTR_EL2 check in access_check_cp_reg(),
because at EL0 any kind of UNDEF-to-EL1 (including "no such
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
takes precedence over the trap to EL2. But we only need to do that
check for EL0 now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
Commit: 034bb45ac14602c757c1e9da32196ffa94459c79
https://github.com/qemu/qemu/commit/034bb45ac14602c757c1e9da32196ffa94459c79
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/helper.c
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
Commit: 15126d9ce2858f472d671960db30aed64fd4f694
https://github.com/qemu/qemu/commit/15126d9ce2858f472d671960db30aed64fd4f694
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Define the FEAT_FGT registers
Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
access. The R and W register pairs are for system registers,
allowing trapping to be done separately for reads and writes; the I
register is for system instructions where trapping is on instruction
execution.
The data storage in the CPU state struct is arranged as a set of
arrays rather than separate fields so that when we're looking up the
bits for a system register access we can just index into the array
rather than having to use a switch to select a named struct member.
The later FEAT_FGT2 will add extra elements to these arrays.
The field definitions for the new registers are in cpregs.h because
in practice the code that needs them is code that also needs
the cpregs information; cpu.h is included in a lot more files.
We're also going to add some FGT-specific definitions to cpregs.h
in the next commit.
We do not implement HAFGRTR_EL2, because we don't implement
FEAT_AMUv1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
Commit: 361c33f6b899a1ddb88a08dc99957419def6086d
https://github.com/qemu/qemu/commit/361c33f6b899a1ddb88a08dc99957419def6086d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement FGT trapping infrastructure
Implement the machinery for fine-grained traps on normal sysregs.
Any sysreg with a fine-grained trap will set the new field to
indicate which FGT register bit it should trap on.
FGT traps only happen when an AArch64 EL2 enables them for
an AArch64 EL1. They therefore are only relevant for AArch32
cpregs when the cpreg can be accessed from EL0. The logic
in access_check_cp_reg() will check this, so it is safe to
add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.
The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
which can be used to specify the FGT bit, eg
.fgt = FGT_AFSR0_EL1
(We assume that there is no bit name duplication across the FGT
registers, for brevity's sake.)
Subsequent commits will add the .fgt fields to the relevant register
definitions and define the FGT_nnn values for them.
Note that some of the FGT traps are for instructions that we don't
handle via the cpregs mechanisms (mostly these are instruction traps).
Those we will have to handle separately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
Commit: 158c276c7417da68ca46f2df88f1c1f9085eb895
https://github.com/qemu/qemu/commit/158c276c7417da68ca46f2df88f1c1f9085eb895
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGRTR bits 0..11
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
Commit: b19ed03c4cdf79efbdc5f2241e8cd20e1f11bd3c
https://github.com/qemu/qemu/commit/b19ed03c4cdf79efbdc5f2241e8cd20e1f11bd3c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGRTR bits 12..23
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 12..23.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
Commit: 67dd80306cd09ad6daf9570bca94095a743d3467
https://github.com/qemu/qemu/commit/67dd80306cd09ad6daf9570bca94095a743d3467
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGRTR bits 24..35
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 24..35.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
Commit: bd8db7d905d19dcd514ace40f41580501c80d51f
https://github.com/qemu/qemu/commit/bd8db7d905d19dcd514ace40f41580501c80d51f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGRTR bits 36..63
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.
Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.
Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
of the FEAT_LS64_ACCDATA feature which we don't yet implement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
Commit: 917b1405c1d87c7710f502661f47508d131ea2ca
https://github.com/qemu/qemu/commit/917b1405c1d87c7710f502661f47508d131ea2ca
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HDFGRTR bits 0..11
Mark up the sysreg definitons for the registers trapped
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
related registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org
Commit: dc780233b60c0e4144e09b01f7060075a3c8ff49
https://github.com/qemu/qemu/commit/dc780233b60c0e4144e09b01f7060075a3c8ff49
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HDFGRTR bits 12..63
Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.
Bits 12..22 and bit 58 are for PMU registers.
The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:
Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ETE
Bits 50..56 : FEAT_TRBE
Bits 59..61 : FEAT_BRBE
Bit 62 : FEAT_SPEv1p2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org
Commit: dd3456531924cfa892e44868b3de3b72459f78d9
https://github.com/qemu/qemu/commit/dd3456531924cfa892e44868b3de3b72459f78d9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGITR bits 0..11
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
Commit: 132c98cd93fba32e8535efae3a4675579b217ea1
https://github.com/qemu/qemu/commit/132c98cd93fba32e8535efae3a4675579b217ea1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGITR bits 12..17
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
Commit: bf2f0625f822f147f6a50204983c9945d416b338
https://github.com/qemu/qemu/commit/bf2f0625f822f147f6a50204983c9945d416b338
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGITR bits 18..47
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 18..47. These bits cover TLBI
TLB maintenance instructions.
(If we implemented FEAT_XS we would need to trap some of the
instructions added by that feature using these bits; but we don't
yet, so will need to add the .fgt markup when we do.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
Commit: 950037e280e80d9204a4bced5b6f4575b9c0d94b
https://github.com/qemu/qemu/commit/950037e280e80d9204a4bced5b6f4575b9c0d94b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Mark up sysregs for HFGITR bits 48..63
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.
Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
* ERET, ERETAA, ERETAB
* SVC
We will have to handle those separately and manually.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org
Commit: 5572f7557fdd1b5c36aee899b7e86fda66c2babf
https://github.com/qemu/qemu/commit/5572f7557fdd1b5c36aee899b7e86fda66c2babf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/syndrome.h
M target/arm/translate-a64.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement the HFGITR_EL2.ERET trap
Implement the HFGITR_EL2.ERET fine-grained trap. This traps
execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is
reported with a syndrome value of 0x1a.
The trap must take precedence over a possible pointer-authentication
trap for ERETAA and ERETAB.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
Commit: 34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54
https://github.com/qemu/qemu/commit/34a8a07e57bba6df2c1c67cc9bd3e80706ce4a54
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
Commit: 1748ef03c562dd4e5222e6d665142b25c0cfb1d1
https://github.com/qemu/qemu/commit/1748ef03c562dd4e5222e6d665142b25c0cfb1d1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents). This trapping is independent of whether
fine-grained traps are enabled or not.
Implement these extra traps. (We don't implement DBGDTR_EL0,
DBGDTRRX_EL0 and DBGDTRTX_EL0.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
Commit: bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6
https://github.com/qemu/qemu/commit/bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_FGT on '-cpu max'
Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
Commit: 0730eab4d38f74589da4a7d55814773260491f89
https://github.com/qemu/qemu/commit/0730eab4d38f74589da4a7d55814773260491f89
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
M docs/system/arm/emulation.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M hw/char/pl011.c
M hw/intc/arm_gicv3_cpuif.c
M include/hw/arm/virt.h
M include/hw/char/pl011.h
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/hvf/trace-events
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/ptw.c
M target/arm/syndrome.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge tag 'pull-target-arm-20230203' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix physical address resolution for Stage2
* pl011: refactoring, implement reset method
* Support GICv3 with hvf acceleration
* sbsa-ref: remove cortex-a76 from list of supported cpus
* Correct syndrome for ATS12NSO* traps at Secure EL1
* Fix priority of HSTR_EL2 traps vs UNDEFs
* Implement FEAT_FGT for '-cpu max'
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# gpg: Signature made Fri 03 Feb 2023 14:28:59 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230203' of
https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
target/arm: Enable FEAT_FGT on '-cpu max'
target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
target/arm: Implement the HFGITR_EL2.ERET trap
target/arm: Mark up sysregs for HFGITR bits 48..63
target/arm: Mark up sysregs for HFGITR bits 18..47
target/arm: Mark up sysregs for HFGITR bits 12..17
target/arm: Mark up sysregs for HFGITR bits 0..11
target/arm: Mark up sysregs for HDFGRTR bits 12..63
target/arm: Mark up sysregs for HDFGRTR bits 0..11
target/arm: Mark up sysregs for HFGRTR bits 36..63
target/arm: Mark up sysregs for HFGRTR bits 24..35
target/arm: Mark up sysregs for HFGRTR bits 12..23
target/arm: Mark up sysregs for HFGRTR bits 0..11
target/arm: Implement FGT trapping infrastructure
target/arm: Define the FEAT_FGT registers
target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
target/arm: Move do_coproc_insn() syndrome calculation earlier
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5736527050cf...0730eab4d38f