[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 91e012: nbd: use a QemuMutex to synchronize y
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 91e012: nbd: use a QemuMutex to synchronize yanking, recon... |
|
Date: |
Tue, 19 Jul 2022 05:00:33 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 91e01228b9610cb556a26723dc659d3659bee56c
https://github.com/qemu/qemu/commit/91e01228b9610cb556a26723dc659d3659bee56c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/nbd.c
Log Message:
-----------
nbd: use a QemuMutex to synchronize yanking, reconnection and coroutines
The condition for waiting on the s->free_sema queue depends on
both s->in_flight and s->state. The latter is currently using
atomics, but this is quite dubious and probably wrong.
Because s->state is written in the main thread too, for example by
the yank callback, it cannot be protected by a CoMutex. Introduce a
separate lock that can be used by nbd_co_send_request(); later on this
lock will also be used for s->state. There will not be any contention
on the lock unless there is a yank or reconnect, so this is not
performance sensitive.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414175756.671165-6-pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: a57d9c043a42f2a5dd2bca7201a9d7ae5437336c
https://github.com/qemu/qemu/commit/a57d9c043a42f2a5dd2bca7201a9d7ae5437336c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/nbd.c
Log Message:
-----------
nbd: code motion and function renaming
Prepare for the next patch, so that the diff is less confusing.
nbd_client_connecting is moved closer to the definition point.
nbd_client_connecting_wait() is kept only for the reconnection
logic; when it is used to check if a request has to be reissued,
use the renamed function nbd_client_will_reconnect(). In the
next patch, the two cases will have different locking requirements.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414175756.671165-7-pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 19a2751672b4668c3e67c79f74b6bb6b0fc59d06
https://github.com/qemu/qemu/commit/19a2751672b4668c3e67c79f74b6bb6b0fc59d06
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/nbd.c
Log Message:
-----------
nbd: move s->state under requests_lock
Remove the confusing, and most likely wrong, atomics. The only function
that used to be somewhat in a hot path was nbd_client_connected(),
but it is not anymore after the previous patches.
The same logic is used both to check if a request had to be reissued
and also in nbd_reconnecting_attempt(). The former cases are outside
requests_lock, while nbd_reconnecting_attempt() does have the lock,
therefore the two have been separated in the previous commit.
nbd_client_will_reconnect() can simply take s->requests_lock, while
nbd_reconnecting_attempt() can inline the access now that no
complicated atomics are involved.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414175756.671165-8-pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: ef2cd9471cbe0f6a241fd04d0f8c1b7805d2f8d3
https://github.com/qemu/qemu/commit/ef2cd9471cbe0f6a241fd04d0f8c1b7805d2f8d3
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/nbd.c
Log Message:
-----------
nbd: take receive_mutex when reading requests[].receiving
requests[].receiving is set by nbd_receive_replies() under the receive_mutex;
Read it under the same mutex as well. Waking up receivers on errors happens
after each reply finishes processing, in nbd_co_receive_one_chunk().
If there is no currently-active reply, there are two cases:
* either there is no active request at all, in which case no
element of request[] can have .receiving = true
* or nbd_receive_replies() must be running and owns receive_mutex;
in that case it will get back to nbd_co_receive_one_chunk() because
the socket has been shutdown, and all waiting coroutines will wake up
in turn.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414175756.671165-9-pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: dda8940d790c6ffd7075006fb7cdc2ab7830d1f4
https://github.com/qemu/qemu/commit/dda8940d790c6ffd7075006fb7cdc2ab7830d1f4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/nbd.c
Log Message:
-----------
nbd: document what is protected by the CoMutexes
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414175756.671165-10-pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 5471a695cfbdbfe8e77d2b0e07746986784fa9b9
https://github.com/qemu/qemu/commit/5471a695cfbdbfe8e77d2b0e07746986784fa9b9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Assert mmu_idx in range before use in cputlb
Coverity reports out-of-bound accesses within cputlb.c.
This should be a false positive due to how the index is
decoded from MemOpIdx. To be fair, nothing is checking
the correct bounds during encoding either.
Assert index in range before use, both to catch user errors
and to pacify static analysis.
Fixes: Coverity CID 1487120, 1487127, 1487170, 1487196, 1487215, 1487238
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220401170813.318609-1-richard.henderson@linaro.org>
Commit: c0186d829f00c474b0f7a87388490f4ad622e496
https://github.com/qemu/qemu/commit/c0186d829f00c474b0f7a87388490f4ad622e496
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Fix the accumulation of ccm in op_icm
Coverity rightly reports that 0xff << pos can overflow.
This would affect the ICMH instruction.
Fixes: Coverity CID 1487161
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220401193659.332079-1-richard.henderson@linaro.org>
Commit: 401f81a3c25f6ed087b97263ea1fe75543b06fdd
https://github.com/qemu/qemu/commit/401f81a3c25f6ed087b97263ea1fe75543b06fdd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: Suppress coverity warning on fsave/frstor
Coverity warns that 14 << data32 may overflow with respect
to the target_ulong to which it is subsequently added.
We know this wasn't true because data32 is in [1,2],
but the suggested fix is perfectly fine.
Fixes: Coverity CID 1487135, 1487256
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-Id: <20220401184635.327423-1-richard.henderson@linaro.org>
Commit: ef520c9ddd459ab6fd1f3bae41ab06c06120dcb4
https://github.com/qemu/qemu/commit/ef520c9ddd459ab6fd1f3bae41ab06c06120dcb4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix declaration of partsN_compare
The declaration used 'int', while the definition used 'FloatRelation'.
This should have resulted in a compiler error, but mysteriously didn't.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220401132240.79730-2-richard.henderson@linaro.org>
Commit: b93274714986bfd317b36c56e1806fd7f07c10fc
https://github.com/qemu/qemu/commit/b93274714986bfd317b36c56e1806fd7f07c10fc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M fpu/softfloat-parts.c.inc
Log Message:
-----------
softfloat: Use FloatRelation within partsN_compare
As the return type is FloatRelation, it's clearer to
use the type for 'cmp' within the function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220401132240.79730-3-richard.henderson@linaro.org>
Commit: 9f697feb5895d75908fc2ae98117e80af4b7f1d5
https://github.com/qemu/qemu/commit/9f697feb5895d75908fc2ae98117e80af4b7f1d5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Use FloatRelation for fracN_cmp
Since the caller, partsN_compare, is now exclusively
using FloatRelation, it's clearer to use it here too.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220401132240.79730-4-richard.henderson@linaro.org>
Commit: 65001d3a1553064302d7e10a670ba22b184104c5
https://github.com/qemu/qemu/commit/65001d3a1553064302d7e10a670ba22b184104c5
Author: Carwyn Ellis <carwynellis@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/display/trace-events
M hw/display/vmware_vga.c
Log Message:
-----------
hw/display/vmware_vga: do not discard screen updates
In certain circumstances, typically when there is lots changing on the
screen, updates will be discarded resulting in garbled output.
This change simplifies the traversal of the display update FIFO queue
when applying updates. We just track the queue length and iterate up to
the end of the queue.
Additionally when adding updates to the queue, if the buffer reaches
capacity we force a flush before accepting further events.
Signed-off-by: Carwyn Ellis <carwynellis@gmail.com>
Message-Id: <20220206183956.10694-3-carwynellis@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: 67ea81bdcf6bf91c095898b0ac3dab217251ade4
https://github.com/qemu/qemu/commit/67ea81bdcf6bf91c095898b0ac3dab217251ade4
Author: Kshitij Suri <kshitij.suri@nutanix.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson.build
M meson_options.txt
M scripts/ci/org.centos/stream/8/x86_64/configure
M scripts/coverity-scan/run-coverity-scan
M scripts/meson-buildoptions.sh
M ui/vnc-enc-tight.c
M ui/vnc.c
M ui/vnc.h
Log Message:
-----------
Replacing CONFIG_VNC_PNG with CONFIG_PNG
Libpng is only detected if VNC is enabled currently. This patch adds a
generalised png option in the meson build which is aimed to replace use of
CONFIG_VNC_PNG with CONFIG_PNG.
Signed-off-by: Kshitij Suri <kshitij.suri@nutanix.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220408071336.99839-2-kshitij.suri@nutanix.com>
[ kraxel: add meson-buildoptions.sh updates ]
[ kraxel: fix centos8 testcase ]
[ kraxel: update --enable-vnc-png too ]
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
--enable-vnc-png fixup
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: e8e8159149e0778cd0be5e2d34abac601c90b962
https://github.com/qemu/qemu/commit/e8e8159149e0778cd0be5e2d34abac601c90b962
Author: Kshitij Suri <kshitij.suri@nutanix.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hmp-commands.hx
M monitor/hmp-cmds.c
M qapi/ui.json
M ui/console.c
Log Message:
-----------
Added parameter to take screenshot with screendump as PNG
Currently screendump only supports PPM format, which is un-compressed. Added
a "format" parameter to QMP and HMP screendump command to support PNG image
capture using libpng.
QMP example usage:
{ "execute": "screendump", "arguments": { "filename": "/tmp/image",
"format":"png" } }
HMP example usage:
screendump /tmp/image -f png
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/718
Signed-off-by: Kshitij Suri <kshitij.suri@nutanix.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20220408071336.99839-3-kshitij.suri@nutanix.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: f22adbfb6d7b6010c8b95c8681bfcd4ad9caad80
https://github.com/qemu/qemu/commit/f22adbfb6d7b6010c8b95c8681bfcd4ad9caad80
Author: Vladimir Sementsov-Ogievskiy <vladimir.sementsov-ogievskiy@openvz.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M ui/vnc.c
Log Message:
-----------
ui/vnc: refactor arrays of addresses to SocketAddressList
Let's use SocketAddressList instead of dynamic arrays.
Benefits:
- Automatic cleanup: don't need specific freeing function and drop
some gotos.
- Less indirection: no triple asterix anymore!
- Prepare for the following commit, which will reuse new interface of
vnc_display_listen().
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220401143936.356460-2-vsementsov@openvz.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: 9eac1f4da536c5d0a64c2695e5d210b960791d03
https://github.com/qemu/qemu/commit/9eac1f4da536c5d0a64c2695e5d210b960791d03
Author: Vladimir Sementsov-Ogievskiy <vladimir.sementsov-ogievskiy@openvz.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/about/removed-features.rst
M include/ui/console.h
M monitor/qmp-cmds.c
M qapi/ui.json
M ui/vnc.c
Log Message:
-----------
qapi/ui: add 'display-update' command for changing listen address
Add possibility to change addresses where VNC server listens for new
connections. Prior to 6.0 this functionality was available through
'change' qmp command which was deleted.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220401143936.356460-3-vsementsov@openvz.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: 1a0470aab3a372a7b794a2c4316a073bf558a42a
https://github.com/qemu/qemu/commit/1a0470aab3a372a7b794a2c4316a073bf558a42a
Author: Vladimir Sementsov-Ogievskiy <vladimir.sementsov-ogievskiy@openvz.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/avocado/vnc.py
Log Message:
-----------
avocado/vnc: add test_change_listen
Add simple test-case for new display-update qmp command.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@openvz.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220401143936.356460-4-vsementsov@openvz.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: e4dbe19cca3437270e392916d410aae13bd65daf
https://github.com/qemu/qemu/commit/e4dbe19cca3437270e392916d410aae13bd65daf
Author: Gerd Hoffmann <kraxel@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/i386/x86.c
Log Message:
-----------
i386: move bios load error message
Switch to usual goto-end-of-function error handling style.
No functional change.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220425135051.551037-2-kraxel@redhat.com>
Commit: 49ead6755a4ff551526548f316dc46af07fcedf2
https://github.com/qemu/qemu/commit/49ead6755a4ff551526548f316dc46af07fcedf2
Author: Gerd Hoffmann <kraxel@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/i386/pc_sysfw.c
M include/hw/i386/x86.h
Log Message:
-----------
i386: factor out x86_firmware_configure()
move sev firmware setup to separate function so it can be used from
other code paths. No functional change.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220425135051.551037-3-kraxel@redhat.com>
Commit: 9c97e69ad6cd3c327c66a425e77e73126e6432c8
https://github.com/qemu/qemu/commit/9c97e69ad6cd3c327c66a425e77e73126e6432c8
Author: Gerd Hoffmann <kraxel@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/i386/x86.c
Log Message:
-----------
i386: firmware parsing and sev setup for -bios loaded firmware
Don't register firmware as rom, not needed (see comment).
Add x86_firmware_configure() call for proper sev initialization.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220425135051.551037-4-kraxel@redhat.com>
Commit: 6b611070513d56c54f49b6d7ead2cb1785b456f1
https://github.com/qemu/qemu/commit/6b611070513d56c54f49b6d7ead2cb1785b456f1
Author: Haiyue Wang <haiyue.wang@intel.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M util/error-report.c
Log Message:
-----------
error-report: fix g_date_time_format assertion
The 'g_get_real_time' returns the number of microseconds since January
1, 1970 UTC, but 'g_date_time_new_from_unix_utc' needs the number of
seconds, so it will cause the invalid time input:
(process:279642): GLib-CRITICAL (recursed) **: g_date_time_format: assertion
'datetime != NULL' failed
Call function 'g_date_time_new_now_utc' instead, it has the same result
as 'g_date_time_new_from_unix_utc(g_get_real_time() / G_USEC_PER_SEC)';
Fixes: 73dab893b569 ("error-report: replace deprecated g_get_current_time()
with glib >= 2.62")
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220424105036.291370-1-haiyue.wang@intel.com>
Commit: f90129a8aba38e773ac10883a9c7ee880490d6e4
https://github.com/qemu/qemu/commit/f90129a8aba38e773ac10883a9c7ee880490d6e4
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: make fortify_source=yes by default
Commit c87ea1163111917 "configure: add --without-default-feature"
changed fortify_source from "yes" to "$default_feature". But there's
no option to turn it on, we only turn it off for debug build. I think
this should always be initialized to "yes" in the first place.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20220422100825.3692002-1-mjt@msgid.tls.msk.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cc960b759c280e0f6788b2dd414721b9fee18708
https://github.com/qemu/qemu/commit/cc960b759c280e0f6788b2dd414721b9fee18708
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M include/qemu/config-file.h
M qemu-options.hx
M softmmu/vl.c
M util/qemu-config.c
Log Message:
-----------
remove -writeconfig
Like -set and -readconfig, it would not really be too hard to
extend -writeconfig to parsing mechanisms other than QemuOpts.
However, the uses of -writeconfig are substantially more
limited, as it is generally easier to write the configuration
by hand in the first place. In addition, -writeconfig does
not even try to detect cases where it prints incorrect
syntax (for example if values have a quote in them, since
qemu_config_parse does not support any kind of escaping.
Just remove it.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414145721.326866-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 205a79b51891c73e934aacdbba6cec3251be0e84
https://github.com/qemu/qemu/commit/205a79b51891c73e934aacdbba6cec3251be0e84
Author: Paul Brook <paul@nowt.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/i386/ops_sse.h
Log Message:
-----------
i386: pcmpestr 64-bit sign extension bug
The abs1 function in ops_sse.h only works sorrectly when the result fits
in a signed int. This is fine most of the time because we're only dealing
with byte sized values.
However pcmp_elen helper function uses abs1 to calculate the absolute value
of a cpu register. This incorrectly truncates to 32 bits, and will give
the wrong anser for the most negative value.
Fix by open coding the saturation check before taking the absolute value.
Signed-off-by: Paul Brook <paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: dfe3fc498af6d8cb8c4fff839b4a5b571d0f74e0
https://github.com/qemu/qemu/commit/dfe3fc498af6d8cb8c4fff839b4a5b571d0f74e0
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson: show final set of compiler flags
The actual set of compiler flags can grow beyond what is found by the configure
script, for example if gprof is used. Show the full set in the summary.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: aa902c85d2504fc308f03d406f2867053dbcfe36
https://github.com/qemu/qemu/commit/aa902c85d2504fc308f03d406f2867053dbcfe36
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: remove dead code
tcg_interpreter is never written, it is purely a meson option;
trace_backends is never read.
And SeaBIOS is only build from the source tree with roms/Makefile,
so the config.mak file is unused.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 20558743e452f5f5b1874f2038fe40f5f22260e1
https://github.com/qemu/qemu/commit/20558743e452f5f5b1874f2038fe40f5f22260e1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M qga/meson.build
Log Message:
-----------
qga: wixl: get path to sysroot from pkg-config as intended
The .wxs file uses $(var.Mingw_bin) while configure/meson have always
used Mingw_dlls. Fix them to match what was probably intended.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bfd1348114c4cc644a67ba07823f25e4c87da788
https://github.com/qemu/qemu/commit/bfd1348114c4cc644a67ba07823f25e4c87da788
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: pc-bios/qemu-icon.bmp does not exist
The file has been removed in commit a8260d3876 ("ui: install logo icons to
$prefix/share/icons", 2019-01-21), do not try to symlink it in the build tree.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 362a7f46081918183d45c8825cdb8b8ee7ee7e8a
https://github.com/qemu/qemu/commit/362a7f46081918183d45c8825cdb8b8ee7ee7e8a
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: gcov should not exclude fortify-source
There is no reason other than history (dating back to commit 1d728c3946,
"tests: add gcov
support", 2013-01-06) for this, remove this unnecessary conditional.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ca7a5c346d9afc4a80ebf2d1f9a1a3d6f82f8fbf
https://github.com/qemu/qemu/commit/ca7a5c346d9afc4a80ebf2d1f9a1a3d6f82f8fbf
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: move --enable/--disable-debug-info to second option parsing pass
$debug_info is not needed anywhere except in the final meson invocation,
no need to special case it.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: be78ad0dcb39c5f1a39959e1434ff37ad104cf48
https://github.com/qemu/qemu/commit/be78ad0dcb39c5f1a39959e1434ff37ad104cf48
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
M ui/meson.build
Log Message:
-----------
configure, meson: move OpenGL check to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 338b11f235ea5eaaa240d8272729276cb234ffc7
https://github.com/qemu/qemu/commit/338b11f235ea5eaaa240d8272729276cb234ffc7
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M contrib/rdmacm-mux/meson.build
M meson.build
M meson_options.txt
M migration/meson.build
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move RDMA options to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 61ea618a5e13de36b319f5cb7625bdc2636064f7
https://github.com/qemu/qemu/commit/61ea618a5e13de36b319f5cb7625bdc2636064f7
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M crypto/meson.build
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move keyctl test to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cfee92839c1d1dd74ad12ad86b2bd34a06f7db69
https://github.com/qemu/qemu/commit/cfee92839c1d1dd74ad12ad86b2bd34a06f7db69
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
Log Message:
-----------
meson, configure: move usbfs test to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6ef18cfc2f3862a98f06d22898762a5c773d4eb9
https://github.com/qemu/qemu/commit/6ef18cfc2f3862a98f06d22898762a5c773d4eb9
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M backends/meson.build
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
M tests/qtest/meson.build
M ui/meson.build
M util/meson.build
Log Message:
-----------
meson, configure: move libgio test to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c98f5b34f3c3f1356c6c118c7a583a9e170e673b
https://github.com/qemu/qemu/commit/c98f5b34f3c3f1356c6c118c7a583a9e170e673b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/xen/meson.build
M meson.build
Log Message:
-----------
meson: remove CONFIG_XEN_PCI_PASSTHROUGH from config-target.h
CONFIG_XEN_PCI_PASSTHROUGH is just a global configuration option;
it is never used in the source files, so there is no need to put
CONFIG_XEN_PCI_PASSTHROUGH in config-target.h or even in config-host.h.
This inaccuracy was copied over from the configure script in commit
8a19980e3f ("configure: move accelerator logic to meson", 2020-10-03).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 888f733b8f9e1b5d4b8eeff4a72797202dde2acd
https://github.com/qemu/qemu/commit/888f733b8f9e1b5d4b8eeff4a72797202dde2acd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move --enable-module-upgrades to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1801e221f68ff4a13c8c8e0575ce52dbfe5942d6
https://github.com/qemu/qemu/commit/1801e221f68ff4a13c8c8e0575ce52dbfe5942d6
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options: Limit the -enable-kvm option to the targets that support it
There is no need to present the user with -enable-kvm if there
is no support for KVM on the corresponding target.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220427134906.348118-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 48ec11ae3e046d2716dd7f590c73557b22744da9
https://github.com/qemu/qemu/commit/48ec11ae3e046d2716dd7f590c73557b22744da9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in gen_probe_access
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d57c96f6a35e96ff824ae8e919f42dcbaa3637ca
https://github.com/qemu/qemu/commit/d57c96f6a35e96ff824ae8e919f42dcbaa3637ca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in gen_mte_check*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd44c26e898dec098aad68249d6520391c577ff3
https://github.com/qemu/qemu/commit/cd44c26e898dec098aad68249d6520391c577ff3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in gen_exception*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6ffa29c64693e301695eaf522226e5e28ce7c707
https://github.com/qemu/qemu/commit/6ffa29c64693e301695eaf522226e5e28ce7c707
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in gen_adc_CC
Note that tmp was doing double-duty as zero
and then later as a temporary in its own right.
Split the use of 0 to a new variable 'zero'.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 93a6e85f34ffd413dbb15007caf36945f6784923
https://github.com/qemu/qemu/commit/93a6e85f34ffd413dbb15007caf36945f6784923
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in handle_msr_i
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 166b4f30c65a5ff7ccd45b268398700570e1f512
https://github.com/qemu/qemu/commit/166b4f30c65a5ff7ccd45b268398700570e1f512
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in handle_sys
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e1d1f03bdcb47f2d45cda72c5cb937f0e5faa019
https://github.com/qemu/qemu/commit/e1d1f03bdcb47f2d45cda72c5cb937f0e5faa019
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_exc
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 97001a3505a6286bff12687a07ade4a5e4a8736c
https://github.com/qemu/qemu/commit/97001a3505a6286bff12687a07ade4a5e4a8736c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in gen_compare_and_swap_pair
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 579144dec57ed0c55d3351048f5188b0310aefa4
https://github.com/qemu/qemu/commit/579144dec57ed0c55d3351048f5188b0310aefa4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_ld_lit
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c9e6549a52e7370d3a6a4f9c8a053d66741e1eb6
https://github.com/qemu/qemu/commit/c9e6549a52e7370d3a6a4f9c8a053d66741e1eb6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_ldst_*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 557e67f7bd083ec8a4a18e2d700b676a9dbcec05
https://github.com/qemu/qemu/commit/557e67f7bd083ec8a4a18e2d700b676a9dbcec05
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_add_sum_imm*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6e92fede80c0ce7140157bf14bf3c41a1265e2c7
https://github.com/qemu/qemu/commit/6e92fede80c0ce7140157bf14bf3c41a1265e2c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_movw_imm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: abe0eeb0b4b16d9408fa679541e0532e125a27b9
https://github.com/qemu/qemu/commit/abe0eeb0b4b16d9408fa679541e0532e125a27b9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in shift_reg_imm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9feac26a3dd81ec547210fa943212ab9e5c6a55a
https://github.com/qemu/qemu/commit/9feac26a3dd81ec547210fa943212ab9e5c6a55a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_cond_select
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 14c362b378493edaf6451c1909e48ac3917e7acb
https://github.com/qemu/qemu/commit/14c362b378493edaf6451c1909e48ac3917e7acb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in handle_{rev16,crc32}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 447338b8268851558f258e3effb210af0ba861de
https://github.com/qemu/qemu/commit/447338b8268851558f258e3effb210af0ba861de
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_data_proc_2src
Existing temp usage treats t1 as both zero and as a
temporary. Rearrange to only require one temporary,
so remove t1 and rename t2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d4ce2af61700e59a3b603b91c8728d3ad462314f
https://github.com/qemu/qemu/commit/d4ce2af61700e59a3b603b91c8728d3ad462314f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in disas_fp*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-18-richard.henderson@linaro.org
[PMM: Restore incorrectly removed free of t_false in disas_fp_csel()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 917f9b10d5d6de40aa951e9d54f9dde4510b8897
https://github.com/qemu/qemu/commit/917f9b10d5d6de40aa951e9d54f9dde4510b8897
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in simd shift expanders
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 262b6984ba3ce2a3e0ad9507d9c2cf6124f4425e
https://github.com/qemu/qemu/commit/262b6984ba3ce2a3e0ad9507d9c2cf6124f4425e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in simd fp/int conversion
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b32a0694d06bd2a0d29efdb3c0b567995e6a86f4
https://github.com/qemu/qemu/commit/b32a0694d06bd2a0d29efdb3c0b567995e6a86f4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in 2misc expanders
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f2974186bc67fa4ca6af1635303c27c36ced5d5e
https://github.com/qemu/qemu/commit/f2974186bc67fa4ca6af1635303c27c36ced5d5e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_constant in balance of translate-a64.c
Finish conversion of the file to tcg_constant_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e51add690be3c718e2e70367391172e45d3cf72b
https://github.com/qemu/qemu/commit/e51add690be3c718e2e70367391172e45d3cf72b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for aa32 exceptions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 52c969134e70cdc9d691d71c7f7e00533914816a
https://github.com/qemu/qemu/commit/52c969134e70cdc9d691d71c7f7e00533914816a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for disas_iwmmxt_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5bb720c8b4cc5e96dbfb57039195efbd4dc17654
https://github.com/qemu/qemu/commit/5bb720c8b4cc5e96dbfb57039195efbd4dc17654
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for gen_{msr,mrs}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ce49411c551e584092b526f6f4d3dfe8324e9c07
https://github.com/qemu/qemu/commit/ce49411c551e584092b526f6f4d3dfe8324e9c07
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for vector shift expanders
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7129451994aaa8f95b9c45091a184fc4a8e3e12f
https://github.com/qemu/qemu/commit/7129451994aaa8f95b9c45091a184fc4a8e3e12f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for do_coproc_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 182bcdc6b8ac9ffe49abe302d380c7de1bfbba2b
https://github.com/qemu/qemu/commit/182bcdc6b8ac9ffe49abe302d380c7de1bfbba2b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for gen_srs
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 96cd6d47b289b9e369fe0c4cba2fced2f38c4599
https://github.com/qemu/qemu/commit/96cd6d47b289b9e369fe0c4cba2fced2f38c4599
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3332153cd23fda816a1ced8093ef6bac8e6a32af
https://github.com/qemu/qemu/commit/3332153cd23fda816a1ced8093ef6bac8e6a32af
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f87052cdcefd5ac315ad745debbed42a69bcc894
https://github.com/qemu/qemu/commit/f87052cdcefd5ac315ad745debbed42a69bcc894
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for v7m MRS, MSR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8f56c1bf7bcb31381b4cc988235a9e601f8cde93
https://github.com/qemu/qemu/commit/8f56c1bf7bcb31381b4cc988235a9e601f8cde93
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant for TT, SAT, SMMLA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7fd4f83957de0a249aa9c26b93e68ef8618a8cdd
https://github.com/qemu/qemu/commit/7fd4f83957de0a249aa9c26b93e68ef8618a8cdd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant in LDM, STM
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dbd3ed2b7738c218a58a64fc23a2622d58cd3073
https://github.com/qemu/qemu/commit/dbd3ed2b7738c218a58a64fc23a2622d58cd3073
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aaef4f6830fa82451c69ed2d4519e8a6abb63942
https://github.com/qemu/qemu/commit/aaef4f6830fa82451c69ed2d4519e8a6abb63942
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant in trans_CPS_v7m
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c77818f5219adae1cee87f4eeeee69df126f516d
https://github.com/qemu/qemu/commit/c77818f5219adae1cee87f4eeeee69df126f516d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use tcg_constant in trans_CSEL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 267b0a5913b5a395fb10dd4fe88f2af86daa2b21
https://github.com/qemu/qemu/commit/267b0a5913b5a395fb10dd4fe88f2af86daa2b21
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant for trans_INDEX_*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 48c63b57f4b7ceef1c755446ca20bc4b1faad8bf
https://github.com/qemu/qemu/commit/48c63b57f4b7ceef1c755446ca20bc4b1faad8bf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in SINCDEC, INCDEC
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b12815dbf73cd9b2feed21b7514e0471e5021399
https://github.com/qemu/qemu/commit/b12815dbf73cd9b2feed21b7514e0471e5021399
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in FCPY, CPY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e54ecada50e9dd5df8cccf5cc5aaff811f92431f
https://github.com/qemu/qemu/commit/e54ecada50e9dd5df8cccf5cc5aaff811f92431f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in {incr, wrap}_last_active
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4bf8b01d130cce9a1ebf94ff65c80c3cdb30bd63
https://github.com/qemu/qemu/commit/4bf8b01d130cce9a1ebf94ff65c80c3cdb30bd63
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in do_clast_scalar
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f656be4dce0672b431fe583b6ae0227f4816468f
https://github.com/qemu/qemu/commit/f656be4dce0672b431fe583b6ae0227f4816468f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in WHILE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2b672d5fef45f760cd6a332b31a91354ea66b8c7
https://github.com/qemu/qemu/commit/2b672d5fef45f760cd6a332b31a91354ea66b8c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in LD1, ST1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7b421a94582101428a7bb7422cbfe685d86f1635
https://github.com/qemu/qemu/commit/7b421a94582101428a7bb7422cbfe685d86f1635
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in SUBR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 68b8b41a6fa6442e7fda005fd2f5600df77d8dc3
https://github.com/qemu/qemu/commit/68b8b41a6fa6442e7fda005fd2f5600df77d8dc3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f3dba1f699627a0c65c355aa9fef4e8af855b91e
https://github.com/qemu/qemu/commit/f3dba1f699627a0c65c355aa9fef4e8af855b91e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant for predicate descriptors
In these cases, 't' did double-duty as zero source and
temporary destination. Split the two uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b7089b2774c1f7f4dfa4a2ef05d81e12e63555a1
https://github.com/qemu/qemu/commit/b7089b2774c1f7f4dfa4a2ef05d81e12e63555a1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant for do_brk{2,3}
In these cases, 't' did double-duty as zero source and
temporary destination. Split the two uses and narrow
the scope of the temp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-47-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8e946bebfd869fd46d4b98edbc3d192b0742de89
https://github.com/qemu/qemu/commit/8e946bebfd869fd46d4b98edbc3d192b0742de89
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_constant for vector descriptor
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-48-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3c35c70f066931a19828843cb0b10f84b8cf4dd9
https://github.com/qemu/qemu/commit/3c35c70f066931a19828843cb0b10f84b8cf4dd9
Author: Damien Hedde <damien.hedde@greensocs.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Disable cryptographic instructions when neon is disabled
As of now, cryptographic instructions ISAR fields are never cleared so
we can end up with a cpu with cryptographic instructions but no
floating-point/neon instructions which is not a possible configuration
according to Arm specifications.
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
+ no support
+ cortex-a57/a72: cryptographic extension is optional,
floating-point/neon is not.
+ cortex-a53: crytographic extension is optional as well as
floating-point/neon. But cryptographic requires
floating-point/neon support.
Therefore we can safely clear the ISAR fields when neon is disabled.
Note that other Arm cpus seem to follow this. For example cortex-a55 is
like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220427090117.6954-1-damien.hedde@greensocs.com
[PMM: fixed commit message typos]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7b70ce6525115e6bf3c0cb48f97184e974ba0f9f
https://github.com/qemu/qemu/commit/7b70ce6525115e6bf3c0cb48f97184e974ba0f9f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Use field names for accessing DBGWCRn
While defining these names, use the correct field width of 5 not 4 for
DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k.
Reported-by: Chris Howard <cvz185@web.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220427051926.295223-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ca9c54599aae5c18ec1041d384200ebcd2b7d156
https://github.com/qemu/qemu/commit/ca9c54599aae5c18ec1041d384200ebcd2b7d156
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Cache event fault record
The Record bit in the Context Descriptor tells the SMMU to report fault
events to the event queue. Since we don't cache the Record bit at the
moment, access faults from a cached Context Descriptor are never
reported. Store the Record bit in the cached SMMUTransCfg.
Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220427111543.124620-1-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 37d01b6d150e3c25b429293e13c787feaf1a0255
https://github.com/qemu/qemu/commit/37d01b6d150e3c25b429293e13c787feaf1a0255
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Add space in guest error message
Make the translation error message prettier by adding a missing space
before the parenthesis.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220427111543.124620-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b1698f239daa98ab360bc5b7fcdbdc8bf48fef4b
https://github.com/qemu/qemu/commit/b1698f239daa98ab360bc5b7fcdbdc8bf48fef4b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Advertise support for FEAT_TTL
The Arm FEAT_TTL architectural feature allows the guest to provide an
optional hint in an AArch64 TLB invalidate operation about which
translation table level holds the leaf entry for the address being
invalidated. QEMU's TLB implementation doesn't need that hint, and
we correctly ignore the (previously RES0) bits in TLB invalidate
operation values that are now used for the TTL field. So we can
simply advertise support for it in our 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
Commit: 88ddf5b224e4253a79a30eef6382aa0f80e6274e
https://github.com/qemu/qemu/commit/88ddf5b224e4253a79a30eef6382aa0f80e6274e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Advertise support for FEAT_BBM level 2
The description in the Arm ARM of the requirements of FEAT_BBM is
admirably clear on the guarantees it provides software, but slightly
more obscure on what that means for implementations. The description
of the equivalent SMMU feature in the SMMU specification (IHI0070D.b
section 3.21.1) is perhaps a bit more detailed and includes some
example valid implementation choices. (The SMMU version of this
feature is slightly tighter than the CPU version: the CPU is permitted
to raise TLB Conflict aborts in some situations that the SMMU may
not. This doesn't matter for QEMU because we don't want to do TLB
Conflict aborts anyway.)
The informal summary of FEAT_BBM is that it is about permitting an OS
to switch a range of memory between "covered by a huge page" and
"covered by a sequence of normal pages" without having to engage in
the 'break-before-make' dance that has traditionally been
necessary. The 'break-before-make' sequence is:
* replace the old translation table entry with an invalid entry
* execute a DSB insn
* execute a broadcast TLB invalidate insn
* execute a DSB insn
* write the new translation table entry
* execute a DSB insn
The point of this is to ensure that no TLB can simultaneously contain
TLB entries for the old and the new entry, which would traditionally
be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault
or to use a random mishmash of values from the old and the new
entry). FEAT_BBM level 2 says "for the specific case where the only
thing that changed is the size of the block, the TLB is guaranteed
not to do weird things even if there are multiple entries for an
address", which means that software can now do:
* replace old translation table entry with new entry
* DSB
* broadcast TLB invalidate
* DSB
As the SMMU spec notes, valid ways to do this include:
* if there are multiple entries in the TLB for an address,
choose one of them and use it, ignoring the others
* if there are multiple entries in the TLB for an address,
throw them all out and do a page table walk to get a new one
QEMU's page table walk implementation for Arm CPUs already meets the
requirements for FEAT_BBM level 2. When we cache an entry in our TCG
TLB, we do so only for the specific (non-huge) page that the address
is in, and there is no way for the TLB data structure to ever have
more than one TLB entry for that page. (We handle huge pages only in
that we track what part of the address space is covered by huge pages
so that a TLB invalidate operation for an address in a huge page
results in an invalidation of the whole TLB.) We ignore the Contiguous
bit in page table entries, so we don't have to do anything for the
parts of FEAT_BBM that deal with changis to the Contiguous bit.
FEAT_BBM level 2 also requires that the nT bit in block descriptors
must be ignored; since commit 39a1fd25287f5dece5 we do this.
It's therefore safe for QEMU to advertise FEAT_BBM level 2 by
setting ID_AA64MMFR2_EL1.BBM to 2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
Commit: 51ee67592cdbc5d859eaa7ec25ba21562101f1f9
https://github.com/qemu/qemu/commit/51ee67592cdbc5d859eaa7ec25ba21562101f1f9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
The Arm SMMUv3 includes an optional feature equivalent to the CPU
FEAT_BBM, which permits an OS to switch a range of memory between
"covered by a huge page" and "covered by a sequence of normal pages"
without having to engage in the traditional 'break-before-make'
dance. (This is particularly important for the SMMU, because devices
performing I/O through an SMMU are less likely to be able to cope with
the window in the sequence where an access results in a translation
fault.) The SMMU spec explicitly notes that one of the valid ways to
be a BBM level 2 compliant implementation is:
* if there are multiple entries in the TLB for an address,
choose one of them and use it, ignoring the others
Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple
TLB entries for an address, because the translation table level is
part of the SMMUIOTLBKey, and so our IOTLB hashtable can include
entries for the same address where the leaf was at different levels
(i.e. both hugepage and normal page). Our TLB lookup implementation in
smmu_iotlb_lookup() will always find the entry with the lowest level
(i.e. it prefers the hugepage over the normal page) and ignore any
others. TLB invalidation correctly removes all TLB entries matching
the specified address or address range (unless the guest specifies the
leaf level explicitly, in which case it gets what it asked for). So we
can validly advertise support for BBML level 2.
Note that we still can't yet advertise ourselves as an SMMU v3.2,
because v3.2 requires support for the S2FWB feature, which we don't
yet implement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
Commit: 2afc7dd5a67574fee6f215428ce14db45d87ea72
https://github.com/qemu/qemu/commit/2afc7dd5a67574fee6f215428ce14db45d87ea72
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a62cfbacae3770c9e0b2d5fba6c5a85ee25b025f
https://github.com/qemu/qemu/commit/a62cfbacae3770c9e0b2d5fba6c5a85ee25b025f
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Don't add empty bootargs to device tree
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty string.
(see hw/core/machine.c::machine_initfn()).
Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
a segfault had already been observed by dereferencing the NULL pointer.
It should be worded as *empty" bootargs.
Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9feb4b8f101be95c8dd6362fd41cc88969937247
https://github.com/qemu/qemu/commit/9feb4b8f101be95c8dd6362fd41cc88969937247
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5ec033e693928724746c8256751306db7f5574a1
https://github.com/qemu/qemu/commit/5ec033e693928724746c8256751306db7f5574a1
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: rvk: add cfg properties for zbk* and zk*
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4b1d8d62adb0a8ae8ecf55a0772bcc0c6e91731e
https://github.com/qemu/qemu/commit/4b1d8d62adb0a8ae8ecf55a0772bcc0c6e91731e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvk: add support for zbkb extension
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cb917fe9184717e6a7225de64956f116cdddae95
https://github.com/qemu/qemu/commit/cb917fe9184717e6a7225de64956f116cdddae95
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zbkc extension
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a7aeaaccad32300e01b6153688463a59d5335a6c
https://github.com/qemu/qemu/commit/a7aeaaccad32300e01b6153688463a59d5335a6c
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zbkx extension
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ed9a4f081e3176c8f752f9ce5862f5fbda26a5fe
https://github.com/qemu/qemu/commit/ed9a4f081e3176c8f752f9ce5862f5fbda26a5fe
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M crypto/meson.build
A crypto/sm4.c
A include/crypto/sm4.h
M target/arm/crypto_helper.c
Log Message:
-----------
crypto: move sm4_sbox from target/arm
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: de61a92aec3a66ed03e0ec75e3bc67d0852fa2fc
https://github.com/qemu/qemu/commit/de61a92aec3a66ed03e0ec75e3bc67d0852fa2fc
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvk.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvk: add support for zknd/zkne extension in RV32
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2faa94985b5e605ff5c52c7315faadf6889cb109
https://github.com/qemu/qemu/commit/2faa94985b5e605ff5c52c7315faadf6889cb109
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zkne/zknd extension in RV64
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7ee4e5db83c1748021a3f81eb21677b3366a01d4
https://github.com/qemu/qemu/commit/7ee4e5db83c1748021a3f81eb21677b3366a01d4
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 585458fa61102d7db7308be1896c0f4adf1c46fb
https://github.com/qemu/qemu/commit/585458fa61102d7db7308be1896c0f4adf1c46fb
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha512 related instructions for RV32 in
zknh extension
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3eea6489df0e76f385bde123cd1be6d60f7a70c
https://github.com/qemu/qemu/commit/b3eea6489df0e76f385bde123cd1be6d60f7a70c
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha512 related instructions for RV64 in
zknh extension
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 26abcf0eda316a995b28080a92470938922cb172
https://github.com/qemu/qemu/commit/26abcf0eda316a995b28080a92470938922cb172
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zksed/zksh extension
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 817ec61083250b8b7cfa8d22ea60a388ff4849d0
https://github.com/qemu/qemu/commit/817ec61083250b8b7cfa8d22ea60a388ff4849d0
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
M target/riscv/op_helper.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: rvk: add CSR support for Zkr
- add SEED CSR which must be accessed with a read-write instruction:
A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 798ad16cf1ff6b3e2876bef3ba13ead4e61d7a81
https://github.com/qemu/qemu/commit/798ad16cf1ff6b3e2876bef3ba13ead4e61d7a81
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fa3e92c98dab98186459547cd3d0053c0046880f
https://github.com/qemu/qemu/commit/fa3e92c98dab98186459547cd3d0053c0046880f
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: rvk: expose zbk* and zk* properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7687355a67f651fdc8e840da536cbfca3da198b6
https://github.com/qemu/qemu/commit/7687355a67f651fdc8e840da536cbfca3da198b6
Author: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/monitor.c
Log Message:
-----------
target/riscv: Fix incorrect PTE merge in walk_pte
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.
Enforce the split up, by tracking the virtual base address.
Let's say we have the mapping:
0x81200000 -> 0x89623000 (4K)
0x8120f000 -> 0x89624000 (4K)
Before, walk_pte would have shown:
vaddr paddr size attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000002000 rwxu-ad
as it only checks for subsequent paddrs. With this patch, it becomes:
vaddr paddr size attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000001000 rwxu-ad
000000008120f000 0000000089624000 0000000000001000 rwxu-ad
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 472594f3e80d606773a2753c1919db98cb7d0bcd
https://github.com/qemu/qemu/commit/472594f3e80d606773a2753c1919db98cb7d0bcd
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add scalar crypto related extenstion strings to isa_string
- add zbk* and zk* strings to isa_edata_arr
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f99c3250f476b43e7b19f97bba5cd8cbfdc635c0
https://github.com/qemu/qemu/commit/f99c3250f476b43e7b19f97bba5cd8cbfdc635c0
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add a machine done notifier
Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.
This is based on similar code in the ARM virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 900fec3597dfd8f1e1a4ee1b9610c6a6a54ce663
https://github.com/qemu/qemu/commit/900fec3597dfd8f1e1a4ee1b9610c6a6a54ce663
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/meson.build
R hw/arm/sysbus-fdt.c
M hw/arm/virt.c
M hw/arm/xlnx-versal-virt.c
M hw/core/meson.build
A hw/core/sysbus-fdt.c
R include/hw/arm/sysbus-fdt.h
A include/hw/core/sysbus-fdt.h
Log Message:
-----------
hw/core: Move the ARM sysbus-fdt to core
The ARM virt machine currently uses sysbus-fdt to create device tree
entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit from this, so move the code to
the core directory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b4768f1d2504e02dcfc008e6ea668f8bfaea9021
https://github.com/qemu/qemu/commit/b4768f1d2504e02dcfc008e6ea668f8bfaea9021
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Create a platform bus
Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b296af7d085132cd91bca0d2f30163b8a5e655b7
https://github.com/qemu/qemu/commit/b296af7d085132cd91bca0d2f30163b8a5e655b7
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Add support for generating platform FDT entries
Similar to the ARM virt machine add support for adding device tree
entries for dynamically created devices.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 01db91489ca22e896a049530a60472efd87d2c9b
https://github.com/qemu/qemu/commit/01db91489ca22e896a049530a60472efd87d2c9b
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Add device plug support
Add support for plugging in devices, this was tested with the TPM
device.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91c9ab70f0a397bb2309713194f51a9fbeb8d7ba
https://github.com/qemu/qemu/commit/91c9ab70f0a397bb2309713194f51a9fbeb8d7ba
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/riscv/virt.rst
M hw/riscv/Kconfig
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Enable TPM backends
Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
Then launching QEMU with:
-chardev socket,id=chrtpm,path=swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-device,tpmdev=tpm0
The TPM device can be seen in the memory tree and the generated device
tree.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3d7f3cf8c66a53427c7da2db7b3cb81805b8c170
https://github.com/qemu/qemu/commit/3d7f3cf8c66a53427c7da2db7b3cb81805b8c170
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-synth.c
Log Message:
-----------
9pfs: fix inode sequencing in 'synth' driver
The 'synth' driver's root node and the 'synth' driver's first
subdirectory node falsely share the same inode number (zero), which
makes it impossible for 9p clients (i.e. 9p test cases) to distinguish
root node and first subdirectory from each other by comparing their QIDs
(which are derived by 9p server from driver's inode numbers).
Fix this issue by using prefix-increment instead of postfix-increment
operator while generating new inode numbers for subdirectories and files.
Link: https://lore.kernel.org/qemu-devel/3859307.hTDP4D0zbi@silver/
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <E1nTpyU-0000yR-9o@lizzy.crudebyte.com>
Commit: d87a5b8f340ca4fd36d11b1959f980e135bd64b2
https://github.com/qemu/qemu/commit/d87a5b8f340ca4fd36d11b1959f980e135bd64b2
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-util-darwin.c
Log Message:
-----------
9pfs: fix qemu_mknodat(S_IFREG) on macOS
mknod() on macOS does not support creating regular files, so
divert to openat_file() if S_IFREG is passed with mode argument.
Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is
equivalent to type S_IFREG".
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Will Cohen <wwcohen@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<3102ca936f88bc1f79d2a325e5bc68f48f54e6e3.1651228000.git.qemu_oss@crudebyte.com>
Commit: c7495c8a4bbb75a219e21f56ac29f428e004a6d7
https://github.com/qemu/qemu/commit/c7495c8a4bbb75a219e21f56ac29f428e004a6d7
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-util-darwin.c
Log Message:
-----------
9pfs: fix qemu_mknodat(S_IFSOCK) on macOS
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and fchmodat() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<2e7b5ecd7a6d83a538db4e8a22d8fb03e9e0f06e.1651228001.git.qemu_oss@crudebyte.com>
[C.S. - Use AT_SYMLINK_NOFOLLOW instead of AT_SYMLINK_NOFOLLOW_ANY. ]
Link: https://lore.kernel.org/qemu-devel/3704033.BMyLRrx2Jx@silver/
Commit: 1bfd6eb26e168057b84b4a2c01d92ae9be39752f
https://github.com/qemu/qemu/commit/1bfd6eb26e168057b84b4a2c01d92ae9be39752f
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-util.h
M hw/9pfs/9p.c
Log Message:
-----------
9pfs: fix wrong encoding of rdev field in Rgetattr on macOS
The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t,
which is actually a system dependant type and therefore both the
size and encoding of dev_t differ between macOS and Linux.
So far we have sent 'rdev' to guest in host's dev_t format as-is,
which caused devices to appear with wrong device numbers on
guests running on macOS hosts, eventually leading to various
misbehaviours on guest in conjunction with device files.
This patch fixes this issue by converting the device number from
host's dev_t format to Linux dev_t format. As 9p request
'Tgettattr' is exclusive to protocol version 9p2000.L, it should
be fair to assume that 'rdev' field is assumed to be in Linux dev_t
format by client as well.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Link: https://lore.kernel.org/qemu-devel/20220421093056.5ab1e7ed@bahia/
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<b3a430c2c382ba69a7405e04c0b090ab0d86f17e.1651228001.git.qemu_oss@crudebyte.com>
Commit: 433f063768c0b5e935b392bff3e680995789055b
https://github.com/qemu/qemu/commit/433f063768c0b5e935b392bff3e680995789055b
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-util.h
M hw/9pfs/9p.c
Log Message:
-----------
9pfs: fix wrong errno being sent to Linux client on macOS host
Linux and macOS only share some errno definitions with equal macro
name and value. In fact most mappings for errno are completely
different on the two systems.
This patch converts some important errno values from macOS host to
corresponding Linux errno values before eventually sending such error
codes along with 'Rlerror' replies (if 9p2000.L is used that is). Not
having translated errnos before violated the 9p2000.L protocol spec,
which says:
"
size[4] Rlerror tag[2] ecode[4]
... ecode is a numerical Linux errno.
"
https://github.com/chaos/diod/wiki/protocol#lerror----return-error-code
This patch fixes a bunch of misbehaviours when running a Linux client
on macOS host. For instance this patch fixes:
mount -t 9p -o posixacl ...
on Linux guest if security_mode=mapped was used for 9p server, which
refused to mount successfully, because macOS returned ENOATTR==93
when client tried to retrieve POSIX ACL xattrs, because errno 93
is defined as EPROTONOSUPPORT==93 on Linux, so Linux client believed
that xattrs were not supported by filesystem on host in general.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Link: https://lore.kernel.org/qemu-devel/20220421124835.3e664669@bahia/
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<b322ab298a62069e527d2b032028bdc9115afacd.1651228001.git.qemu_oss@crudebyte.com>
Commit: 60b3befc4a115aeaab4a13cddd871d45747e0cd9
https://github.com/qemu/qemu/commit/60b3befc4a115aeaab4a13cddd871d45747e0cd9
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-posix-acl.c
Log Message:
-----------
9pfs: fix removing non-existent POSIX ACL xattr on macOS host
When mapped POSIX ACL is used, we are ignoring errors when trying
to remove a POSIX ACL xattr that does not exist. On Linux hosts we
would get ENODATA in such cases, on macOS hosts however we get
ENOATTR instead.
As we can be sure that ENOATTR is defined as being identical on Linux
hosts (at least by qemu/xattr.h), it is safe to fix this issue by
simply comparing against ENOATTR instead of ENODATA.
This patch fixes e.g. a command on Linux guest like:
cp --preserve=mode old new
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Link: https://lore.kernel.org/qemu-devel/2866993.yOYK24bMf6@silver/
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<34f81e9bffd7a3e65fb7aab5b56c107bd0aac960.1651228001.git.qemu_oss@crudebyte.com>
Commit: 8fd0065ab9ca0205c820716943384be74ab081fc
https://github.com/qemu/qemu/commit/8fd0065ab9ca0205c820716943384be74ab081fc
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/9pfs/9p-util-darwin.c
Log Message:
-----------
9pfs: fix qemu_mknodat() to always return -1 on error on macOS host
qemu_mknodat() is expected to behave according to its POSIX API, and
therefore should always return exactly -1 on any error, and errno
should be set for the actual error code.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-Id:
<c714b5e1cae225ab7575242c45ee0fe4945eb6ad.1651228001.git.qemu_oss@crudebyte.com>
Commit: ee4836e81b9cd571ab070b846eaebe48a4064297
https://github.com/qemu/qemu/commit/ee4836e81b9cd571ab070b846eaebe48a4064297
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function and an apb frequency calculation
function based on SCU200 register description in ast2600v11.pdf.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <20220315075753.8591-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c8a3d082fee4c025af042ba51ea7d4fc69c5bcfb
https://github.com/qemu/qemu/commit/c8a3d082fee4c025af042ba51ea7d4fc69c5bcfb
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
hw: aspeed_scu: Introduce clkin_25Mhz attribute
AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute
for aspeed_scu_get_clkin() to return the correct clkin for ast2600.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220315075753.8591-3-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e5ef6b5966347c43a7ef8b8fcee7758b6ab4cb70
https://github.com/qemu/qemu/commit/e5ef6b5966347c43a7ef8b8fcee7758b6ab4cb70
Author: Joel Stanley <joel@jms.id.au>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_sbc.c
Log Message:
-----------
aspeed: sbc: Correct default reset values
In order to correctly report secure boot running firmware, these values
must be set. They are taken from a running machine when secure boot is
enabled.
We don't yet have documentation from ASPEED on what they mean. Set the
raw values for now, and in the future improve the model with properties
to set these on a per-machine basis.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220310052159.183975-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a97f25c42f07f4da0899f0ea7b9f7bb065c9f78a
https://github.com/qemu/qemu/commit/a97f25c42f07f4da0899f0ea7b9f7bb065c9f78a
Author: Joel Stanley <joel@jms.id.au>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Add eMMC Boot Controller stub
Guest code (u-boot) pokes at this on boot. No functionality is required
for guest code to work correctly, but it helps to document the region
being read from.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220318092211.723938-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e3627ef7dca13f21d5bcd615a17ae897ea9ffddd
https://github.com/qemu/qemu/commit/e3627ef7dca13f21d5bcd615a17ae897ea9ffddd
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/adc/aspeed_adc.c
M include/hw/adc/aspeed_adc.h
Log Message:
-----------
aspeed/adc: Add AST1030 support
Per ast1030_v7.pdf, AST1030 ADC engine is identical to AST2600's ADC.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1748e16ab3b75dfe38af4f0a495a2fcfd10bd37d
https://github.com/qemu/qemu/commit/1748e16ab3b75dfe38af4f0a495a2fcfd10bd37d
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Add AST1030 support
AST1030 spi controller's address decoding unit is 1MB that is identical
to ast2600, but fmc address decoding unit is 512kb.
Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller.
In addition, add ast1030 fmc, spi1, and spi2 class init handler.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-3-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5712ae22a30ecf3cfcf16eeb931505610756bb10
https://github.com/qemu/qemu/commit/5712ae22a30ecf3cfcf16eeb931505610756bb10
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/watchdog/wdt_aspeed.c
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
aspeed/wdt: Fix ast2500/ast2600 default reload value
Per ast2500_2520_datasheet_v1.8 and ast2600v11.pdf, the default value of
WDT00 and WDT04 is 0x014FB180 for ast2500/ast2600.
Add default_status and default_reload_value attributes for storing
counter status and reload value as they are different from ast2400.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-4-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: de0e88222d6cb1a765f64e4fb820791d126096f1
https://github.com/qemu/qemu/commit/de0e88222d6cb1a765f64e4fb820791d126096f1
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/watchdog/wdt_aspeed.c
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
aspeed/wdt: Add AST1030 support
AST1030 wdt controller is similiar to AST2600's wdt, but it has extra
registers.
Introduce ast1030 object class and increse the number of regs(offset) of
ast1030 model.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-5-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b05eeb4602a0d66b81a4cbe768e524708435ae4f
https://github.com/qemu/qemu/commit/b05eeb4602a0d66b81a4cbe768e524708435ae4f
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
aspeed/timer: Add AST1030 support
ast1030 tmc(timer controller) is identical to ast2600 tmc.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-6-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 81e13e634df276571eae59721ec5e4537e69e33a
https://github.com/qemu/qemu/commit/81e13e634df276571eae59721ec5e4537e69e33a
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
aspeed/scu: Add AST1030 support
Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider
selection is defined in SCU310[11:8].
Add a get_apb_freq function and a class init handler for ast1030.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-7-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f3b0138319a2034c22a265ff852ee692b90d4ca5
https://github.com/qemu/qemu/commit/f3b0138319a2034c22a265ff852ee692b90d4ca5
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A hw/arm/aspeed_ast10x0.c
M hw/arm/meson.build
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed/soc : Add AST1030 support
The embedded core of AST1030 SoC is ARM Coretex M4.
It is hard to be integrated in the common Aspeed Soc framework.
We introduce a new ast1030 class with instance_init and realize
handlers.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: rename aspeed_ast10xx.c to aspeed_ast10x0.c to match zephyr ]
Message-Id: <20220401083850.15266-8-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6cc134dda134f77e131cbd814508d8d6f0845743
https://github.com/qemu/qemu/commit/6cc134dda134f77e131cbd814508d8d6f0845743
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Add an AST1030 eval board
The image should be supplied with ELF binary.
$ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-9-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d645e47bce837831b20b1194753bb68835e277dc
https://github.com/qemu/qemu/commit/d645e47bce837831b20b1194753bb68835e277dc
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A tests/avocado/machine_aspeed.py
Log Message:
-----------
test/avocado/machine_aspeed.py: Add ast1030 test case
Add test case to test "ast1030-evb" machine with zephyr os
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-10-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a419d9633d8ebf5328f6a084f2b44e74de15f310
https://github.com/qemu/qemu/commit/a419d9633d8ebf5328f6a084f2b44e74de15f310
Author: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model
Current fmc model of AST2500 EVB and AST2600 EVB can't emulate quad
mode properly so fix them using equivalent mx25l25635e and mx66u51235f
respectively.
These default settings still can be overridden using the 'fmc-model'
command line option.
Reported-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220402184427.4010304-1-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9f2fe667b4ff18a1cee998058f63823248f8c541
https://github.com/qemu/qemu/commit/9f2fe667b4ff18a1cee998058f63823248f8c541
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
aspeed/hace: Support HMAC Key Buffer register.
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8bad8ff99f5383e4a0787991fc46b49bf175308a
https://github.com/qemu/qemu/commit/8bad8ff99f5383e4a0787991fc46b49bf175308a
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
aspeed/hace: Support AST2600 HACE
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the initial state is already set by
crypto library (gcrypt/glib/...), so skip this step.
2. Calculating accumulative hash digest.
(a) When receiving the last accumulative data, software need to add
padding message at the end of the accumulative data. Padding
message described in specific of MD5, SHA-1, SHA224, SHA256,
SHA512, SHA512/224, SHA512/256.
* Since the crypto library (gcrypt/glib) already pad the
padding message internally.
* This patch is to remove the padding message which fed byguest
machine driver.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-3-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 843e54a71a8fca19a3c7e71f25780941cd956b3d
https://github.com/qemu/qemu/commit/843e54a71a8fca19a3c7e71f25780941cd956b3d
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/aspeed_hace-test.c
Log Message:
-----------
tests/qtest: Add test for Aspeed HACE accumulative mode
This add two addition test cases for accumulative mode under sg enabled.
The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).
The result was calculated by command line sha512sum/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20220426021120.28255-4-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2dae4fe3a160abd8fd5fc1c6b5adb45690949425
https://github.com/qemu/qemu/commit/2dae4fe3a160abd8fd5fc1c6b5adb45690949425
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
A tests/qtest/aspeed_gpio-test.c
M tests/qtest/meson.build
Log Message:
-----------
hw/gpio/aspeed_gpio: Fix QOM pin property
I was setting gpioV4-7 to "1110" using the QOM pin property handler and
noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.
(qemu) qom-set /machine/soc/gpio gpioV4 true
(qemu) qom-set /machine/soc/gpio gpioV5 true
(qemu) qom-set /machine/soc/gpio gpioV6 true
(qemu) qom-get /machine/soc/gpio gpioV4
true
(qemu) qom-set /machine/soc/gpio gpioV7 false
(qemu) qom-get /machine/soc/gpio gpioV4
false
An expression in aspeed_gpio_set_pin_level was using a logical NOT
operator instead of a bitwise NOT operator:
value &= !pin_mask;
The original author probably intended to make a bitwise NOT expression
"~", but mistakenly used a logical NOT operator "!" instead. Some
programming languages like Rust use "!" for both purposes.
Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and
AST2500")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220502080827.244815-1-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8caf59de3e63c61ea8afe01f49f815c747e77ea3
https://github.com/qemu/qemu/commit/8caf59de3e63c61ea8afe01f49f815c747e77ea3
Author: Steven Lee <steven_lee@aspeedtech.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
aspeed/hace: Support AST1030 HACE
Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE
engine.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: deb678582f60cd6e1ba52ba849fbc7dd746f876d
https://github.com/qemu/qemu/commit/deb678582f60cd6e1ba52ba849fbc7dd746f876d
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/qemu/atomic.h
A subprojects/libvhost-user/include/compiler.h
Log Message:
-----------
Use QEMU_SANITIZE_THREAD
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 174a2f4032180f62010a08d30b92e0398ec3fcd4
https://github.com/qemu/qemu/commit/174a2f4032180f62010a08d30b92e0398ec3fcd4
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/fdc-test.c
M util/coroutine-ucontext.c
Log Message:
-----------
Use QEMU_SANITIZE_ADDRESS
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 103b25c2f23c4bb4aaf2854dcf34000f4082f619
https://github.com/qemu/qemu/commit/103b25c2f23c4bb4aaf2854dcf34000f4082f619
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/devel/qtest.rst
M scripts/oss-fuzz/output_reproducer.py
M tests/qtest/ac97-test.c
M tests/qtest/acpi-utils.h
M tests/qtest/ahci-test.c
M tests/qtest/am53c974-test.c
M tests/qtest/arm-cpu-features.c
M tests/qtest/aspeed_hace-test.c
M tests/qtest/boot-order-test.c
M tests/qtest/boot-sector.c
M tests/qtest/boot-sector.h
M tests/qtest/boot-serial-test.c
M tests/qtest/cdrom-test.c
M tests/qtest/dbus-display-test.c
M tests/qtest/dbus-vmstate-test.c
M tests/qtest/device-introspect-test.c
M tests/qtest/device-plug-test.c
M tests/qtest/drive_del-test.c
M tests/qtest/ds1338-test.c
M tests/qtest/e1000-test.c
M tests/qtest/eepro100-test.c
M tests/qtest/endianness-test.c
M tests/qtest/erst-test.c
M tests/qtest/es1370-test.c
M tests/qtest/fuzz-e1000e-test.c
M tests/qtest/fuzz-lsi53c895a-test.c
M tests/qtest/fuzz-megasas-test.c
M tests/qtest/fuzz-sb16-test.c
M tests/qtest/fuzz-sdcard-test.c
M tests/qtest/fuzz-virtio-scsi-test.c
M tests/qtest/fuzz-xlnx-dp-test.c
M tests/qtest/fuzz/fuzz.c
M tests/qtest/fuzz/fuzz.h
M tests/qtest/fuzz/generic_fuzz.c
M tests/qtest/fuzz/i440fx_fuzz.c
M tests/qtest/fuzz/qos_fuzz.c
M tests/qtest/fuzz/virtio_blk_fuzz.c
M tests/qtest/fuzz/virtio_net_fuzz.c
M tests/qtest/fuzz/virtio_scsi_fuzz.c
M tests/qtest/fw_cfg-test.c
M tests/qtest/hd-geo-test.c
M tests/qtest/hexloader-test.c
M tests/qtest/ide-test.c
M tests/qtest/ipoctal232-test.c
M tests/qtest/ivshmem-test.c
M tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c
M tests/qtest/libqos/ahci.c
M tests/qtest/libqos/arm-imx25-pdk-machine.c
M tests/qtest/libqos/arm-n800-machine.c
M tests/qtest/libqos/arm-raspi2-machine.c
M tests/qtest/libqos/arm-sabrelite-machine.c
M tests/qtest/libqos/arm-smdkc210-machine.c
M tests/qtest/libqos/arm-virt-machine.c
M tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c
M tests/qtest/libqos/e1000e.c
M tests/qtest/libqos/fw_cfg.c
M tests/qtest/libqos/fw_cfg.h
M tests/qtest/libqos/i2c-imx.c
M tests/qtest/libqos/i2c-omap.c
M tests/qtest/libqos/i2c.c
M tests/qtest/libqos/i2c.h
M tests/qtest/libqos/libqos.c
M tests/qtest/libqos/libqos.h
R tests/qtest/libqos/libqtest.h
M tests/qtest/libqos/malloc.h
M tests/qtest/libqos/pci-pc.c
M tests/qtest/libqos/pci-spapr.c
M tests/qtest/libqos/pci.h
M tests/qtest/libqos/ppc64_pseries-machine.c
M tests/qtest/libqos/qgraph.c
M tests/qtest/libqos/qos_external.c
M tests/qtest/libqos/rtas.c
M tests/qtest/libqos/sdhci-cmd.c
M tests/qtest/libqos/sdhci-cmd.h
M tests/qtest/libqos/sdhci.c
M tests/qtest/libqos/tpci200.c
M tests/qtest/libqos/usb.c
M tests/qtest/libqos/vhost-user-blk.c
M tests/qtest/libqos/virtio-9p.c
M tests/qtest/libqos/virtio-balloon.c
M tests/qtest/libqos/virtio-blk.c
M tests/qtest/libqos/virtio-iommu.c
M tests/qtest/libqos/virtio-mmio.c
M tests/qtest/libqos/virtio-net.c
M tests/qtest/libqos/virtio-pci.c
M tests/qtest/libqos/virtio-rng.c
M tests/qtest/libqos/virtio-scsi.c
M tests/qtest/libqos/virtio-serial.c
M tests/qtest/libqos/virtio.c
M tests/qtest/libqos/x86_64_pc-machine.c
M tests/qtest/libqtest-single.h
M tests/qtest/libqtest.c
A tests/qtest/libqtest.h
M tests/qtest/lpc-ich9-test.c
M tests/qtest/m48t59-test.c
M tests/qtest/machine-none-test.c
M tests/qtest/megasas-test.c
M tests/qtest/microbit-test.c
M tests/qtest/migration-helpers.h
M tests/qtest/migration-test.c
M tests/qtest/modules-test.c
M tests/qtest/ne2000-test.c
M tests/qtest/npcm7xx_adc-test.c
M tests/qtest/npcm7xx_pwm-test.c
M tests/qtest/npcm7xx_sdhci-test.c
M tests/qtest/npcm7xx_smbus-test.c
M tests/qtest/npcm7xx_watchdog_timer-test.c
M tests/qtest/numa-test.c
M tests/qtest/nvme-test.c
M tests/qtest/pca9552-test.c
M tests/qtest/pci-test.c
M tests/qtest/pcnet-test.c
M tests/qtest/pflash-cfi02-test.c
M tests/qtest/pnv-xscom-test.c
M tests/qtest/prom-env-test.c
M tests/qtest/pvpanic-pci-test.c
M tests/qtest/pvpanic-test.c
M tests/qtest/pxe-test.c
M tests/qtest/q35-test.c
M tests/qtest/qmp-cmd-test.c
M tests/qtest/qmp-test.c
M tests/qtest/qom-test.c
M tests/qtest/rtas-test.c
M tests/qtest/sdhci-test.c
M tests/qtest/spapr-phb-test.c
M tests/qtest/tco-test.c
M tests/qtest/test-filter-mirror.c
M tests/qtest/test-filter-redirector.c
M tests/qtest/test-hmp.c
M tests/qtest/tpm-crb-swtpm-test.c
M tests/qtest/tpm-emu.h
M tests/qtest/tpm-tis-device-swtpm-test.c
M tests/qtest/tpm-tis-swtpm-test.c
M tests/qtest/tpm-util.c
M tests/qtest/tulip-test.c
M tests/qtest/virtio-net-failover.c
M tests/qtest/virtio-rng-test.c
M tests/qtest/virtio-test.c
M tests/qtest/vmgenid-test.c
M tests/qtest/vmxnet3-test.c
M tests/qtest/wdt_ib700-test.c
M tests/qtest/xlnx-can-test.c
M tests/unit/test-qga.c
Log Message:
-----------
tests: move libqtest.h back under qtest/
Since commit a2ce7dbd917 ("meson: convert tests/qtest to meson"),
libqtest.h is under libqos/ directory, while libqtest.c is still in
qtest/. Move back to its original location to avoid mixing with libqos/.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Commit: 145bacf0dac3a17db1791322666506fdd07c6139
https://github.com/qemu/qemu/commit/145bacf0dac3a17db1791322666506fdd07c6139
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A tests/qtest/libqmp.c
A tests/qtest/libqmp.h
M tests/qtest/libqos/meson.build
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
M tests/unit/meson.build
Log Message:
-----------
libqtest: split QMP part in libqmp
This will help moving QAPI/QMP in a common subproject.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Commit: 03e6369b70c407c18910f10104ad20824354b51f
https://github.com/qemu/qemu/commit/03e6369b70c407c18910f10104ad20824354b51f
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/misc/ivshmem.c
M util/event_notifier-posix.c
M util/main-loop.c
Log Message:
-----------
Use g_unix_set_fd_nonblocking()
API available since glib 2.30. It also preserves errno.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0b96c8eae88bb3575f90033aacedca64cc7194f6
https://github.com/qemu/qemu/commit/0b96c8eae88bb3575f90033aacedca64cc7194f6
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/file-posix.c
M include/sysemu/os-posix.h
M util/oslib-posix.c
Log Message:
-----------
block: move fcntl_setfl()
It is only used by block/file-posix.c, move it there.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9e5aff8f778f12791914e48d08f893864e6ed972
https://github.com/qemu/qemu/commit/9e5aff8f778f12791914e48d08f893864e6ed972
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/qemu/osdep.h
M qemu-nbd.c
M util/event_notifier-posix.c
M util/oslib-posix.c
Log Message:
-----------
Replace qemu_pipe() with g_unix_open_pipe()
GLib g_unix_open_pipe() is essentially like qemu_pipe(), available since
2.30.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f4dc7d21ea3bc71782a8ed3817f9ec545db892b3
https://github.com/qemu/qemu/commit/f4dc7d21ea3bc71782a8ed3817f9ec545db892b3
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M util/compatfd.c
Log Message:
-----------
util: replace pipe()+cloexec with g_unix_open_pipe()
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1bb47ce68028724660b714f4a8f2c7bd4bb9b2f2
https://github.com/qemu/qemu/commit/1bb47ce68028724660b714f4a8f2c7bd4bb9b2f2
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga: replace pipe() with g_unix_open_pipe(CLOEXEC)
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 8de47205af6de43f52813d1ceaf980f59bced666
https://github.com/qemu/qemu/commit/8de47205af6de43f52813d1ceaf980f59bced666
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/ivshmem-test.c
M tests/unit/test-io-channel-file.c
Log Message:
-----------
tests: replace pipe() with g_unix_open_pipe(CLOEXEC)
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: c6738fd025f7916ef31a807bcc2e4369efe7bac0
https://github.com/qemu/qemu/commit/c6738fd025f7916ef31a807bcc2e4369efe7bac0
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M os-posix.c
Log Message:
-----------
os-posix: replace pipe()+cloexec with g_unix_open_pipe(CLOEXEC)
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2bede8a5f9637e0fed09da9dd7026accc9eedb13
https://github.com/qemu/qemu/commit/2bede8a5f9637e0fed09da9dd7026accc9eedb13
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tools/virtiofsd/helper.c
Log Message:
-----------
virtiofsd: replace pipe() with g_unix_open_pipe(CLOEXEC)
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: ed0b6c5f78c41a37bc3e27d6edfbfbc6e643433f
https://github.com/qemu/qemu/commit/ed0b6c5f78c41a37bc3e27d6edfbfbc6e643433f
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M io/channel-command.c
Log Message:
-----------
io: replace pipe() with g_unix_open_pipe(CLOEXEC)
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 9e11d27574cc5b6aba9861e5649c5b01d07b741c
https://github.com/qemu/qemu/commit/9e11d27574cc5b6aba9861e5649c5b01d07b741c
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M net/tap-bsd.c
M net/tap-linux.c
M net/tap-solaris.c
M tests/qtest/fuzz/virtio_net_fuzz.c
M tests/unit/test-iov.c
M util/oslib-posix.c
Log Message:
-----------
Replace fcntl(O_NONBLOCK) with g_unix_set_fd_nonblocking()
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 662e9f4d36cc15e3c5fb7395ac6a551467b973e1
https://github.com/qemu/qemu/commit/662e9f4d36cc15e3c5fb7395ac6a551467b973e1
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/io/channel-command.h
M io/channel-command.c
Log Message:
-----------
io: make qio_channel_command_new_pid() static
The function isn't used outside of qio_channel_command_new_spawn(),
which is !win32-specific.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bf43b818c097c97366e992968f246c21e326840f
https://github.com/qemu/qemu/commit/bf43b818c097c97366e992968f246c21e326840f
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M chardev/char-fd.c
M chardev/char-pty.c
M chardev/char-serial.c
M chardev/char-stdio.c
Log Message:
-----------
chardev: replace qemu_set_nonblock()
Those calls are either for non-socket fd, or are POSIX-specific. Use the
dedicated GLib API. (qemu_set_nonblock() is for socket-like)
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 5ad84758c2d6080c34ddab608d4b8d73f9aa30d2
https://github.com/qemu/qemu/commit/5ad84758c2d6080c34ddab608d4b8d73f9aa30d2
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M io/channel-command.c
M io/channel-file.c
Log Message:
-----------
io: replace qemu_set{_non}block()
Those calls are non-socket fd, or are POSIX-specific. Use the dedicated
GLib API. (qemu_set_nonblock() is for socket-like)
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 99720db84bcd76bdfc444bcab97ff5edc1f3cf3d
https://github.com/qemu/qemu/commit/99720db84bcd76bdfc444bcab97ff5edc1f3cf3d
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga: replace qemu_set_nonblock()
The call is POSIX-specific. Use the dedicated GLib API.
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: d6ebc9142541e09f113e5e0a0d675c86dfc0d639
https://github.com/qemu/qemu/commit/d6ebc9142541e09f113e5e0a0d675c86dfc0d639
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/input/virtio-input-host.c
M hw/virtio/vhost-vsock.c
Log Message:
-----------
hw: replace qemu_set_nonblock()
Those calls are non-socket fd, or are POSIX-specific. Use the dedicated
GLib API. (qemu_set_nonblock() is for socket-like)
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 2689152e6bc99487ea62feb89464b314b8cab0bb
https://github.com/qemu/qemu/commit/2689152e6bc99487ea62feb89464b314b8cab0bb
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M ui/input-linux.c
Log Message:
-----------
ui: replace qemu_set_nonblock()
The call is POSIX-specific. Use the dedicated GLib API.
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 91181f550757c8949d68cf783ad2c0618ad352af
https://github.com/qemu/qemu/commit/91181f550757c8949d68cf783ad2c0618ad352af
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M net/tap.c
Log Message:
-----------
net: replace qemu_set_nonblock()
Those calls are POSIX-specific. Use the dedicated GLib
API. (qemu_set_nonblock() is for socket-like)
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 077f2edcd7f05a1016930de1161847a31dd342e5
https://github.com/qemu/qemu/commit/077f2edcd7f05a1016930de1161847a31dd342e5
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/vhost-user-test.c
Log Message:
-----------
tests: replace qemu_set_nonblock()
The call is POSIX-specific. Use the dedicated GLib API.
(this is a preliminary patch before renaming qemu_set_nonblock())
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: f12f87388dad6f020e335084d398175d70233f16
https://github.com/qemu/qemu/commit/f12f87388dad6f020e335084d398175d70233f16
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M chardev/char-socket.c
M contrib/ivshmem-server/ivshmem-server.c
M hw/hyperv/syndbg.c
M hw/virtio/vhost-user.c
M include/qemu/sockets.h
M io/channel-socket.c
M net/l2tpv3.c
M net/socket.c
M qga/channel-posix.c
M tests/unit/socket-helpers.c
M tests/unit/test-crypto-tlssession.c
M util/oslib-posix.c
M util/oslib-win32.c
M util/vhost-user-server.c
Log Message:
-----------
util: rename qemu_*block() socket functions
The qemu_*block() functions are meant to be be used with sockets (the
win32 implementation expects SOCKET)
Over time, those functions where used with Win32 SOCKET or
file-descriptors interchangeably. But for portability, they must only be
used with socket-like file-descriptors. FDs can use
g_unix_set_fd_nonblocking() instead.
Rename the functions with "socket" in the name to prevent bad usages.
This is effectively reverting commit f9e8cacc5557e43 ("oslib-posix:
rename socket_set_nonblock() to qemu_set_nonblock()").
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 6df11a3d77039a55e446758116af8db6740a89fe
https://github.com/qemu/qemu/commit/6df11a3d77039a55e446758116af8db6740a89fe
Author: Andrew Deason <adeason@sinenomine.net>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson.build
M qga/commands-posix.c
Log Message:
-----------
qga/commands-posix: Use getifaddrs when available
Currently, commands-posix.c assumes that getifaddrs() is only
available on Linux, and so the related guest agent command
guest-network-get-interfaces is only implemented for #ifdef __linux__.
This function does exist on other platforms, though, such as Solaris.
So, add a meson check for getifaddrs(), and move the code for
guest-network-get-interfaces to be built whenever getifaddrs() is
available.
The implementation for guest-network-get-interfaces still has some
Linux-specific code, which is not fixed in this commit. This commit
moves the relevant big chunks of code around without changing them, so
a future commit can change the code in place.
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
Message-Id: <20220426195526.7699-2-adeason@sinenomine.net>
Commit: 7d8567ed4d308289ff30741f0e01a640c7a95cec
https://github.com/qemu/qemu/commit/7d8567ed4d308289ff30741f0e01a640c7a95cec
Author: Andrew Deason <adeason@sinenomine.net>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga/commands-posix: Fix iface hw address detection
Since its introduction in commit 3424fc9f16a1 ("qemu-ga: add
guest-network-get-interfaces command"), guest-network-get-interfaces
seems to check if a given interface has a hardware address by checking
'ifa->ifa_flags & SIOCGIFHWADDR'. But ifa_flags is a field for IFF_*
flags (IFF_UP, IFF_LOOPBACK, etc), and comparing it to an ioctl like
SIOCGIFHWADDR doesn't make sense.
On Linux, this isn't a big deal, since SIOCGIFHWADDR has so many bits
set (0x8927), 'ifa->ifa_flags & SIOCGIFHWADDR' will usually have a
nonzero result for any 'normal'-looking interfaces: anything with
IFF_UP (0x1) or IFF_BROADCAST (0x2) set, as well as several
less-common flags. This means we'll try to get the hardware address
for most/all interfaces, even those that don't really have one (like
the loopback device). For those interfaces, Linux just returns a
hardware address of all zeroes.
On Solaris, however, trying to get the hardware address for a loopback
device returns an EADDRNOTAVAIL error. This causes us to return an
error and the entire guest-network-get-interfaces call fails.
Change this logic to always try to get the hardware address for each
interface, and don't return an error if we fail to get it. Instead,
just don't include the 'hardware-address' field in the result if we
can't get the hardware address.
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
Message-Id: <20220426195526.7699-3-adeason@sinenomine.net>
Commit: bf03b84c77b6c30a2d0a6ae52d858a0e7d85dd94
https://github.com/qemu/qemu/commit/bf03b84c77b6c30a2d0a6ae52d858a0e7d85dd94
Author: Andrew Deason <adeason@sinenomine.net>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga/commands-posix: Fix listing ifaces for Solaris
The code for guest-network-get-interfaces needs a couple of small
adjustments for Solaris:
- The results from SIOCGIFHWADDR are documented as being in ifr_addr,
not ifr_hwaddr (ifr_hwaddr doesn't exist on Solaris).
- The implementation of guest_get_network_stats is Linux-specific, so
hide it under #ifdef CONFIG_LINUX. On non-Linux, we just won't
provide network interface stats.
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
Message-Id: <20220426195526.7699-4-adeason@sinenomine.net>
Commit: 52f24c29d4a85a34afbfe76cf2ddb55ec2ea8af7
https://github.com/qemu/qemu/commit/52f24c29d4a85a34afbfe76cf2ddb55ec2ea8af7
Author: Andrew Deason <adeason@sinenomine.net>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga/commands-posix: Log all net stats failures
guest_get_network_stats can silently fail in a couple of ways. Add
debug messages to these cases, so we're never completely silent on
failure.
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220426195526.7699-5-adeason@sinenomine.net>
Commit: baff9338106c3f3f1dcd7b8ab5e58ad8a91575cd
https://github.com/qemu/qemu/commit/baff9338106c3f3f1dcd7b8ab5e58ad8a91575cd
Author: Andrew Deason <adeason@sinenomine.net>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga/commands-posix: 'guest-shutdown' for Solaris
On Solaris, instead of the -P, -H, and -r flags, we need to provide
the target init state to the 'shutdown' command: state 5 is poweroff,
0 is halt, and 6 is reboot. We also need to pass -g0 to avoid the
default 60-second delay, and -y to avoid a confirmation prompt.
Implement this logic under an #ifdef CONFIG_SOLARIS, so the
'guest-shutdown' command works properly on Solaris.
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220426195526.7699-6-adeason@sinenomine.net>
Commit: 95359cbcd9e263fbc8d645c489e7a275744b4500
https://github.com/qemu/qemu/commit/95359cbcd9e263fbc8d645c489e7a275744b4500
Author: zhenwei pi <pizhenwei@bytedance.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
M qga/qapi-schema.json
Log Message:
-----------
qga: Introduce NVMe disk bus type
Assigning a NVMe disk by VFIO or emulating a NVMe controller by QEMU,
a NVMe disk get exposed in guest side. Support NVMe disk bus type and
implement posix version.
Test PCI passthrough case:
~#virsh qemu-agent-command buster '{"execute":"guest-get-disks"}' | jq
...
{
"name": "/dev/nvme0n1",
"dependencies": [],
"partition": false,
"address": {
"serial": "SAMSUNG MZQL23T8HCLS-00A07_S64HNE0N500076",
"bus-type": "nvme",
"bus": 0,
"unit": 0,
"pci-controller": {
"bus": 0,
"slot": 22,
"domain": 0,
"function": 0
},
"dev": "/dev/nvme0n1",
"target": 0
}
...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Message-Id: <20220420022610.418052-2-pizhenwei@bytedance.com>
Commit: ee0664922d4f4d77ce23e057014687abd10434ba
https://github.com/qemu/qemu/commit/ee0664922d4f4d77ce23e057014687abd10434ba
Author: zhenwei pi <pizhenwei@bytedance.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/commands-posix.c
M qga/qapi-schema.json
Log Message:
-----------
qga: Introduce disk smart
After assigning a NVMe/SCSI controller to guest by VFIO, we lose
everything on the host side. A guest uses these devices exclusively,
we usually don't care the actions on these devices. But there is a
low probability that hitting physical hardware warning, we need a
chance to get the basic smart log info.
Introduce disk smart, and implement NVMe smart on linux.
Thanks to Keith and Marc-André.
CC: Keith Busch <kbusch@kernel.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Message-Id: <20220420022610.418052-3-pizhenwei@bytedance.com>
Commit: 9e0c1d25be4960f8d7dec9f8618fbd6226080578
https://github.com/qemu/qemu/commit/9e0c1d25be4960f8d7dec9f8618fbd6226080578
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/vec_helper.c
Log Message:
-----------
target/s390x: Fix writeback to v1 in helper_vstl
Fixes: 0e0a5b49ad58 ("s390x/tcg: Implement VECTOR STORE WITH LENGTH")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Miller <dmiller423@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-2-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: fb587db2895a65aeab77e4733e91acff220604d9
https://github.com/qemu/qemu/commit/fb587db2895a65aeab77e4733e91acff220604d9
Author: David Hildenbrand <david@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/gen-features.c
Log Message:
-----------
s390x/cpu_models: drop "msa5" from the TCG "max" model
We don't include the "msa5" feature in the "qemu" model because it
generates a warning. The PoP states:
"The message-security-assist extension 5 requires
the secure-hash-algorithm (SHA-512) capabilities of
the message-security-assist extension 2 as a prereq-
uisite. (March, 2015)"
As SHA-512 won't be supported in the near future, let's just drop the
feature from the "max" model. This avoids the warning and allows us for
making the "max" model match the "qemu" model (except for compat
machines). We don't lose much, as we only implement the function stubs
for MSA, excluding any real subfunctions.
Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/897
Message-Id: <20220428094708.84835-3-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 21419f6f399b4972222e006fdc66a4dfdce7abef
https://github.com/qemu/qemu/commit/21419f6f399b4972222e006fdc66a4dfdce7abef
Author: David Hildenbrand <david@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/cpu_models.c
M target/s390x/gen-features.c
Log Message:
-----------
s390x/cpu_models: make "max" match the unmodified "qemu" CPU model under TCG
Before we were able to bump up the qemu CPU model to a z13, we included
some experimental features during development in the "max" model only.
Nowadays, the "max" model corresponds exactly to the "qemu" CPU model
of the latest QEMU machine under TCG.
Let's remove all the special casing, effectively making both models
match completely from now on, and clean up.
Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220428094708.84835-4-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 11d380604090dc10b895dffc9a0de3ecc1a0165c
https://github.com/qemu/qemu/commit/11d380604090dc10b895dffc9a0de3ecc1a0165c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/tcg/tcg-op.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Implement tcg_gen_{h,w}swap_{i32,i64}
Swap half-words (16-bit) and words (32-bit) within a larger value.
Mirrors functions of the same names within include/qemu/bitops.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: David Miller <dmiller423@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-5-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 99e6ffee50997096aa7fd1465c4ed0344d3fd747
https://github.com/qemu/qemu/commit/99e6ffee50997096aa7fd1465c4ed0344d3fd747
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/translate_vx.c.inc
M target/s390x/tcg/vec_fpu_helper.c
Log Message:
-----------
target/s390x: vxeh2: vector convert short/32b
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-6-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: cd1334c6dbae60b21d19bccf80798436667c7b20
https://github.com/qemu/qemu/commit/cd1334c6dbae60b21d19bccf80798436667c7b20
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate.c
M target/s390x/tcg/translate_vx.c.inc
M target/s390x/tcg/vec_string_helper.c
Log Message:
-----------
target/s390x: vxeh2: vector string search
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-7-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 56aad17c295a4fa798d212348e7cd3de0bbc540b
https://github.com/qemu/qemu/commit/56aad17c295a4fa798d212348e7cd3de0bbc540b
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate_vx.c.inc
M target/s390x/tcg/vec_int_helper.c
Log Message:
-----------
target/s390x: vxeh2: Update for changes to vector shifts
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-8-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d549d5e9410df95b8a98d49a55b10469239fa66f
https://github.com/qemu/qemu/commit/d549d5e9410df95b8a98d49a55b10469239fa66f
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: vxeh2: vector shift double by bit
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220428094708.84835-9-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8f1154d4850f1c640451550834b0eb913e38c489
https://github.com/qemu/qemu/commit/8f1154d4850f1c640451550834b0eb913e38c489
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: vxeh2: vector {load, store} elements reversed
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-10-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: db152ac10d30126399f10fcc93e3f317fc51cb44
https://github.com/qemu/qemu/commit/db152ac10d30126399f10fcc93e3f317fc51cb44
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: vxeh2: vector {load, store} byte reversed elements
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-11-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 68d483c63665fec86dc26f63d78d3ea8425f0afe
https://github.com/qemu/qemu/commit/68d483c63665fec86dc26f63d78d3ea8425f0afe
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: vxeh2: vector {load, store} byte reversed element
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-12-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 93239d88dd52253e01e1b04bb497dbe85d027ce6
https://github.com/qemu/qemu/commit/93239d88dd52253e01e1b04bb497dbe85d027ce6
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/s390x/s390-virtio-ccw.c
M target/s390x/gen-features.c
Log Message:
-----------
target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model
[ dh: take care of compat machines ]
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-13-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 88cf86c9b858fc369de916f11d9f588e65faf94c
https://github.com/qemu/qemu/commit/88cf86c9b858fc369de916f11d9f588e65faf94c
Author: David Miller <dmiller423@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/vx.h
A tests/tcg/s390x/vxeh2_vcvt.c
A tests/tcg/s390x/vxeh2_vlstr.c
A tests/tcg/s390x/vxeh2_vs.c
Log Message:
-----------
tests/tcg/s390x: Tests for Vector Enhancements Facility 2
Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220428094708.84835-14-david@redhat.com>
[thuth: Only add test if -march=z15 is supported. Fix constraints for Clang]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9f56ae404618662f4aff7d8bd53bcb0e985940fb
https://github.com/qemu/qemu/commit/9f56ae404618662f4aff7d8bd53bcb0e985940fb
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M disas.c
M disas/meson.build
R disas/s390.c
M include/disas/dis-asm.h
M target/s390x/cpu.c
Log Message:
-----------
disas: Remove old libopcode s390 disassembler
Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.
Message-Id: <20220412165836.355850-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8bbf2afbd953aea109ed1d30d33c51f62ffead60
https://github.com/qemu/qemu/commit/8bbf2afbd953aea109ed1d30d33c51f62ffead60
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/s390x/branch-relative-long.c
Log Message:
-----------
tests/tcg/s390x: Use a different PCRel32 notation in branch-relative-long.c
Binutils >=2.37 and Clang do not accept (. - 0x100000000) PCRel32
constants. While this looks like a bug that needs fixing, use a
different notation (-0x100000000) as a workaround.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20220502164830.1622191-1-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a064a84b5fedf3896e00eeed4d29bbeafd52581d
https://github.com/qemu/qemu/commit/a064a84b5fedf3896e00eeed4d29bbeafd52581d
Author: Denis V. Lunev <den@openvz.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/tools/qemu-img.rst
Log Message:
-----------
qemu-img: properly list formats which have consistency check implemented
Simple grep for the .bdrv_co_check callback presence gives the following
list of block drivers
* QED
* VDI
* VHDX
* VMDK
* Parallels
which have this callback. The presense of the callback means that
consistency check is supported.
The patch updates documentation accordingly.
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Kevin Wolf <kwolf@redhat.com>
CC: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220407083932.531965-1-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 8267803fb77852006fa03d7dc630ba3a44363ea2
https://github.com/qemu/qemu/commit/8267803fb77852006fa03d7dc630ba3a44363ea2
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG
The specification for VHOST_USER_ADD/REM_MEM_REG messages is unclear
in several points, which has led to clients having incompatible
implementations. This changes the specification to be more explicit
about them:
* VHOST_USER_ADD_MEM_REG is not specified as receiving a file
descriptor, though it obviously does need to do so. All
implementations agree on this one, fix the specification.
* VHOST_USER_REM_MEM_REG is not specified as receiving a file
descriptor either, and it also has no reason to do so. rust-vmm does
not send file descriptors for removing a memory region (in agreement
with the specification), libvhost-user and QEMU do (which is a bug),
though libvhost-user doesn't actually make any use of it.
Change the specification so that for compatibility QEMU's behaviour
becomes legal, even if discouraged, but rust-vmm's behaviour becomes
the explicitly recommended mode of operation.
* VHOST_USER_ADD_MEM_REG doesn't have a documented return value, which
is the desired behaviour in the non-postcopy case. It also implemented
like this in QEMU and rust-vmm, though libvhost-user is buggy and
sometimes sends an unexpected reply. This will be fixed in a separate
patch.
However, in postcopy mode it does reply like VHOST_USER_SET_MEM_TABLE.
This behaviour is shared between libvhost-user and QEMU; rust-vmm
doesn't implement postcopy mode yet. Mention it explicitly in the
spec.
* The specification doesn't mention how VHOST_USER_REM_MEM_REG
identifies the memory region to be removed. Change it to describe the
existing behaviour of libvhost-user (guest address, user address and
size must match).
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220407133657.155281-2-kwolf@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 8478514d1ba63e5fe1447c77bb5e920b31d23009
https://github.com/qemu/qemu/commit/8478514d1ba63e5fe1447c77bb5e920b31d23009
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M subprojects/libvhost-user/libvhost-user.c
Log Message:
-----------
libvhost-user: Fix extra vu_add/rem_mem_reg reply
Outside of postcopy mode, neither VHOST_USER_ADD_MEM_REG nor
VHOST_USER_REM_MEM_REG are supposed to send a reply unless explicitly
requested with the need_reply flag. Their current implementation always
sends a reply, even if it isn't requested. This confuses the master
because it will interpret the reply as a reply for the next message for
which it actually expects a reply.
need_reply is already handled correctly by vu_dispatch(), so just don't
send a reply in the non-postcopy part of the message handler for these
two commands.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220407133657.155281-3-kwolf@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: b0a83087d17f18920aa4549d02cfce8ad4ac7050
https://github.com/qemu/qemu/commit/b0a83087d17f18920aa4549d02cfce8ad4ac7050
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/virtio/vhost-user.c
M subprojects/libvhost-user/libvhost-user.c
Log Message:
-----------
vhost-user: Don't pass file descriptor for VHOST_USER_REM_MEM_REG
The spec clarifies now that QEMU should not send a file descriptor in a
request to remove a memory region. Change it accordingly.
For libvhost-user, this is a bug fix that makes it compatible with
rust-vmm's implementation that doesn't send a file descriptor. Keep
accepting, but ignoring a file descriptor for compatibility with older
QEMU versions.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220407133657.155281-4-kwolf@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 53c034c1d0f449d3348cbe029f58bdc135cfd0d4
https://github.com/qemu/qemu/commit/53c034c1d0f449d3348cbe029f58bdc135cfd0d4
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block.c
M include/block/block-global-state.h
M include/block/block-io.h
Log Message:
-----------
block: Classify bdrv_get_flags() as I/O function
This function is safe to call in an I/O context, and qcow2_do_open()
does so (invoked in an I/O context by qcow2_co_invalidate_cache()).
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220427114057.36651-2-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 1a606879598c92d094cb663b1985219d92be9c87
https://github.com/qemu/qemu/commit/1a606879598c92d094cb663b1985219d92be9c87
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/qcow2.c
Log Message:
-----------
qcow2: Do not reopen data_file in invalidate_cache
qcow2_co_invalidate_cache() closes and opens the qcow2 file, by calling
qcow2_close() and qcow2_do_open(). These two functions must thus be
usable from both a global-state and an I/O context.
As they are, they are not safe to call in an I/O context, because they
use bdrv_unref_child() and bdrv_open_child() to close/open the data_file
child, respectively, both of which are global-state functions. When
used from qcow2_co_invalidate_cache(), we do not need to close/open the
data_file child, though (we do not do this for bs->file or bs->backing
either), and so we should skip it in the qcow2_co_invalidate_cache()
path.
To do so, add a parameter to qcow2_do_open() and qcow2_close() to make
them skip handling s->data_file, and have qcow2_co_invalidate_cache()
exempt it from the memset() on the BDRVQcow2State.
(Note that the QED driver similarly closes/opens the QED image by
invoking bdrv_qed_close()+bdrv_qed_do_open(), but both functions seem
safe to use in an I/O context.)
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/945
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220427114057.36651-3-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 4948427eecfcbc33c99bd96722759a4c0ef1bd6b
https://github.com/qemu/qemu/commit/4948427eecfcbc33c99bd96722759a4c0ef1bd6b
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/qemu/main-loop.h
Log Message:
-----------
Revert "main-loop: Disable GLOBAL_STATE_CODE() assertions"
This reverts commit b1c073490553f80594b903ceedfc7c1aef6b1b19. (We
wanted to do so once the 7.1 tree opens, which has happened. The issue
reported in https://gitlab.com/qemu-project/qemu/-/issues/945 should be
fixed by the preceding patches.)
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220427114057.36651-4-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: dd5b12961d7d464b6a02853000363c4b987d5fd4
https://github.com/qemu/qemu/commit/dd5b12961d7d464b6a02853000363c4b987d5fd4
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A tests/qemu-iotests/tests/export-incoming-iothread
A tests/qemu-iotests/tests/export-incoming-iothread.out
Log Message:
-----------
iotests: Add regression test for issue 945
Create a VM with a BDS in an iothread, add -incoming defer to the
command line, and then export this BDS via NBD. Doing so should not
fail an assertion.
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220427114057.36651-5-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: dd686d61d60de08a722a3e26f2d69fdc3776bb08
https://github.com/qemu/qemu/commit/dd686d61d60de08a722a3e26f2d69fdc3776bb08
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M block/vmdk.c
Log Message:
-----------
block/vmdk: Fix reopening bs->file
VMDK disk data is stored in extents, which may or may not be separate
from bs->file. VmdkExtent.file points to where they are stored. Each
that is stored in bs->file will simply reuse the exact pointer value of
bs->file.
(That is why vmdk_free_extents() will unref VmdkExtent.file (e->file)
only if e->file != bs->file.)
Reopen operations can change bs->file (they will replace the whole
BdrvChild object, not just the BDS stored in that BdrvChild), and then
we will need to change all .file pointers of all such VmdkExtents to
point to the new BdrvChild.
In vmdk_reopen_prepare(), we have to check which VmdkExtents are
affected, and in vmdk_reopen_commit(), we can modify them. We have to
split this because:
- The new BdrvChild is created only after prepare, so we can change
VmdkExtent.file only in commit
- In commit, there no longer is any (valid) reference to the old
BdrvChild object, so there would be nothing to compare VmdkExtent.file
against to see whether it was equal to bs->file before reopening
(There is BDRVReopenState.old_file_bs, but the old bs->file
BdrvChild's .bs pointer will be NULL-ed when the new BdrvChild is
created, and so we cannot compare VmdkExtent.file->bs against
BDRVReopenState.old_file_bs)
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220314162719.65384-2-hreitz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: f602f8d1272590a08efa458843c0f977d9179830
https://github.com/qemu/qemu/commit/f602f8d1272590a08efa458843c0f977d9179830
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A tests/qemu-iotests/tests/reopen-file
A tests/qemu-iotests/tests/reopen-file.out
Log Message:
-----------
iotests/reopen-file: Test reopening file child
This should work for all format drivers that support reopening, so test
it.
(This serves as a regression test for HEAD^: This test used to fail for
VMDK before HEAD^.)
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220314162719.65384-3-hreitz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: e1acaf81b9ca6ef2991482be003dcb5915f20e4f
https://github.com/qemu/qemu/commit/e1acaf81b9ca6ef2991482be003dcb5915f20e4f
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M util/coroutine-ucontext.c
Log Message:
-----------
coroutine-ucontext: use QEMU_DEFINE_STATIC_CO_TLS()
Thread-Local Storage variables cannot be used directly from coroutine
code because the compiler may optimize TLS variable accesses across
qemu_coroutine_yield() calls. When the coroutine is re-entered from
another thread the TLS variables from the old thread must no longer be
used.
Use QEMU_DEFINE_STATIC_CO_TLS() for the current and leader variables.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220307153853.602859-2-stefanha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 0e83a93e3bd4d77530cf0cdda22e5ce2e0fff118
https://github.com/qemu/qemu/commit/0e83a93e3bd4d77530cf0cdda22e5ce2e0fff118
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M util/qemu-coroutine.c
Log Message:
-----------
coroutine: use QEMU_DEFINE_STATIC_CO_TLS()
Thread-Local Storage variables cannot be used directly from coroutine
code because the compiler may optimize TLS variable accesses across
qemu_coroutine_yield() calls. When the coroutine is re-entered from
another thread the TLS variables from the old thread must no longer be
used.
Use QEMU_DEFINE_STATIC_CO_TLS() for the current and leader variables.
The alloc_pool QSLIST needs a typedef so the return value of
get_ptr_alloc_pool() can be stored in a local variable.
One example of why this code is necessary: a coroutine that yields
before calling qemu_coroutine_create() to create another coroutine is
affected by the TLS issue.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220307153853.602859-3-stefanha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: adcc396426ca4213f5e0690a20c54e8677ebaa16
https://github.com/qemu/qemu/commit/adcc396426ca4213f5e0690a20c54e8677ebaa16
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M util/coroutine-win32.c
Log Message:
-----------
coroutine-win32: use QEMU_DEFINE_STATIC_CO_TLS()
Thread-Local Storage variables cannot be used directly from coroutine
code because the compiler may optimize TLS variable accesses across
qemu_coroutine_yield() calls. When the coroutine is re-entered from
another thread the TLS variables from the old thread must no longer be
used.
Use QEMU_DEFINE_STATIC_CO_TLS() for the current and leader variables.
I think coroutine-win32.c could get away with __thread because the
variables are only used in situations where either the stale value is
correct (current) or outside coroutine context (loading leader when
current is NULL). Due to the difficulty of being sure that this is
really safe in all scenarios it seems worth converting it anyway.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220307153853.602859-4-stefanha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: f8d254d997384a83ae2284a976dfdb054af16e21
https://github.com/qemu/qemu/commit/f8d254d997384a83ae2284a976dfdb054af16e21
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/bti-3.c
Log Message:
-----------
target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17). The linux kernel
sets this in bti_enable().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5c339a7c5cdad0b03d8bdc1a195ac4cc509d0169
https://github.com/qemu/qemu/commit/5c339a7c5cdad0b03d8bdc1a195ac4cc509d0169
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/pxa2xx.c
M hw/arm/pxa2xx_pic.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_kvm.c
A target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/gdbstub.c
M target/arm/helper.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Split out cpregs.h
Move ARMCPRegInfo and all related declarations to a new
internal header, out of the public cpu.h.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 106f041b76647f78bcdd976398ea9cd4fbdca7fa
https://github.com/qemu/qemu/commit/106f041b76647f78bcdd976398ea9cd4fbdca7fa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Reorg CPAccessResult and access_check_cp_reg
Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 076716d48c28b75bfbc9f25e68ab2b4a3a4f4e86
https://github.com/qemu/qemu/commit/076716d48c28b75bfbc9f25e68ab2b4a3a4f4e86
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/pxa2xx.c
M hw/arm/pxa2xx_pic.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_kvm.c
M target/arm/cpregs.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
Remove a possible source of error by removing REGINFO_SENTINEL
and using ARRAY_SIZE (convinently hidden inside a macro) to
find the end of the set of regs being registered or modified.
The space saved by not having the extra array element reduces
the executable's .data.rel.ro section by about 9k.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d3d655ea6f8761a6fa3641f77a849d2f1fd8262c
https://github.com/qemu/qemu/commit/d3d655ea6f8761a6fa3641f77a849d2f1fd8262c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Make some more cpreg data static const
These particular data structures are not modified at runtime.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ae6d80b555ae13bd9603460ef12f5bd6f940fbcd
https://github.com/qemu/qemu/commit/ae6d80b555ae13bd9603460ef12f5bd6f940fbcd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Reorg ARMCPRegInfo type field bits
Instead of defining ARM_CP_FLAG_MASK to remove flags,
define ARM_CP_SPECIAL_MASK to isolate special cases.
Sort the specials to the low bits. Use an enum.
Split the large comment block so as to document each
value separately.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 061680fac3ac7b7a542bcfa409f8578ddadff7a7
https://github.com/qemu/qemu/commit/061680fac3ac7b7a542bcfa409f8578ddadff7a7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm-stub.c
M target/arm/kvm.c
M target/arm/machine.c
M target/arm/translate-a64.c
M target/arm/translate-neon.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen".
Retain abort() when preceeded by fprintf or error_report.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc59984cb62875f2c2b43fe94dba336d4d1cdfea
https://github.com/qemu/qemu/commit/fc59984cb62875f2c2b43fe94dba336d4d1cdfea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Change cpreg access permissions to enum
Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 57ef817080e735e658af7d8be609c1978b6e70a5
https://github.com/qemu/qemu/commit/57ef817080e735e658af7d8be609c1978b6e70a5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Name CPState type
Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f66f76a4903443b3929a5a04b930ea26f8e02f21
https://github.com/qemu/qemu/commit/f66f76a4903443b3929a5a04b930ea26f8e02f21
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Name CPSecureState type
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 98d3549474f5c68a9005abafd117c9e00f4b0bb6
https://github.com/qemu/qemu/commit/98d3549474f5c68a9005abafd117c9e00f4b0bb6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
The new_key field is always non-zero -- drop the if.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
[PMM: reinstated dropped PL3_RW mask]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 37d4834d169c8b878d711a794b7ce0f5c54e234b
https://github.com/qemu/qemu/commit/37d4834d169c8b878d711a794b7ce0f5c54e234b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
M target/arm/gdbstub.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Store cpregs key in the hash table directly
Cast the uint32_t key into a gpointer directly, which
allows us to avoid allocating storage for each key.
Use g_hash_table_lookup when we already have a gpointer
(e.g. for callbacks like count_cpreg), or when using
get_arm_cp_reginfo would require casting away const.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a78bcadcccbb1c99c62c3c43f6f8534a325ac80d
https://github.com/qemu/qemu/commit/a78bcadcccbb1c99c62c3c43f6f8534a325ac80d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Merge allocation of the cpreg and its name
Simplify freeing cp_regs hash table entries by using a single
allocation for the entire value.
This fixes a theoretical bug if we were to ever free the entire
hash table, because we've been installing string literal constants
into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
However, at present we only free entries created for AArch32
wildcard cpregs which get overwritten by more specific cpregs,
so this bug is never exposed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9dd5bb7618307c3523f8c0d8ff81288bed84e634
https://github.com/qemu/qemu/commit/9dd5bb7618307c3523f8c0d8ff81288bed84e634
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Hoist computation of key in add_cpreg_to_hashtable
Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.
This will be required by a subsequent patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 93e0a7e353824afe5be19ea359db141b1ef9562c
https://github.com/qemu/qemu/commit/93e0a7e353824afe5be19ea359db141b1ef9562c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
Put most of the value writeback to the same place,
and improve the comment that goes with them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4e87d5e2b7bdd2020fe4211724f0decd54db381d
https://github.com/qemu/qemu/commit/4e87d5e2b7bdd2020fe4211724f0decd54db381d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
Bool is a more appropriate type for these variables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6625a8899537d74ed6402efe113506e6a08df9b1
https://github.com/qemu/qemu/commit/6625a8899537d74ed6402efe113506e6a08df9b1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
Computing isbanked only once makes the code
a bit easier to read.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b7923064e6841c1c32f33551a8dfc63cbb8e154
https://github.com/qemu/qemu/commit/3b7923064e6841c1c32f33551a8dfc63cbb8e154
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Perform override check early in add_cpreg_to_hashtable
Perform the override check early, so that it is still done
even when we decide to discard an unreachable cpreg.
Use assert not printf+abort.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 61f9f6708ab7d6c2d81ccccf15864c796ac3541a
https://github.com/qemu/qemu/commit/61f9f6708ab7d6c2d81ccccf15864c796ac3541a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Reformat comments in add_cpreg_to_hashtable
Put the block comments into the current coding style.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8cb85773b83973f981b61c7ce2588a2e48ccabea
https://github.com/qemu/qemu/commit/8cb85773b83973f981b61c7ce2588a2e48ccabea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
Since e03b56863d2bc, our host endian indicator is unconditionally
set, which means that we can use a normal C condition.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
[PMM: quote correct git hash in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d2b96c5b2e9e9e8651223d9ff308376421f20e4a
https://github.com/qemu/qemu/commit/d2b96c5b2e9e9e8651223d9ff308376421f20e4a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add isar predicates for FEAT_Debugv8p2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 308d5f33d4229198e714673523661d0412e10e30
https://github.com/qemu/qemu/commit/308d5f33d4229198e714673523661d0412e10e30
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add isar_feature_{aa64,any}_ras
Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d9ab9dc689e9c2539d4f920dd334cfcc8119c31e
https://github.com/qemu/qemu/commit/d9ab9dc689e9c2539d4f920dd334cfcc8119c31e
Author: Alex Zuepke <alex.zuepke@tum.de>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: read access to performance counters from EL0
The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0bd5b0c81a58361636ce22bdd2a9d9df57e7c065
https://github.com/qemu/qemu/commit/0bd5b0c81a58361636ce22bdd2a9d9df57e7c065
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: initialize 'val' union in kvm_get_one_spr()
Valgrind isn't convinced that we are initializing the values we assign
to env->spr[spr] because it doesn't understand that the 'val' union is
being written by the kvm_vcpu_ioctl() that follows (via struct
kvm_one_reg).
This results in Valgrind complaining about uninitialized values every
time we use env->spr in a conditional, like this instance:
==707578== Thread 1:
==707578== Conditional jump or move depends on uninitialised value(s)
==707578== at 0xA10A40: hreg_compute_hflags_value (helper_regs.c:106)
==707578== by 0xA10C9F: hreg_compute_hflags (helper_regs.c:173)
==707578== by 0xA110F7: hreg_store_msr (helper_regs.c:262)
==707578== by 0xA051A3: ppc_cpu_reset (cpu_init.c:7168)
==707578== by 0xD4730F: device_transitional_reset (qdev.c:799)
==707578== by 0xD4A11B: resettable_phase_hold (resettable.c:182)
==707578== by 0xD49A77: resettable_assert_reset (resettable.c:60)
==707578== by 0xD4994B: resettable_reset (resettable.c:45)
==707578== by 0xD458BB: device_cold_reset (qdev.c:296)
==707578== by 0x48FBC7: cpu_reset (cpu-common.c:114)
==707578== by 0x97B5EB: spapr_reset_vcpu (spapr_cpu_core.c:38)
==707578== by 0x97BABB: spapr_cpu_core_reset (spapr_cpu_core.c:209)
==707578== Uninitialised value was created by a stack allocation
==707578== at 0xB11F08: kvm_get_one_spr (kvm.c:543)
Initializing 'val' has no impact in the logic and makes Valgrind output
more bearable.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220331001717.616938-2-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b69176595fdb8d5fa499321d6c21369763b497f2
https://github.com/qemu/qemu/commit/b69176595fdb8d5fa499321d6c21369763b497f2
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr()
'lpcr' is used as an input of kvm_get_one_reg(). Valgrind doesn't
understand that and it returns warnings as such for this function:
==55240== Thread 1:
==55240== Conditional jump or move depends on uninitialised value(s)
==55240== at 0xB011E4: kvmppc_enable_cap_large_decr (kvm.c:2546)
==55240== by 0x92F28F: cap_large_decr_cpu_apply (spapr_caps.c:523)
==55240== by 0x930C37: spapr_caps_cpu_apply (spapr_caps.c:921)
==55240== by 0x955D3B: spapr_reset_vcpu (spapr_cpu_core.c:73)
==55240== by 0x95612B: spapr_cpu_core_reset (spapr_cpu_core.c:209)
==55240== by 0x95619B: spapr_cpu_core_reset_handler (spapr_cpu_core.c:218)
==55240== by 0xD3605F: qemu_devices_reset (reset.c:69)
==55240== by 0x92112B: spapr_machine_reset (spapr.c:1641)
==55240== by 0x4FBD63: qemu_system_reset (runstate.c:444)
==55240== by 0x62812B: qdev_machine_creation_done (machine.c:1247)
==55240== by 0x5064C3: qemu_machine_creation_done (vl.c:2725)
==55240== by 0x5065DF: qmp_x_exit_preconfig (vl.c:2748)
==55240== Uninitialised value was created by a stack allocation
==55240== at 0xB01158: kvmppc_enable_cap_large_decr (kvm.c:2540)
Init 'lpcr' to avoid this warning.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220331001717.616938-3-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ded93e40a0c58198506ca495d34eea4a85798294
https://github.com/qemu/qemu/commit/ded93e40a0c58198506ca495d34eea4a85798294
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: init 'sregs' in kvmppc_put_books_sregs()
Init 'sregs' to avoid Valgrind complaints about uninitialized bytes
from kvmppc_put_books_sregs():
==54059== Thread 3:
==54059== Syscall param ioctl(generic) points to uninitialised byte(s)
==54059== at 0x55864E4: ioctl (in /usr/lib64/libc.so.6)
==54059== by 0xD1FA23: kvm_vcpu_ioctl (kvm-all.c:3053)
==54059== by 0xAFB18B: kvmppc_put_books_sregs (kvm.c:891)
==54059== by 0xAFB47B: kvm_arch_put_registers (kvm.c:949)
==54059== by 0xD1EDA7: do_kvm_cpu_synchronize_post_init (kvm-all.c:2766)
==54059== by 0x481AF3: process_queued_cpu_work (cpus-common.c:343)
==54059== by 0x4EF247: qemu_wait_io_event_common (cpus.c:412)
==54059== by 0x4EF343: qemu_wait_io_event (cpus.c:436)
==54059== by 0xD21E83: kvm_vcpu_thread_fn (kvm-accel-ops.c:54)
==54059== by 0xFFEBF3: qemu_thread_start (qemu-thread-posix.c:556)
==54059== by 0x54E6DC3: start_thread (in /usr/lib64/libc.so.6)
==54059== by 0x5596C9F: clone (in /usr/lib64/libc.so.6)
==54059== Address 0x799d1cc is on thread 3's stack
==54059== in frame #2, created by kvmppc_put_books_sregs (kvm.c:851)
==54059== Uninitialised value was created by a stack allocation
==54059== at 0xAFAEB0: kvmppc_put_books_sregs (kvm.c:851)
This happens because Valgrind does not consider the 'sregs'
initialization done by kvm_vcpu_ioctl() at the end of the function.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220331001717.616938-4-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 010973f2d42f40181ee2d8e797e3e98e37a2666d
https://github.com/qemu/qemu/commit/010973f2d42f40181ee2d8e797e3e98e37a2666d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: init 'rmmu_info' in kvm_get_radix_page_info()
Init the struct to avoid Valgrind complaints about unitialized bytes,
such as this one:
==39549== Syscall param ioctl(generic) points to uninitialised byte(s)
==39549== at 0x55864E4: ioctl (in /usr/lib64/libc.so.6)
==39549== by 0xD1F7EF: kvm_vm_ioctl (kvm-all.c:3035)
==39549== by 0xAF8F5B: kvm_get_radix_page_info (kvm.c:276)
==39549== by 0xB00533: kvmppc_host_cpu_class_init (kvm.c:2369)
==39549== by 0xD3DCE7: type_initialize (object.c:366)
==39549== by 0xD3FACF: object_class_foreach_tramp (object.c:1071)
==39549== by 0x502757B: g_hash_table_foreach (in
/usr/lib64/libglib-2.0.so.0.7000.5)
==39549== by 0xD3FC1B: object_class_foreach (object.c:1093)
==39549== by 0xB0141F: kvm_ppc_register_host_cpu_type (kvm.c:2613)
==39549== by 0xAF87E7: kvm_arch_init (kvm.c:157)
==39549== by 0xD1E2A7: kvm_init (kvm-all.c:2595)
==39549== by 0x8E6E93: accel_init_machine (accel-softmmu.c:39)
==39549== Address 0x1fff00e208 is on thread 1's stack
==39549== in frame #2, created by kvm_get_radix_page_info (kvm.c:267)
==39549== Uninitialised value was created by a stack allocation
==39549== at 0xAF8EE8: kvm_get_radix_page_info (kvm.c:267)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220331001717.616938-5-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fb1029067ee0b2a74c898668043ae1cf1b9f286d
https://github.com/qemu/qemu/commit/fb1029067ee0b2a74c898668043ae1cf1b9f286d
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Fix BookE debug interrupt generation
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are not recognized if MSR[DE]
is cleared when the branch instruction executes."
"An instruction complete debug event occurs when any instruction
completes execution so long as MSR[DE] and DBCR0[ICMP] are both
set ... Instruction complete debug events are not recognized if
MSR[DE] is cleared at the time of the instruction execution."
Current codes do not check MSR.DE bit before setting HFLAGS_SE and
HFLAGS_BE flag, which would cause the immediate debug interrupt to
be generated, e.g.: when DBCR0.ICMP bit is set by guest software
and MSR.DE is not set.
[1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
Message-Id: <20220421011729.1148727-1-bmeng.cn@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9b7968deaebb727a9bf8bcd4f371be62f168191a
https://github.com/qemu/qemu/commit/9b7968deaebb727a9bf8bcd4f371be62f168191a
Author: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: Use correct macro name TARGET_PPC64
The correct name of the macro is TARGET_PPC64.
Fixes: 27598393a232 ("Lift max memory slots limit imposed by vhost-user")
Reported-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Cc: Raphael Norwitz <raphael.norwitz@nutanix.com>
Cc: Peter Turschmid <peter.turschm@nutanix.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20220503180108.34506-1-muriloo@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: db44de16d6adb0bc67d01427ae1f6cbf775a2f03
https://github.com/qemu/qemu/commit/db44de16d6adb0bc67d01427ae1f6cbf775a2f03
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive: Always recompute the PIPR when pushing an OS context
The Post Interrupt Priority Register (PIPR) is not restored like the
other OS-context related fields of the TIMA when pushing an OS context
on the CPU. It's not needed because it can be calculated from the
Interrupt Pending Buffer (IPB), which is saved and restored. The PIPR
must therefore always be recomputed when pushing an OS context.
This patch fixes a path on P9 and P10 where it was not done. If there
was a pending interrupt when the OS context was pulled, the IPB was
saved correctly. When pushing back the context, the code in
xive_tctx_need_resend() was checking for a interrupt raised while the
context was not on the CPU, saved in the NVT. If one was found, then
it was merged with the saved IPB and the PIPR updated and everything
was fine. However, if there was no interrupt found in the NVT, then
xive_tctx_ipb_update() was not being called and the PIPR was not
updated. This patch fixes it by always calling xive_tctx_ipb_update().
Note that on P10 (xive2.c) and because of the above, there's no longer
any need to check the CPPR value so it can go away.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220429071620.177142-2-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bb4e8a7e9cef2dbe5c2d7b19625fc14f97ca9ec5
https://github.com/qemu/qemu/commit/bb4e8a7e9cef2dbe5c2d7b19625fc14f97ca9ec5
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Update the state of the External interrupt signal
When pulling or pushing an OS context from/to a CPU, we should
re-evaluate the state of the External interrupt signal. Otherwise, we
can end up catching the External interrupt exception in hypervisor
mode, which is unexpected.
The problem is best illustrated with the following scenario:
1. an External interrupt is raised while the guest is on the CPU.
2. before the guest can ack the External interrupt, an hypervisor
interrupt is raised, for example the Hypervisor Decrementer or
Hypervisor Virtualization interrupt. The hypervisor interrupt forces
the guest to exit while the External interrupt is still pending.
3. the hypervisor handles the hypervisor interrupt. At this point, the
External interrupt is still pending. So it's very likely to be
delivered while the hypervisor is running. That's unexpected and can
result in an infinite loop where the hypervisor catches the External
interrupt, looks for an interrupt in its hypervisor queue, doesn't
find any, exits the interrupt handler with the External interrupt
still raised, repeat...
The fix is simply to always lower the External interrupt signal when
pulling an OS context. It means it needs to be raised again when
re-pushing the OS context. Fortunately, it's already the case, as we
now always call xive_tctx_ipb_update(), which will raise the signal if
needed.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220429071620.177142-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d882fff76cf50d0eec579e3b6c1ad225a1fa9291
https://github.com/qemu/qemu/commit/d882fff76cf50d0eec579e3b6c1ad225a1fa9291
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Remove fpscr_* macros from cpu.h
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7eadae9ba79df8444afe4cdfa0f45d34b8d1a7dd
https://github.com/qemu/qemu/commit/7eadae9ba79df8444afe4cdfa0f45d34b8d1a7dd
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Remove unused msr_* macros
Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220504210541.115256-3-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 25a87972627ad8503aa20eea59787541d0194328
https://github.com/qemu/qemu/commit/25a87972627ad8503aa20eea59787541d0194328
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/ppc/pegasos2.c
M hw/ppc/spapr.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/mem_helper.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove msr_pr macro
msr_pr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fe47b0adfce291759c04a5698b82d5172a6ab5b1
https://github.com/qemu/qemu/commit/fe47b0adfce291759c04a5698b82d5172a6ab5b1
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/ppc/mem_helper.c
Log Message:
-----------
target/ppc: Remove msr_le macro
msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-5-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ce76913f593a4d724248ecd6a04430cd678f59be
https://github.com/qemu/qemu/commit/ce76913f593a4d724248ecd6a04430cd678f59be
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove msr_ds macro
msr_ds macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-6-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f0882858a8a13a30615f3a79e284b755910e5b57
https://github.com/qemu/qemu/commit/f0882858a8a13a30615f3a79e284b755910e5b57
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Remove msr_ile macro
msr_ile macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-7-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ec54b25e02462722ce1a27fab3cc9a33abe5e754
https://github.com/qemu/qemu/commit/ec54b25e02462722ce1a27fab3cc9a33abe5e754
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Remove msr_ee macro
msr_ee macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 77f4cf18006a6139aeb289913a76e03c416ed11d
https://github.com/qemu/qemu/commit/77f4cf18006a6139aeb289913a76e03c416ed11d
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove msr_ce macro
msr_ce macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-9-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9ef97442bf368e07553d4ed08d2840c1cf1df353
https://github.com/qemu/qemu/commit/9ef97442bf368e07553d4ed08d2840c1cf1df353
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Remove msr_pow macro
msr_pow macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-10-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6f291d5af2ae4dbbd66b5c39b35e38f84b0f7ee5
https://github.com/qemu/qemu/commit/6f291d5af2ae4dbbd66b5c39b35e38f84b0f7ee5
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove msr_me macro
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-11-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 035519b97510b44e789399a26fd324a53c4af808
https://github.com/qemu/qemu/commit/035519b97510b44e789399a26fd324a53c4af808
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove msr_gs macro
msr_gs macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-12-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f2fc9feba45f590d218d9f015a264d03393ca113
https://github.com/qemu/qemu/commit/f2fc9feba45f590d218d9f015a264d03393ca113
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove msr_fp macro
msr_fp macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-13-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fdc857dd5a4565cc5906562c9552abdce3f63149
https://github.com/qemu/qemu/commit/fdc857dd5a4565cc5906562c9552abdce3f63149
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove msr_cm macro
msr_cm macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-14-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9aff43cae345d9dd33600e65a825d342f07770d5
https://github.com/qemu/qemu/commit/9aff43cae345d9dd33600e65a825d342f07770d5
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove msr_ir macro
msr_ir macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-15-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 30ecd5c544eacf2767672968802106f13b2b0e70
https://github.com/qemu/qemu/commit/30ecd5c544eacf2767672968802106f13b2b0e70
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove msr_dr macro
msr_dr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-16-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: da9c3a460b70bcdaf6d3b50f9a32a9e7d30faf0e
https://github.com/qemu/qemu/commit/da9c3a460b70bcdaf6d3b50f9a32a9e7d30faf0e
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Remove msr_ep macro
msr_ep macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-17-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9099f7554c430b3cbf96bb9020312ff3656ee955
https://github.com/qemu/qemu/commit/9099f7554c430b3cbf96bb9020312ff3656ee955
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove msr_fe0 and msr_fe1 macros
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-18-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4a7a9c0a3cf044ddeeeac0cd1103feeb8b4c3ff1
https://github.com/qemu/qemu/commit/4a7a9c0a3cf044ddeeeac0cd1103feeb8b4c3ff1
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Remove msr_ts macro
msr_ts macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-19-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6542f92d1125408d04e71ea88b905f6dd1887b64
https://github.com/qemu/qemu/commit/6542f92d1125408d04e71ea88b905f6dd1887b64
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/mem_helper.c
M target/ppc/misc_helper.c
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Remove msr_hv macro
msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-20-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9b0f8579fb1d5e7919e54f862c79cff771b83236
https://github.com/qemu/qemu/commit/9b0f8579fb1d5e7919e54f862c79cff771b83236
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Remove msr_de macro
msr_de macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-21-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3c9c1b7e0a83e4592f7b62393beb08dd09e3f66a
https://github.com/qemu/qemu/commit/3c9c1b7e0a83e4592f7b62393beb08dd09e3f66a
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Add unused msr bits FIELDs
Add FIELDs macros for msr bits that had an unused msr_* before.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-22-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1fc0062625d7d409ceb5620f4b98646bca123288
https://github.com/qemu/qemu/commit/1fc0062625d7d409ceb5620f4b98646bca123288
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Change MSR_* to follow POWER ISA numbering convention
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.
Add a macro to be used to convert from QEMU order to ISA order.
This solution requires less changes than to use the already defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-23-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 06e427bc350c07122c6a0d69b19f01242ee47909
https://github.com/qemu/qemu/commit/06e427bc350c07122c6a0d69b19f01242ee47909
Author: Longpeng(Mike) <longpeng2@huawei.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
vfio: simplify the conditional statements in vfio_msi_enable
It's unnecessary to test against the specific return value of
VFIO_DEVICE_SET_IRQS, since any positive return is an error
indicating the number of vectors we should retry with.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Link: https://lore.kernel.org/r/20220326060226.1892-2-longpeng2@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 7e91e66da59b96cbe1c10964f19f72fe075e6377
https://github.com/qemu/qemu/commit/7e91e66da59b96cbe1c10964f19f72fe075e6377
Author: Longpeng(Mike) <longpeng2@huawei.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
vfio: move re-enabling INTX out of the common helper
Move re-enabling INTX out, and the callers should decide to
re-enable it or not.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Link: https://lore.kernel.org/r/20220326060226.1892-3-longpeng2@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: dac4dc0899fdb12f06a57a8f371ad6816f974604
https://github.com/qemu/qemu/commit/dac4dc0899fdb12f06a57a8f371ad6816f974604
Author: Longpeng(Mike) <longpeng2@huawei.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
vfio: simplify the failure path in vfio_msi_enable
Use vfio_msi_disable_common to simplify the error handling
in vfio_msi_enable.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Link: https://lore.kernel.org/r/20220326060226.1892-4-longpeng2@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 58308018e8930a5ec9232346c46d008c0c7fa319
https://github.com/qemu/qemu/commit/58308018e8930a5ec9232346c46d008c0c7fa319
Author: Longpeng(Mike) <longpeng2@huawei.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
Revert "vfio: Avoid disabling and enabling vectors repeatedly in VFIO
migration"
Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors
repeatedly in VFIO migration") avoids inefficiently disabling and
enabling vectors repeatedly and lets the unmasked vectors be enabled
one by one.
But we want to batch multiple routes and defer the commit, and only
commit once outside the loop of setting vector notifiers, so we
cannot enable the vectors one by one in the loop now.
Revert that commit and we will take another way in the next patch,
it can not only avoid disabling/enabling vectors repeatedly, but
also satisfy our requirement of defer to commit.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Link: https://lore.kernel.org/r/20220326060226.1892-5-longpeng2@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 282800ee1816272e3ade5e55c400f711477ee726
https://github.com/qemu/qemu/commit/282800ee1816272e3ade5e55c400f711477ee726
Author: Longpeng(Mike) <longpeng2@huawei.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
M hw/vfio/pci.h
Log Message:
-----------
vfio: defer to commit kvm irq routing when enable msi/msix
In migration resume phase, all unmasked msix vectors need to be
setup when loading the VF state. However, the setup operation would
take longer if the VM has more VFs and each VF has more unmasked
vectors.
The hot spot is kvm_irqchip_commit_routes, it'll scan and update
all irqfds that are already assigned each invocation, so more
vectors means need more time to process them.
vfio_pci_load_config
vfio_msix_enable
msix_set_vector_notifiers
for (vector = 0; vector < dev->msix_entries_nr; vector++) {
vfio_msix_vector_do_use
vfio_add_kvm_msi_virq
kvm_irqchip_commit_routes <-- expensive
}
We can reduce the cost by only committing once outside the loop.
The routes are cached in kvm_state, we commit them first and then
bind irqfd for each vector.
The test VM has 128 vcpus and 8 VF (each one has 65 vectors),
we measure the cost of the vfio_msix_enable for each VF, and
we can see 90+% costs can be reduce.
VF Count of irqfds[*] Original With this patch
1st 65 8 2
2nd 130 15 2
3rd 195 22 2
4th 260 24 3
5th 325 36 2
6th 390 44 3
7th 455 51 3
8th 520 58 4
Total 258ms 21ms
[*] Count of irqfds
How many irqfds that already assigned and need to process in this
round.
The optimization can be applied to msi type too.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Link: https://lore.kernel.org/r/20220326060226.1892-6-longpeng2@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: d4e99a519cffd624b49de5d444797fc8ed73a92d
https://github.com/qemu/qemu/commit/d4e99a519cffd624b49de5d444797fc8ed73a92d
Author: Xiang Chen <chenxiang66@hisilicon.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio/common: Fix a small boundary issue of a trace
It uses [offset, offset + size - 1] to indicate that the length of range is
size in most places in vfio trace code (such as
trace_vfio_region_region_mmap()) execpt trace_vfio_region_sparse_mmap_entry().
So change it for trace_vfio_region_sparse_mmap_entry(), but if size is zero,
the trace will be weird with an underflow, so move the trace and trace it
only if size is not zero.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Link:
https://lore.kernel.org/r/1650100104-130737-1-git-send-email-chenxiang66@hisilicon.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 4637fecb4ae504b7dda30aea59ae4b27dc7f2575
https://github.com/qemu/qemu/commit/4637fecb4ae504b7dda30aea59ae4b27dc7f2575
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M include/sysemu/tpm.h
Log Message:
-----------
sysemu: tpm: Add a stub function for TPM_IS_CRB
In a subsequent patch, VFIO will need to recognize if
a memory region owner is a TPM CRB device. Hence VFIO
needs to use TPM_IS_CRB() even if CONFIG_TPM is unset. So
let's add a stub function.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linnux.ibm.com>
Link: https://lore.kernel.org/r/20220506132510.1847942-2-eric.auger@redhat.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 18ff358ad3f8e6baa4e4c3690e4c7321153f0cb4
https://github.com/qemu/qemu/commit/18ff358ad3f8e6baa4e4c3690e4c7321153f0cb4
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/common.c
M hw/vfio/trace-events
Log Message:
-----------
vfio/common: remove spurious tpm-crb-cmd misalignment warning
The CRB command buffer currently is a RAM MemoryRegion and given
its base address alignment, it causes an error report on
vfio_listener_region_add(). This region could have been a RAM device
region, easing the detection of such safe situation but this option
was not well received. So let's add a helper function that uses the
memory region owner type to detect the situation is safe wrt
the assignment. Other device types can be checked here if such kind
of problem occurs again.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Link: https://lore.kernel.org/r/20220506132510.1847942-3-eric.auger@redhat.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 530c3139f1e269fe29cebc35c760cccf03a1a333
https://github.com/qemu/qemu/commit/530c3139f1e269fe29cebc35c760cccf03a1a333
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
hw/vfio/pci: fix vfio_pci_hot_reset_result trace point
"%m" format specifier is not interpreted by the trace infrastructure
and thus "%m" is output instead of the actual errno string. Fix it by
outputting strerror(errno).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Link: https://lore.kernel.org/r/20220502094223.36384-2-yi.l.liu@intel.com
[aw: replace commit log as provided by Eric]
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: ad5ec5a940f379c200213302ab753b47a049e2dc
https://github.com/qemu/qemu/commit/ad5ec5a940f379c200213302ab753b47a049e2dc
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
vfio/pci: Use vbasedev local variable in vfio_realize()
Using a VFIODevice handle local variable to improve the code readability.
no functional change intended
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Link: https://lore.kernel.org/r/20220502094223.36384-3-yi.l.liu@intel.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 78f402260bf25c0ad2ab4a0a5815bfa67e819062
https://github.com/qemu/qemu/commit/78f402260bf25c0ad2ab4a0a5815bfa67e819062
Author: Yi Liu <yi.l.liu@intel.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/vfio/common.c
M include/hw/vfio/vfio-common.h
Log Message:
-----------
vfio/common: Rename VFIOGuestIOMMU::iommu into ::iommu_mr
Rename VFIOGuestIOMMU iommu field into iommu_mr. Then it becomes clearer
it is an IOMMU memory region.
no functional change intended
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Link: https://lore.kernel.org/r/20220502094223.36384-4-yi.l.liu@intel.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: 5cd754fdba0eea0ac51ddaf2acea1829ca4efd99
https://github.com/qemu/qemu/commit/5cd754fdba0eea0ac51ddaf2acea1829ca4efd99
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: fix missing tcg_temp_free in gen_window_check
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Use tcg_constant_i32 for them both.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: fc3cdce57d0f43d0a11ea2eb5f6be1d31714a94d
https://github.com/qemu/qemu/commit/fc3cdce57d0f43d0a11ea2eb5f6be1d31714a94d
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_contatnt_* for numeric literals
Replace tcg_const_* for numeric literals with tcg_constant_*.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 204954be618f1a0fe2aaa2e75211579b994e16a4
https://github.com/qemu/qemu/commit/204954be618f1a0fe2aaa2e75211579b994e16a4
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for exceptions
Use tcg_contant_* for exception number, exception cause, debug cause
code and exception PC.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: d10c42e5eae77fa5e0d9aeb3f80049ad3aa52afc
https://github.com/qemu/qemu/commit/d10c42e5eae77fa5e0d9aeb3f80049ad3aa52afc
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for TLB opcodes
dtlb is a boolean flag, use tcg_constant_* for it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 05694f9f4acbe0d5b418756497ab615b06fda211
https://github.com/qemu/qemu/commit/05694f9f4acbe0d5b418756497ab615b06fda211
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for numbered special registers
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: a0ca5ca67e07d7a6678992cdd387413885e62ea0
https://github.com/qemu/qemu/commit/a0ca5ca67e07d7a6678992cdd387413885e62ea0
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for FPU conversion opcodes
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 488144c4a4c9f7514c228e1dcc35b49bd93f47ed
https://github.com/qemu/qemu/commit/488144c4a4c9f7514c228e1dcc35b49bd93f47ed
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for remaining opcodes
- gen_jumpi passes target PC to the helper;
- gen_callw_slot uses callinc (1..3);
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- disas_xtensa_insn passes PC to the helpers;
- translate_entry passes PC, stack register number (0..15) and stack
frame size to the helper;
- gen_check_exclusive passes PC and boolean flag to the helper;
- test_exceptions_retw passes PC to the helper;
- gen_check_atomctl passes PC to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes next PC and an immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: a5fc18fc0247324f5f8a5d19b8afd48e79a7631d
https://github.com/qemu/qemu/commit/a5fc18fc0247324f5f8a5d19b8afd48e79a7631d
Author: Simon Safar <simon@simonsafar.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A target/xtensa/core-lx106.c
A target/xtensa/core-lx106/core-isa.h
A target/xtensa/core-lx106/gdb-config.c.inc
A target/xtensa/core-lx106/xtensa-modules.c.inc
M target/xtensa/cores.list
Log Message:
-----------
target/xtensa: import core lx106
This is the core used in e.g. ESP8266 chips. Importing them
using import_core.sh, with the required files sourced from
https://github.com/espressif/xtensa-overlays
core-lx106.c was generated by the script; the only change is removing
the reference to core-matmap.h which doesn't seem to be available.
Signed-off-by: Simon Safar <simon@simonsafar.com>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Message-Id: <20220423040835.29254-1-simon@simonsafar.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: e197cde893900b39f9cdc09e1323361dc230eaee
https://github.com/qemu/qemu/commit/e197cde893900b39f9cdc09e1323361dc230eaee
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/op_helper.c
Log Message:
-----------
target/xtensa: add clock input to xtensa CPU
Create clock input for the xtensa CPU device and initialize its
frequency to the default core frequency specified in the config.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: c9ea534684367af9fb62b213c61925922fb46712
https://github.com/qemu/qemu/commit/c9ea534684367af9fb62b213c61925922fb46712
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/xtensa/mx_pic.c
Log Message:
-----------
hw/xtensa: fix reset value of MIROUT register of MX PIC
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 462ae01adc80b6fe55a92d79d9bcef944c5269e2
https://github.com/qemu/qemu/commit/462ae01adc80b6fe55a92d79d9bcef944c5269e2
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/crt.S
Log Message:
-----------
tests/tcg/xtensa: fix build for cores without windowed registers
Don't try to initialize windowbase/windowstart in crt.S if they don't
exist.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 9c6de0bdfc269f7fe2c23bf7263685c7a290a0f3
https://github.com/qemu/qemu/commit/9c6de0bdfc269f7fe2c23bf7263685c7a290a0f3
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_sr.S
Log Message:
-----------
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent
tests that expect to raise an exception. Restore vecbase SR to its
reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 7bec59efcbe8198aa8ecb8016a89def497733994
https://github.com/qemu/qemu/commit/7bec59efcbe8198aa8ecb8016a89def497733994
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_break.S
Log Message:
-----------
tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't
hardcode register numbers in the test as 0 and 1, use macros that only
index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 7164addb77b2abc25499523222c9dee1f6b9b2cd
https://github.com/qemu/qemu/commit/7164addb77b2abc25499523222c9dee1f6b9b2cd
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
tests/tcg/xtensa: remove dependency on the loop option
xtensa core may not have the loop option, but still have timers. Don't
use loop opcode in the timer test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: a0653b20d440d5c7f13bbf1fa7f1424faf64cf23
https://github.com/qemu/qemu/commit/a0653b20d440d5c7f13bbf1fa7f1424faf64cf23
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_phys_mem.S
Log Message:
-----------
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
Autorefill tests in the phys_mem test suite are disabled for cores that
have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it
invalidate TLB mappings for entries that conflict with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: db78bce8e5aa5a228abfe3a2ef0f9a31b0baf7f8
https://github.com/qemu/qemu/commit/db78bce8e5aa5a228abfe3a2ef0f9a31b0baf7f8
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_mmu.S
Log Message:
-----------
tests/tcg/xtensa: enable mmu tests for MMUv3
MMU test suite is disabled for cores that have spanning TLB way, i.e.
for all MMUv3 cores. Instead of disabling it make testing region virtual
addresses explicit and invalidate TLB mappings for entries that conflict
with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 4057d5d1ebfeabfd0389da2008850a5c1a25bb19
https://github.com/qemu/qemu/commit/4057d5d1ebfeabfd0389da2008850a5c1a25bb19
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
tests/tcg/xtensa: fix vectors and checks in timer test
Timer test assumes that timer 0 IRQ has level 1 and other timers have
higher level IRQs. This assumption is not correct and the levels may be
arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and
using it for vector selection and by making the check for the timer
exception cause conditional.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: e70ac3a19e9567344417a6c2dbb2347094069af0
https://github.com/qemu/qemu/commit/e70ac3a19e9567344417a6c2dbb2347094069af0
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: implement cache test option opcodes
We don't model caches, so for l*ct opcodes return tags with all bits
(including Valid) set to 0. For all other opcodes don't do anything.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: f721cc29e161ac799c4c7f898527cb4a5d283981
https://github.com/qemu/qemu/commit/f721cc29e161ac799c4c7f898527cb4a5d283981
Author: Sunil Muthuswamy <sunilmut@microsoft.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/i386/whpx/whpx-all.c
M target/i386/whpx/whpx-internal.h
Log Message:
-----------
WHPX: support for xcr0
Support for xcr0 to be able to enable xsave/xrstor. This by itself
is not sufficient to enable xsave/xrstor. WHPX XSAVE API's also
needs to be hooked up.
Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com>
Message-Id:
<MW2PR2101MB1116F07C07A26FD7A7ED8DCFC0780@MW2PR2101MB1116.namprd21.prod.outlook.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1d9a6d1ad872ef8259daf79a7e3b4fa42fb65a30
https://github.com/qemu/qemu/commit/1d9a6d1ad872ef8259daf79a7e3b4fa42fb65a30
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: Add cross prefix for widl tool
The mingw-w64-tool package in Fedora provides widl tool with a
cross prefix, so adds it automatically for cross builds.
WIDL env can be used to redefine the path to tool.
The same behavior as with windres.
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220428181525.300521-1-kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8d72412a216fb648a07e03a6466d9922a25b250f
https://github.com/qemu/qemu/commit/8d72412a216fb648a07e03a6466d9922a25b250f
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qga/vss-win32/meson.build
Log Message:
-----------
qga-vss: always build qga-vss.tlb when qga-vss.dll is built
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220428181541.300619-1-kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b83a0c0f8c95def8acd1a8728d190d011351f839
https://github.com/qemu/qemu/commit/b83a0c0f8c95def8acd1a8728d190d011351f839
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson_options.txt
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson-buildoptions: add support for string options
Allow using the buildoptions.json file for more options, namely anything
that is not a boolean or multiple-choice.
The mapping between configure and meson is messy for string options,
so allow configure to use to something other than the name in
meson_options.txt. This will come in handy anyway for builtin
Meson options such as b_lto or b_coverage.
Tested-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d4f70a4e0de3ea28f28a6e646de2156119545f64
https://github.com/qemu/qemu/commit/d4f70a4e0de3ea28f28a6e646de2156119545f64
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
A scripts/xen-detect.c
Log Message:
-----------
meson, configure: move Xen detection to meson
This is quite a complicated check. I moved all the test programs to
a single file in scripts/, picking the right program with #if and a -D
flag in meson.build's cc.links() invocation.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 55c3482e7f41507a9c45e9626b9e16728984e9f4
https://github.com/qemu/qemu/commit/55c3482e7f41507a9c45e9626b9e16728984e9f4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
Log Message:
-----------
configure, meson: move iasl detection to meson
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c94dfe3ca1e94893bca1f80877eec12be5c0b560
https://github.com/qemu/qemu/commit/c94dfe3ca1e94893bca1f80877eec12be5c0b560
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
Log Message:
-----------
configure: move Windows flags detection to meson
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 676a9f9882e82e90532761e1ac86ce402455d31c
https://github.com/qemu/qemu/commit/676a9f9882e82e90532761e1ac86ce402455d31c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
Log Message:
-----------
configure: switch string options to automatic parsing
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8f54bdcace938918b7b62639b5587be5b67a08df
https://github.com/qemu/qemu/commit/8f54bdcace938918b7b62639b5587be5b67a08df
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move --tls-priority to meson
Use the new support for string option parsing.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 86b0693e5e667aa47c158d0a1e3c9ff6f8a5758f
https://github.com/qemu/qemu/commit/86b0693e5e667aa47c158d0a1e3c9ff6f8a5758f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move bdrv whitelists to meson
Use the new support for string option parsing.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7edf3c53b53043318f3952f82e8baa966858b31b
https://github.com/qemu/qemu/commit/7edf3c53b53043318f3952f82e8baa966858b31b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M docs/meson.build
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
A scripts/qemu-stamp.py
Log Message:
-----------
meson, configure: move --with-pkgversion, CONFIG_STAMP to meson
The hash is now generated with a Python script.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4004385dadf19f9ded0f8390c6fb4d7e03b1a337
https://github.com/qemu/qemu/commit/4004385dadf19f9ded0f8390c6fb4d7e03b1a337
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson, configure: move --interp-prefix to meson
This is the last CONFIG_* entry in config-host.mak that had to be
special cased.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 01b2229100dc0658ae5825541d0b3e2223b1750c
https://github.com/qemu/qemu/commit/01b2229100dc0658ae5825541d0b3e2223b1750c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson: always combine directories with prefix
Meson allows directories such as "bindir" to be relative to the prefix. Right
now configure is forcing an absolute path, but that is not really necessary:
just make sure all uses of the directory variables are prefixed appropriately.
Do the same also for the options that are custom for QEMU, i.e. docdir and
qemu_firmwarepath.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: da78add3964ea7ebfda204a36ed5b44b988d6023
https://github.com/qemu/qemu/commit/da78add3964ea7ebfda204a36ed5b44b988d6023
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson_options.txt
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
Log Message:
-----------
configure: switch directory options to automatic parsing
While prefix, bindir and qemu_suffix needs special treatment due to
differences between Windows and POSIX systems, everything else
needs no extra code in configure.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 00bd4e583d87515935bc5b3333a79478fccdf87f
https://github.com/qemu/qemu/commit/00bd4e583d87515935bc5b3333a79478fccdf87f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson: pass more options directly as -D
If an option is not used anywhere by the configure script, it can be just
added to $meson_options even if it is not parsed by the automatically
generated bits in scripts/meson-buildoptions.sh.
The only slightly tricky case is $debug, where the
if test "$fortify_source" = "yes" ; then
QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS"
debug=no
fi
assignment is dead; configure sets fortify_source=no whenever debug=yes.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7a3024066ac406b26a162e202194b427f280a871
https://github.com/qemu/qemu/commit/7a3024066ac406b26a162e202194b427f280a871
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
Log Message:
-----------
configure: omit options with default values from meson command line
This has no functional change, it only makes the command line shorter
and nicer.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 43a5238f4a7d9b2f82904b0286891995855d4693
https://github.com/qemu/qemu/commit/43a5238f4a7d9b2f82904b0286891995855d4693
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/virtio/meson.build
Log Message:
-----------
meson, virtio: place all virtio-pci devices under virtio_pci_ss
Since a sourceset already exists for this, avoid unnecessary repeat
of CONFIG_VIRTIO_PCI.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 387c469fd007f5660d913f375a3cadfed986c207
https://github.com/qemu/qemu/commit/387c469fd007f5660d913f375a3cadfed986c207
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
Log Message:
-----------
configure: simplify vhost-net-{user, vdpa} configuration
Cleanup to ease review of the conversion to meson. vhost_net_user and
vhost_net_vdpa are never assigned anything in the command line parsing
loop, so they are always equal to $vhost_user and $vhost_vdpa.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0f3cba7f81a5ed2f620005099b5f67a95bacb1b8
https://github.com/qemu/qemu/commit/0f3cba7f81a5ed2f620005099b5f67a95bacb1b8
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M hw/virtio/Kconfig
M meson.build
M scripts/ci/org.centos/stream/8/x86_64/configure
Log Message:
-----------
build: move vhost-vsock configuration to Kconfig
vhost-vsock and vhost-user-vsock are two devices of their own; it should
be possible to enable/disable them with --without-default-devices, not
--without-default-features. Compute their default value in Kconfig to
obtain the more intuitive behavior.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 649669d37992c8d30bac167f1e44c93670c41585
https://github.com/qemu/qemu/commit/649669d37992c8d30bac167f1e44c93670c41585
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M hw/scsi/Kconfig
M include/hw/virtio/virtio-scsi.h
M meson.build
M scripts/ci/org.centos/stream/8/x86_64/configure
Log Message:
-----------
build: move vhost-scsi configuration to Kconfig
vhost-scsi and vhost-user-scsi are two devices of their own; it should
be possible to enable/disable them with --without-default-devices, not
--without-default-features. Compute their default value in Kconfig to
obtain the more intuitive behavior.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0ddfd285e01a066adb647b302f29eabd9b382adc
https://github.com/qemu/qemu/commit/0ddfd285e01a066adb647b302f29eabd9b382adc
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M hw/virtio/Kconfig
M meson.build
Log Message:
-----------
build: move vhost-user-fs configuration to Kconfig
vhost-user-fs is a device and it should be possible to enable/disable
it with --without-default-devices, not --without-default-features.
Compute its default value in Kconfig to obtain the more intuitive
behavior.
In this case the configure options were undocumented, too.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3b448b1f5b4eb92ea6c227ac86a056146ec4ce47
https://github.com/qemu/qemu/commit/3b448b1f5b4eb92ea6c227ac86a056146ec4ce47
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M meson.build
M tests/meson.build
M tools/meson.build
Log Message:
-----------
meson: create have_vhost_* variables
When using Meson options rather than config-host.h, the "when" clauses
have to be changed to if statements (which is not necessarily great,
though at least it highlights which parts of the build are per-target
and which are not).
Do that before moving vhost logic to meson.build, though for now
the variables are just based on config-host.mak data.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 17d5e1e4dddeb8f5432987c3af0cfcfbd6910b19
https://github.com/qemu/qemu/commit/17d5e1e4dddeb8f5432987c3af0cfcfbd6910b19
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M Kconfig.host
M backends/meson.build
M hw/net/meson.build
M hw/virtio/Kconfig
M hw/virtio/meson.build
M meson.build
M net/meson.build
M tests/qtest/meson.build
Log Message:
-----------
meson: use have_vhost_* variables to pick sources
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 96d0b4bb61429c2ba8e2766e178967eed0ba2d48
https://github.com/qemu/qemu/commit/96d0b4bb61429c2ba8e2766e178967eed0ba2d48
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
configure, meson: move vhost options to Meson
Finish the conversion by moving all the definitions and the constraint
checks to meson_options.txt and meson.build respectively.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 01c5f0ac93515decf3963efc9f3ac7faad5b98fd
https://github.com/qemu/qemu/commit/01c5f0ac93515decf3963efc9f3ac7faad5b98fd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/audio/pcspk.c
M hw/audio/soundhw.c
M include/hw/audio/soundhw.h
Log Message:
-----------
pc: remove -soundhw pcspk
The pcspk device is the only user of the init_isa function, and the only
-soundhw option which does not create a new device (it hacks into the
PCSpkState by hand). Remove it, since it was deprecated.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2835d455ca3ce4b576e52df7084cf15ae72170fe
https://github.com/qemu/qemu/commit/2835d455ca3ce4b576e52df7084cf15ae72170fe
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: checkpatch fixes
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 6c2f3a1b164de51321848e09f7da1fe80476caba
https://github.com/qemu/qemu/commit/6c2f3a1b164de51321848e09f7da1fe80476caba
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move registers from dino_init() to DINO_PCI_BRIDGE init function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: b8737f0f4957562a84508b680928cc4cbd99ec23
https://github.com/qemu/qemu/commit/b8737f0f4957562a84508b680928cc4cbd99ec23
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move PCI bus initialisation to dino_pcihost_init()
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 2b1c458497c6dcf8d8d8cf13a8c2866a2de8befc
https://github.com/qemu/qemu/commit/2b1c458497c6dcf8d8d8cf13a8c2866a2de8befc
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move PCI windows initialisation to dino_pcihost_init()
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-5-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 225f47049049db90091e6c7263141359698c4106
https://github.com/qemu/qemu/commit/225f47049049db90091e6c7263141359698c4106
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: add memory-as property containing a link to the memory address space
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-6-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: d51e1ae580aa8ac007c009df6eec4bcd94f59f1b
https://github.com/qemu/qemu/commit/d51e1ae580aa8ac007c009df6eec4bcd94f59f1b
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move pci_setup_iommu() to dino_pcihost_init()
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-7-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: ca9280c33638cc03eaf0583bd568b134856e2acb
https://github.com/qemu/qemu/commit/ca9280c33638cc03eaf0583bd568b134856e2acb
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move PCI bus master address space setup to dino_pcihost_realize()
Add a new dino_pcihost_unrealize() function to remove the address space when the
device is unrealized.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-8-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 570a7671d6fc0e9f61df5c94774ea0937bc9e378
https://github.com/qemu/qemu/commit/570a7671d6fc0e9f61df5c94774ea0937bc9e378
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: move initial register configuration to new dino_pcihost_reset() function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-9-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 609ac143503c7a5d8429732d6e98758910003869
https://github.com/qemu/qemu/commit/609ac143503c7a5d8429732d6e98758910003869
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: use QOM cast instead of directly referencing parent_obj
Use a QOM cast in both dino_chip_read_with_attrs() and
dino_chip_write_with_attrs()
instead of directly referencing parent_obj.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-10-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: a61a7abe54177287f3f4b1b7e09eacc97b2ba9f4
https://github.com/qemu/qemu/commit/a61a7abe54177287f3f4b1b7e09eacc97b2ba9f4
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: return PCIBus from dino_init() using qdev_get_child_bus()
This allows access to the PCI bus without having to reference parent_obj
directly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-11-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: cbbfd31188b2161afb20048dd038f120b7f8889c
https://github.com/qemu/qemu/commit/cbbfd31188b2161afb20048dd038f120b7f8889c
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
A hw/hppa/dino.h
M hw/hppa/hppa_sys.h
Log Message:
-----------
dino: split declarations from dino.c into dino.h
This is to allow access to DinoState from outside dino.c. With the changes to
the headers it is now possible to remove the duplicate definition for
TYPE_DINO_PCI_HOST_BRIDGE from hppa_sys.h.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-12-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 0daa6df4459f8cf0b95b4ff94a2487fb4a8ae937
https://github.com/qemu/qemu/commit/0daa6df4459f8cf0b95b4ff94a2487fb4a8ae937
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M configs/devices/hppa-softmmu/default.mak
M hw/hppa/Kconfig
M hw/hppa/machine.c
M hw/hppa/meson.build
Log Message:
-----------
hppa: use new CONFIG_HPPA_B160L option instead of CONFIG_DINO to build hppa
machine
DINO refers to the GSC-PCI bridge device which will soon be handled separately,
however the QEMU HPPA machine is actually based upon the HPPA B160L as indicated
by the Linux kernel dmesg output when booted in qemu-system-hppa and the QEMU
MAINTAINERS file.
Update the machine configuration to use CONFIG_HPPA_B160L instead of CONFIG_DINO
and also update the machine description accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-13-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 60694bf96880e0cb2ee6b240dfcdee07bbe3556f
https://github.com/qemu/qemu/commit/60694bf96880e0cb2ee6b240dfcdee07bbe3556f
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
dino: change dino_init() to return the DINO device instead of PCIBus
This is in preparation for using more qdev APIs during the configuration of the
HPPA generic machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-14-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: f5c24037f12ba78b59197a1187066337bb23f54d
https://github.com/qemu/qemu/commit/f5c24037f12ba78b59197a1187066337bb23f54d
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/machine.c
Log Message:
-----------
machine.c: map DINO device during board configuration
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-15-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: de797be6c3aa629616423e112de5eae39dc79ef2
https://github.com/qemu/qemu/commit/de797be6c3aa629616423e112de5eae39dc79ef2
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.h
Log Message:
-----------
dino.h: add defines for DINO IRQ numbers
This is to allow the DINO IRQs to be defined as qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-16-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 4f7065bae6316f8fc4d7eb21ef770d665aef046d
https://github.com/qemu/qemu/commit/4f7065bae6316f8fc4d7eb21ef770d665aef046d
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/dino.h
Log Message:
-----------
dino: define IRQ inputs as qdev GPIOs
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-17-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 4db10524b500a87d0bae18f11416374f0e185413
https://github.com/qemu/qemu/commit/4db10524b500a87d0bae18f11416374f0e185413
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
dino: wire up serial IRQ using a qdev GPIO in machine.c
This makes it unnecessary to allocate a separate IRQ for the serial port.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-18-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: e83d4338d46be9c9581ac42a9bb3749d63f2d460
https://github.com/qemu/qemu/commit/e83d4338d46be9c9581ac42a9bb3749d63f2d460
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
dino: remove unused dino_set_timer_irq() IRQ handler
According to the comments in dino.c the timer IRQ is unused, so remove the empty
dino_set_timer_irq() handler function and simply pass NULL to
mc146818_rtc_init()
in machine.c instead.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-19-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: f1fa032d0420203dc3a6ac1ef6d985c8691ee79a
https://github.com/qemu/qemu/commit/f1fa032d0420203dc3a6ac1ef6d985c8691ee79a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
hppa: move dino_init() from dino.c to machine.c
Now that dino_init() is completely decoupled from dino.c it can be moved to
machine.c with the rest of the board configuration.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-20-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: e07b2acc547fe593aed40a6b82c471f570dd417c
https://github.com/qemu/qemu/commit/e07b2acc547fe593aed40a6b82c471f570dd417c
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.c
Log Message:
-----------
dino: use numerical constant for iar0 and iar1 reset values
This is to allow us to decouple the DINO device from the board logic. The choice
of using a hard-coded constant (along with a comment) is to match how this is
already done for toc_addr. If it is decided later that these values need to be
configurable then they can easily be converted to qdev properties.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-21-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 2682c84f56415e7c4139a5f965d2964b16b7dd5a
https://github.com/qemu/qemu/commit/2682c84f56415e7c4139a5f965d2964b16b7dd5a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/dino.h
M hw/hppa/hppa_hardware.h
Log Message:
-----------
dino: move DINO HPA constants from hppa_hardware.h to dino.h
This is to allow us to decouple the DINO device from the board logic.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-22-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: cf524d3e23da7543edaaf407a75e8191ef8d8f94
https://github.com/qemu/qemu/commit/cf524d3e23da7543edaaf407a75e8191ef8d8f94
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M hw/hppa/Kconfig
R hw/hppa/dino.c
R hw/hppa/dino.h
M hw/hppa/machine.c
M hw/hppa/meson.build
M hw/hppa/trace-events
M hw/pci-host/Kconfig
A hw/pci-host/dino.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
A include/hw/pci-host/dino.h
Log Message:
-----------
dino: move from hw/hppa to hw/pci-host
Move the DINO device implementation from hw/hppa to hw/pci-host so that it is
located with all the other PCI host bridges.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-23-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: fbc9e5783ee1e385ab69d643e47a7b17a94b6912
https://github.com/qemu/qemu/commit/fbc9e5783ee1e385ab69d643e47a7b17a94b6912
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
Log Message:
-----------
lasi: checkpatch fixes
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-24-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 20c873f5c7d333d49b07d1e2e69a06073d5c1b7f
https://github.com/qemu/qemu/commit/20c873f5c7d333d49b07d1e2e69a06073d5c1b7f
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move memory region initialisation to new lasi_init() function
Create a new lasi_init() instance initialisation function and move the LASI
memory region initialisation into it. Rename the existing lasi_init() function
to lasi_initfn() for now.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-25-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 7fdea8cd98b245308157319c1c58638d95eaaa0f
https://github.com/qemu/qemu/commit/7fdea8cd98b245308157319c1c58638d95eaaa0f
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move register memory mapping from lasi.c to machine.c
The device register should be mapped directly by the board code.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-26-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: ec38eae2dfec06d4fcf20eff8108ff132ce2c58e
https://github.com/qemu/qemu/commit/ec38eae2dfec06d4fcf20eff8108ff132ce2c58e
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
Log Message:
-----------
lasi: move initialisation of iar and rtc to new lasi_reset() function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-27-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 2e2fa91811573c282fc658b8d7565d85e58a5cf9
https://github.com/qemu/qemu/commit/2e2fa91811573c282fc658b8d7565d85e58a5cf9
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
A hw/hppa/lasi.h
Log Message:
-----------
lasi: move LASIState and associated QOM structures to lasi.h
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-28-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 7c672685f2b50100b6cf9ac8a48615ee72fc742a
https://github.com/qemu/qemu/commit/7c672685f2b50100b6cf9ac8a48615ee72fc742a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/lasi.h
Log Message:
-----------
lasi: replace lasi_get_irq() with defined constants
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-29-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 0a4f21a9dcfbc4884b98874107311a44d640b843
https://github.com/qemu/qemu/commit/0a4f21a9dcfbc4884b98874107311a44d640b843
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/lasi.h
Log Message:
-----------
lasi: define IRQ inputs as qdev GPIOs
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-30-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 57725107b152af103d9b02c19e4bcc78f7f40f60
https://github.com/qemu/qemu/commit/57725107b152af103d9b02c19e4bcc78f7f40f60
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
Log Message:
-----------
lasi: use qdev GPIOs to wire up IRQs in lasi_initfn()
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-31-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 69e10f9f289d5db6f9a4f5ca05720ca7060e8c60
https://github.com/qemu/qemu/commit/69e10f9f289d5db6f9a4f5ca05720ca7060e8c60
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
Log Message:
-----------
lasi: fix serial port initialisation
The existing code checks for serial_hd(1) but sets the LASI serial port chardev
to serial_hd(0). Use serial_hd(1) for the LASI serial port and also set the
serial port endian to DEVICE_BIG_ENDIAN (which also matches the endian of the
existing serial port).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-32-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 5a5449998bd013845ceaaaddc3b0a01d23da316a
https://github.com/qemu/qemu/commit/5a5449998bd013845ceaaaddc3b0a01d23da316a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: update lasi_initfn() to return LASIState
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-33-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: f7d857978521ea0495a88d8f150f20799451d576
https://github.com/qemu/qemu/commit/f7d857978521ea0495a88d8f150f20799451d576
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move LAN initialisation to machine.c
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-34-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 4b55ada0df06da26c7a3eadac52dbcde5d187666
https://github.com/qemu/qemu/commit/4b55ada0df06da26c7a3eadac52dbcde5d187666
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move parallel port initialisation to machine.c
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-35-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 85f735dc93d8ef8df13b7a58a95d444295ac5dfe
https://github.com/qemu/qemu/commit/85f735dc93d8ef8df13b7a58a95d444295ac5dfe
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move second serial port initialisation to machine.c
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-36-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: bea4b89f813c00a3868495e1e262390590ee229e
https://github.com/qemu/qemu/commit/bea4b89f813c00a3868495e1e262390590ee229e
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move PS2 initialisation to machine.c
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-37-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 04d6318ddd862cdc68c3570a0ee66681f2a52afd
https://github.com/qemu/qemu/commit/04d6318ddd862cdc68c3570a0ee66681f2a52afd
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: remove address space parameter from lasi_initfn()
Now that all of the LASI devices are mapped by the board, this parameter is no
longer required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-38-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: d56f8f27bec9d448fa7e083b68696de47d0f5a52
https://github.com/qemu/qemu/commit/d56f8f27bec9d448fa7e083b68696de47d0f5a52
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/lasi.c
M hw/hppa/machine.c
Log Message:
-----------
lasi: move lasi_initfn() to machine.c
Move the simplified lasi_initfn() back to machine.c whilst also renaming it
back to its original lasi_init() name.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-39-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 4461bb3295644fa7ae26dc0fa78b8cce233a3e5e
https://github.com/qemu/qemu/commit/4461bb3295644fa7ae26dc0fa78b8cce233a3e5e
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
M hw/hppa/lasi.h
Log Message:
-----------
lasi: use constants for device register offsets
Instead of generating the offset based upon the physical address of the
register, add constants for each of the device registers to lasi.h and
update lasi.c to use them.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-40-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 0c0b59493ba12eed7d0e0cf7dfb2c5fb14642a12
https://github.com/qemu/qemu/commit/0c0b59493ba12eed7d0e0cf7dfb2c5fb14642a12
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/lasi.c
Log Message:
-----------
lasi: use numerical constant for iar reset value
This is to allow us to decouple the LASI device from the board logic. If it is
decided later that this value needs to be configurable then it can easily be
converted to a qdev property.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-41-mark.cave-ayland@ilande.co.uk>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: d803a737f55826d09315bf6210721fd2558f99dd
https://github.com/qemu/qemu/commit/d803a737f55826d09315bf6210721fd2558f99dd
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/lasi.h
M hw/hppa/machine.c
M hw/hppa/pci.c
Log Message:
-----------
hppa: move device headers from hppa_sys.h into individual .c files
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-42-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: cdf5037261ba9350c3e780e6ba697886268a216a
https://github.com/qemu/qemu/commit/cdf5037261ba9350c3e780e6ba697886268a216a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M hw/hppa/Kconfig
R hw/hppa/lasi.c
R hw/hppa/lasi.h
M hw/hppa/machine.c
M hw/hppa/meson.build
M hw/hppa/trace-events
M hw/misc/Kconfig
A hw/misc/lasi.c
M hw/misc/meson.build
M hw/misc/trace-events
A include/hw/misc/lasi.h
Log Message:
-----------
lasi: move from hw/hppa to hw/misc
Move the LASI device implementation from hw/hppa to hw/misc so that it is
located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-43-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 8b56221e8625a696c010b74671296d0ab1b269fa
https://github.com/qemu/qemu/commit/8b56221e8625a696c010b74671296d0ab1b269fa
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
M hw/hppa/pci.c
Log Message:
-----------
hppa: move hppa_pci_ignore_ops from pci.c to machine.c
The memory region only has one user which is for ensuring accesses to the ISA
bus memory do not fault.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-44-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 32853957d83c2bd0fceb131536273ca2f2b1909a
https://github.com/qemu/qemu/commit/32853957d83c2bd0fceb131536273ca2f2b1909a
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/meson.build
R hw/hppa/pci.c
M hw/hppa/trace-events
Log Message:
-----------
hppa: remove hw/hppa/pci.c
The functions and definitions in this file are not used anywhere within the
generic hppa machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-45-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 28d069707bcc9dec463315406f2225955d9a1d00
https://github.com/qemu/qemu/commit/28d069707bcc9dec463315406f2225955d9a1d00
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
R hw/hppa/trace-events
M meson.build
Log Message:
-----------
hppa: remove unused trace-events from from hw/hppa
Now that there are no longer any devices in hw/hppa the trace-events file is
empty and can be removed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-46-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 36806682526eb0a4e8612e24b867064b8b531225
https://github.com/qemu/qemu/commit/36806682526eb0a4e8612e24b867064b8b531225
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
hppa: move enable_lan() define from hppa_sys.h to machine.c
Now that the board configuration is in one place, the define is only needed when
wiring up the board in machine.c.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-47-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 43146d1789b644d8aa5af89d5759afac04175e12
https://github.com/qemu/qemu/commit/43146d1789b644d8aa5af89d5759afac04175e12
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
R hw/hppa/hppa_sys.h
M hw/hppa/machine.c
Log Message:
-----------
hppa: remove the empty hppa_sys.h file
This file is now just a simple wrapper that includes hppa_hardware.h so remove
the file completely, and update its single user in machine.c to include
hppa_hardware.h directly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-48-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 175f1fdf7c5ad6385f37c4ced16299dd49b29cbc
https://github.com/qemu/qemu/commit/175f1fdf7c5ad6385f37c4ced16299dd49b29cbc
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hppa: use MACHINE QOM macros for defining the hppa machine
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-49-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 188f5d942c722ec636c9acb899d232cc75bfa479
https://github.com/qemu/qemu/commit/188f5d942c722ec636c9acb899d232cc75bfa479
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hppa: fold machine_hppa_machine_init() into
machine_hppa_machine_init_class_init()
There is no need for a separate function to set the machine class properties
separately from the others.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-50-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: c0daaf015dd262642b8b143ea1c6011ed736e379
https://github.com/qemu/qemu/commit/c0daaf015dd262642b8b143ea1c6011ed736e379
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hppa: simplify machine function names in machine.c
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <20220504092600.10048-51-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 71e5b68ef5b2caae4acec94796671c50ac592d13
https://github.com/qemu/qemu/commit/71e5b68ef5b2caae4acec94796671c50ac592d13
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: checkpatch and newline style fixes
Ensure that subsequent patches do not cause checkpatch to fail and also tidy up
extra/missing newlines.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220504153708.10352-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 379f918985198c1983ce00886efeb1d96dd6cf11
https://github.com/qemu/qemu/commit/379f918985198c1983ce00886efeb1d96dd6cf11
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: remove unused ROP8OFF() macro
This macro is unused and so can simply be removed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220504153708.10352-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: db49743c6387640b1bfd431c6665fb1d8d40e89e
https://github.com/qemu/qemu/commit/db49743c6387640b1bfd431c6665fb1d8d40e89e
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: only render dirty scanlines on the display surface
The framebuffer_update_display() function returns the dirty scanlines that were
touched since the last display update, however artist_update_display() always
calls
dpy_gfx_update() with start and end scanlines of 0 and s->height causing the
entire display surface to be rendered on every update.
Update artist_update_display() so that dpy_gfx_update() only renders the dirty
scanlines on the display surface, bypassing the display surface rendering
completely if framebuffer_update_display() indicates no changes occurred.
This noticeably improves boot performance when the framebuffer is enabled on my
rather modest laptop here, including making the GTK UI usable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220504153708.10352-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: d1a0f80e71517aa2f98660eab7aabb23a869ea89
https://github.com/qemu/qemu/commit/d1a0f80e71517aa2f98660eab7aabb23a869ea89
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M disas.c
R disas/arm.c
M disas/meson.build
M include/disas/dis-asm.h
M target/arm/cpu.c
Log Message:
-----------
disas: Remove old libopcode arm disassembler
Capstone should be superior to the old libopcode disassembler, so
we can drop the old file nowadays.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220412165836.355850-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a331aa27fb9d6641cc263fa468d78739b624e6c4
https://github.com/qemu/qemu/commit/a331aa27fb9d6641cc263fa468d78739b624e6c4
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M disas.c
R disas/i386.c
M disas/meson.build
M include/disas/dis-asm.h
M target/i386/cpu.c
Log Message:
-----------
disas: Remove old libopcode i386 disassembler
Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220412165836.355850-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e94cc2a0300aa49547c0e339b1076c16b5275d24
https://github.com/qemu/qemu/commit/e94cc2a0300aa49547c0e339b1076c16b5275d24
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M MAINTAINERS
M disas.c
M disas/meson.build
R disas/ppc.c
M include/disas/dis-asm.h
M target/ppc/cpu_init.c
Log Message:
-----------
disas: Remove old libopcode ppc disassembler
Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.
Message-Id: <20220505173619.488350-1-thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 103fbacaa0dda0eced82bf80f31740cfb0749640
https://github.com/qemu/qemu/commit/103fbacaa0dda0eced82bf80f31740cfb0749640
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M softmmu/vl.c
Log Message:
-----------
softmmu/vl: Fence 'xenfb' if Xen support is not compiled in
The 'xenfb' parameter for the '-vga' command line option is currently
always enabled unconditionally (since the xenfb is not a proper QOM
device that could be tested via its class name). That means it also
shows up if Xen is not enabled at all, e.g. like this:
$ ./qemu-system-sparc -vga help
none no graphic card
xenfb Xen paravirtualized framebuffer
tcx TCX framebuffer (default)
cg3 CG3 framebuffer
Let's avoid this situation by fencing the parameter with the
CONFIG_XEN_BACKEND switch.
Message-Id: <20220427123316.329312-1-thuth@redhat.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2fa93e57ab88bfe735d29bc127bb1a9d9a796da4
https://github.com/qemu/qemu/commit/2fa93e57ab88bfe735d29bc127bb1a9d9a796da4
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options: Limit the -xen options to x86 and arm
The Xen hypervisor is only available on x86 and arm - thus let's
limit the related options to these targets.
Message-Id: <20220427133156.344418-1-thuth@redhat.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: b6c3b5043d98b64c4ee7dd385a85a68c340565da
https://github.com/qemu/qemu/commit/b6c3b5043d98b64c4ee7dd385a85a68c340565da
Author: Yonggang Luo <luoyonggang@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
R scripts/hxtool-conv.pl
Log Message:
-----------
doc: remove hxtool-conv.pl
This script doesn't need anymore as all texi are already convert to rST
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Message-Id: <20201001162705.219-3-luoyonggang@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: bddc6e3323cf56e0416cf076cd4c6aeee2b151fb
https://github.com/qemu/qemu/commit/bddc6e3323cf56e0416cf076cd4c6aeee2b151fb
Author: Yonggang Luo <luoyonggang@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M .cirrus.yml
Log Message:
-----------
cirrus/win32: upgrade mingw base packages
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220503200524.1868-2-luoyonggang@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 6f2648dcfaf101316be71166136c687caf66d1e7
https://github.com/qemu/qemu/commit/6f2648dcfaf101316be71166136c687caf66d1e7
Author: Yonggang Luo <luoyonggang@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M .gitlab-ci.d/windows.yml
Log Message:
-----------
gitlab-ci: Upgrade mingw base package.
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220503200524.1868-3-luoyonggang@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 61c9b38be593301ba9f8d79df6dbebcc2248dc34
https://github.com/qemu/qemu/commit/61c9b38be593301ba9f8d79df6dbebcc2248dc34
Author: Brad Smith <brad@comstyle.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/vm/openbsd
Log Message:
-----------
tests/vm: update openbsd to release 7.1
tests/vm/openbsd: Update to release 7.1
Signed-off-by: Brad Smith <brad@comstyle.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Message-Id: <YnRed7sw45lTbRjb@humpty.home.comstyle.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 7ff0d148284a4377ffa7cd9b504061a8f0431f68
https://github.com/qemu/qemu/commit/7ff0d148284a4377ffa7cd9b504061a8f0431f68
Author: Gautam Agrawal <gautamnagrawal@gmail.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/hppa/machine.c
M hw/isa/isa-bus.c
M hw/mips/fuloong2e.c
M hw/pci/pci.c
M hw/ppc/spapr.c
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
M hw/xenpv/xen_machine_pv.c
M include/sysemu/sysemu.h
M softmmu/globals.c
M softmmu/vl.c
Log Message:
-----------
Warn user if the vga flag is passed but no vga device is created
A global boolean variable "vga_interface_created"(declared in softmmu/globals.c)
has been used to track the creation of vga interface. If the vga flag is passed
in the command line "default_vga"(declared in softmmu/vl.c) variable is set to
0.
To warn user, the condition checks if vga_interface_created is false
and default_vga is equal to 0. If "-vga none" is passed, this patch will not
warn the
user regarding the creation of VGA device.
The warning "A -vga option was passed but this
machine type does not use that option; no VGA device has been created"
is logged if vga flag is passed but no vga device is created.
This patch has been tested for x86_64, i386, sparc, sparc64 and arm boards.
Signed-off-by: Gautam Agrawal <gautamnagrawal@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/581
Message-Id: <20220501122505.29202-1-gautamnagrawal@gmail.com>
[thuth: Fix wrong warning with "-device" in some cases as reported by Paolo]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 4dc28dc3f11e36ebebcb386538a1983543c4fc6e
https://github.com/qemu/qemu/commit/4dc28dc3f11e36ebebcb386538a1983543c4fc6e
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/devel/writing-monitor-commands.rst
Log Message:
-----------
docs/devel/writing-monitor-commands: Replace obsolete STEXI/ETEXI tags
STEXI and ETEXI is not used anymore since we switched to Sphinx.
Replace them in the example with SRST and ERST, too.
Message-Id: <20220506150146.564244-1-thuth@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 90072d1e083336064d9d0ba37ece5bfcec9131b3
https://github.com/qemu/qemu/commit/90072d1e083336064d9d0ba37ece5bfcec9131b3
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M .mailmap
M MAINTAINERS
Log Message:
-----------
MAINTAINERS/.mailmap: update email for Leif Lindholm
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e21b59667767989ecec52005b1e114bc1a8bd5ca
https://github.com/qemu/qemu/commit/e21b59667767989ecec52005b1e114bc1a8bd5ca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle cpreg registration for missing EL
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
This will simplify cpreg registration for conditional arm features.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9ab512ab5e5e5b54c984aec7ae893264091f94ac
https://github.com/qemu/qemu/commit/9ab512ab5e5e5b54c984aec7ae893264091f94ac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Drop EL3 no EL2 fallbacks
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.
This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present. This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1df9fe6c7a928253f6b614788435ea7ce0025163
https://github.com/qemu/qemu/commit/1df9fe6c7a928253f6b614788435ea7ce0025163
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Merge zcr reginfo
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 651593b5eed28b209c9316e916b81a765e560334
https://github.com/qemu/qemu/commit/651593b5eed28b209c9316e916b81a765e560334
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Adjust definition of CONTEXTIDR_EL2
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3fdd366c6a7455b846cba28cd9165ed8e6e35ed3
https://github.com/qemu/qemu/commit/3fdd366c6a7455b846cba28cd9165ed8e6e35ed3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move cortex impdef sysregs to cpu_tcg.c
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6a00b08287445d19a35a02d0cef79bb654631e7a
https://github.com/qemu/qemu/commit/6a00b08287445d19a35a02d0cef79bb654631e7a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Update qemu-system-arm -cpu max to cortex-a57
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 75c60cab2bd02330323a858cdaf874308dd0836d
https://github.com/qemu/qemu/commit/75c60cab2bd02330323a858cdaf874308dd0836d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5073a9fd0ba4e4faa7470c24cc83d53153129f68
https://github.com/qemu/qemu/commit/5073a9fd0ba4e4faa7470c24cc83d53153129f68
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Split out aa32_max_features
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3f0b1238018267b286e8412d16ad62c18af4f0a1
https://github.com/qemu/qemu/commit/3f0b1238018267b286e8412d16ad62c18af4f0a1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Annotate arm_max_initfn with FEAT identifiers
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bad00b33175f06d75fc4dada488aca11f1252544
https://github.com/qemu/qemu/commit/bad00b33175f06d75fc4dada488aca11f1252544
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Use field names for manipulating EL2 and EL3 modes
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a564fc81219eb75fd6bad26c56ecbb1ba8141bd8
https://github.com/qemu/qemu/commit/a564fc81219eb75fd6bad26c56ecbb1ba8141bd8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_Debugv8p2 for -cpu max
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ef3ebc008cdd22859bb2a544107ce0e5b5c5d3c3
https://github.com/qemu/qemu/commit/ef3ebc008cdd22859bb2a544107ce0e5b5c5d3c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_Debugv8p4 for -cpu max
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 206eeed11741731a8311042fb354c3449f8962ec
https://github.com/qemu/qemu/commit/206eeed11741731a8311042fb354c3449f8962ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add minimal RAS registers
Add only the system registers required to implement zero error
records. This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.
Add the EL2 registers required for injecting virtual SError.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 24658c6551a20dd075a976fcd97e765c069fef80
https://github.com/qemu/qemu/commit/24658c6551a20dd075a976fcd97e765c069fef80
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable SCR and HCR bits for RAS
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: beb6e93af269b93e93ae3ab117707c2b51efa1c0
https://github.com/qemu/qemu/commit/beb6e93af269b93e93ae3ab117707c2b51efa1c0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/syndrome.h
Log Message:
-----------
target/arm: Implement virtual SError exceptions
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e723b5b2efd10ae8dc68217d41eb42403b9c3445
https://github.com/qemu/qemu/commit/e723b5b2efd10ae8dc68217d41eb42403b9c3445
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/a32.decode
M target/arm/helper.h
M target/arm/op_helper.c
M target/arm/t32.decode
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement ESB instruction
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bdf8f8b3fc1d92ff5662754d7fe698e97d2963c0
https://github.com/qemu/qemu/commit/bdf8f8b3fc1d92ff5662754d7fe698e97d2963c0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_RAS for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3bf8719031da46361675a58359c92c539c9dcf4a
https://github.com/qemu/qemu/commit/3bf8719031da46361675a58359c92c539c9dcf4a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_IESB for -cpu max
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6ae8572640f9d51b4c206ee3de7a26bd86e08270
https://github.com/qemu/qemu/commit/6ae8572640f9d51b4c206ee3de7a26bd86e08270
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_CSV2 for -cpu max
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 74b326d97635247d93bf9347a7c457cd6738a507
https://github.com/qemu/qemu/commit/74b326d97635247d93bf9347a7c457cd6738a507
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable FEAT_CSV2_2 for -cpu max
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0042e0f6bf0c6dd808217ce38d39a2539ad2a1fb
https://github.com/qemu/qemu/commit/0042e0f6bf0c6dd808217ce38d39a2539ad2a1fb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_CSV3 for -cpu max
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7d5587c25282a930eebaffbcb4f7cc7308654f7c
https://github.com/qemu/qemu/commit/7d5587c25282a930eebaffbcb4f7cc7308654f7c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enable FEAT_DGH for -cpu max
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 369eced7b573a62ba71f4bf0cd5b60c947779b36
https://github.com/qemu/qemu/commit/369eced7b573a62ba71f4bf0cd5b60c947779b36
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Define cortex-a76
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c5bee3af0790a1bc52e6ced76a34b53d9d831106
https://github.com/qemu/qemu/commit/c5bee3af0790a1bc52e6ced76a34b53d9d831106
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Define neoverse-n1
Enable the n1 for virt and sbsa board use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d05b96e6a37a5148ef09c53a1f39ee8780f95f9e
https://github.com/qemu/qemu/commit/d05b96e6a37a5148ef09c53a1f39ee8780f95f9e
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm: add versioning to sbsa-ref machine DT
The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.
Introduce two new properties to the DT generated on machine generation:
- machine-version-major
To be incremented when a platform change makes the machine
incompatible with existing firmware.
- machine-version-minor
To be incremented when functionality is added to the machine
without causing incompatibility with existing firmware.
to be reset to 0 when machine-version-major is incremented.
This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.
The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fb90c68def2c0068f7b5e4afb769d192aa4dc6d6
https://github.com/qemu/qemu/commit/fb90c68def2c0068f7b5e4afb769d192aa4dc6d6
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/core/machine-hmp-cmds.c
M hw/core/machine.c
M qapi/machine.json
Log Message:
-----------
qapi/machine.json: Add cluster-id
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA node.
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
CPU slots with no NUMA mapping set.
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
cluster-id.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9faa0a023a38243e1798e52bd122551ccffd518f
https://github.com/qemu/qemu/commit/9faa0a023a38243e1798e52bd122551ccffd518f
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/numa-test.c
Log Message:
-----------
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
1.48s killed by signal 6 SIGABRT
>>>
G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon
\
QTEST_QEMU_BINARY=./qemu-system-aarch64
\
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83
\
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
――――――――――――――――――――――――――――――――――――――――――――――
stderr:
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 48bd8248b1328af17e4d00ca4b03f44ba4be6e2d
https://github.com/qemu/qemu/commit/48bd8248b1328af17e4d00ca4b03f44ba4be6e2d
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Consider SMP configuration in CPU topology
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d5f565aeb51589f67c12af7223de50a236272e1
https://github.com/qemu/qemu/commit/6d5f565aeb51589f67c12af7223de50a236272e1
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/numa-test.c
Log Message:
-----------
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.
NUMA-node socket cluster core thread
------------------------------------------
0 0 0 0 0
1 0 0 0 1
This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.
NUMA-node socket cluster core thread
------------------------------------------
0 1 0 0 0
1 0 0 0 0
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a84f201af2eb22d800da2b9cf99a1385eabbb676
https://github.com/qemu/qemu/commit/a84f201af2eb22d800da2b9cf99a1385eabbb676
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Fix CPU's default NUMA node ID
When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.
For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
-accel kvm -machine virt,gic-version=host \
-cpu host \
-smp 6,sockets=2,cores=3,threads=1 \
-m 1024M,slots=16,maxmem=64G \
-object memory-backend-ram,id=mem0,size=128M \
-object memory-backend-ram,id=mem1,size=128M \
-object memory-backend-ram,id=mem2,size=128M \
-object memory-backend-ram,id=mem3,size=128M \
-object memory-backend-ram,id=mem4,size=128M \
-object memory-backend-ram,id=mem4,size=384M \
-numa node,nodeid=0,memdev=mem0 \
-numa node,nodeid=1,memdev=mem1 \
-numa node,nodeid=2,memdev=mem2 \
-numa node,nodeid=3,memdev=mem3 \
-numa node,nodeid=4,memdev=mem4 \
-numa node,nodeid=5,memdev=mem5
:
alternatives: patching kernel code
BUG: arch topology borken
the CLS domain not a subset of the MC domain
<the above error log repeats>
BUG: arch topology borken
the DIE domain not a subset of the NODE domain
With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.
This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e82cdeba09b3886c2584327eade807169c2b4c1c
https://github.com/qemu/qemu/commit/e82cdeba09b3886c2584327eade807169c2b4c1c
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/acpi/aml-build.c
Log Message:
-----------
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b38300f6d29b70e769088d5c2607a0026527e9bd
https://github.com/qemu/qemu/commit/b38300f6d29b70e769088d5c2607a0026527e9bd
Author: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
A event-loop-base.c
A include/sysemu/event-loop-base.h
M include/sysemu/iothread.h
M iothread.c
M meson.build
M qapi/qom.json
Log Message:
-----------
Introduce event-loop-base abstract class
Introduce the 'event-loop-base' abstract class, it'll hold the
properties common to all event loops and provide the necessary hooks for
their creation and maintenance. Then have iothread inherit from it.
EventLoopBaseClass is defined as user creatable and provides a hook for
its children to attach themselves to the user creatable class 'complete'
function. It also provides an update_params() callback to propagate
property changes onto its children.
The new 'event-loop-base' class will live in the root directory. It is
built on its own using the 'link_whole' option (there are no direct
function dependencies between the class and its children, it all happens
trough 'constructor' magic). And also imposes new compilation
dependencies:
qom <- event-loop-base <- blockdev (iothread.c)
And in subsequent patches:
qom <- event-loop-base <- qemuutil (util/main-loop.c)
All this forced some amount of reordering in meson.build:
- Moved qom build definition before qemuutil. Doing it the other way
around (i.e. moving qemuutil after qom) isn't possible as a lot of
core libraries that live in between the two depend on it.
- Process the 'hw' subdir earlier, as it introduces files into the
'qom' source set.
No functional changes intended.
Signed-off-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 20220425075723.20019-2-nsaenzju@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 4ebf7bb6d4c205f09f61562158301553425b5414
https://github.com/qemu/qemu/commit/4ebf7bb6d4c205f09f61562158301553425b5414
Author: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M event-loop-base.c
M include/qemu/main-loop.h
M include/sysemu/event-loop-base.h
M meson.build
M qapi/qom.json
M util/main-loop.c
Log Message:
-----------
util/main-loop: Introduce the main loop into QOM
'event-loop-base' provides basic property handling for all 'AioContext'
based event loops. So let's define a new 'MainLoopClass' that inherits
from it. This will permit tweaking the main loop's properties through
qapi as well as through the command line using the '-object' keyword[1].
Only one instance of 'MainLoopClass' might be created at any time.
'EventLoopBaseClass' learns a new callback, 'can_be_deleted()' so as to
mark 'MainLoop' as non-deletable.
[1] For example:
-object main-loop,id=main-loop,aio-max-batch=<value>
Signed-off-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 20220425075723.20019-3-nsaenzju@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: f1bcf760027fa361c6b23444befc3aa7c48a0f13
https://github.com/qemu/qemu/commit/f1bcf760027fa361c6b23444befc3aa7c48a0f13
Author: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M event-loop-base.c
M include/block/aio.h
M include/block/thread-pool.h
M include/sysemu/event-loop-base.h
M iothread.c
M qapi/qom.json
M util/aio-posix.c
M util/async.c
M util/main-loop.c
M util/thread-pool.c
Log Message:
-----------
util/event-loop-base: Introduce options to set the thread pool size
The thread pool regulates itself: when idle, it kills threads until
empty, when in demand, it creates new threads until full. This behaviour
doesn't play well with latency sensitive workloads where the price of
creating a new thread is too high. For example, when paired with qemu's
'-mlock', or using safety features like SafeStack, creating a new thread
has been measured take multiple milliseconds.
In order to mitigate this let's introduce a new 'EventLoopBase'
property to set the thread pool size. The threads will be created during
the pool's initialization or upon updating the property's value, remain
available during its lifetime regardless of demand, and destroyed upon
freeing it. A properly characterized workload will then be able to
configure the pool to avoid any latency spikes.
Signed-off-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 20220425075723.20019-4-nsaenzju@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 3b8da4cc2c9d4d67211a369c2c66f60e3a4a4ebb
https://github.com/qemu/qemu/commit/3b8da4cc2c9d4d67211a369c2c66f60e3a4a4ebb
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi.c
Log Message:
-----------
virtio-scsi: fix ctrl and event handler functions in dataplane mode
Commit f34e8d8b8d48d73f36a67b6d5e492ef9784b5012 ("virtio-scsi: prepare
virtio_scsi_handle_cmd for dataplane") prepared the virtio-scsi cmd
virtqueue handler function to be used in both the dataplane and
non-datpalane code paths.
It failed to convert the ctrl and event virtqueue handler functions,
which are not designed to be called from the dataplane code path but
will be since the ioeventfd is set up for those virtqueues when
dataplane starts.
Convert the ctrl and event virtqueue handler functions now so they
operate correctly when called from the dataplane code path. Avoid code
duplication by extracting this code into a helper function.
Fixes: f34e8d8b8d48d73f36a67b6d5e492ef9784b5012 ("virtio-scsi: prepare
virtio_scsi_handle_cmd for dataplane")
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20220427143541.119567-2-stefanha@redhat.com
[Fixed s/by used/be used/ typo pointed out by Michael Tokarev
<mjt@tls.msk.ru>.
--Stefan]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: d10c4fff4f0c64b13330ea42f4c94439e5c2ae3e
https://github.com/qemu/qemu/commit/d10c4fff4f0c64b13330ea42f4c94439e5c2ae3e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi-dataplane.c
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio-scsi: don't waste CPU polling the event virtqueue
The virtio-scsi event virtqueue is not emptied by its handler function.
This is typical for rx virtqueues where the device uses buffers when
some event occurs (e.g. a packet is received, an error condition
happens, etc).
Polling non-empty virtqueues wastes CPU cycles. We are not waiting for
new buffers to become available, we are waiting for an event to occur,
so it's a misuse of CPU resources to poll for buffers.
Introduce the new virtio_queue_aio_attach_host_notifier_no_poll() API,
which is identical to virtio_queue_aio_attach_host_notifier() except
that it does not poll the virtqueue.
Before this patch the following command-line consumed 100% CPU in the
IOThread polling and calling virtio_scsi_handle_event():
$ qemu-system-x86_64 -M accel=kvm -m 1G -cpu host \
--object iothread,id=iothread0 \
--device virtio-scsi-pci,iothread=iothread0 \
--blockdev
file,filename=test.img,aio=native,cache.direct=on,node-name=drive0 \
--device scsi-hd,drive=drive0
After this patch CPU is no longer wasted.
Reported-by: Nir Soffer <nsoffer@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Tested-by: Nir Soffer <nsoffer@redhat.com>
Message-id: 20220427143541.119567-3-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: d6d63e23187affbe57d3ffab2d1471506ac443a1
https://github.com/qemu/qemu/commit/d6d63e23187affbe57d3ffab2d1471506ac443a1
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi.c
M include/hw/virtio/virtio-scsi.h
Log Message:
-----------
virtio-scsi: clean up virtio_scsi_handle_event_vq()
virtio_scsi_handle_event_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20220427143541.119567-4-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 3a2445c54f29f3403dcd6256b6dc66e7aa717480
https://github.com/qemu/qemu/commit/3a2445c54f29f3403dcd6256b6dc66e7aa717480
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi.c
M include/hw/virtio/virtio-scsi.h
Log Message:
-----------
virtio-scsi: clean up virtio_scsi_handle_ctrl_vq()
virtio_scsi_handle_ctrl_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20220427143541.119567-5-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: c854b6cb39a9b9f3275230e01766936d04331a78
https://github.com/qemu/qemu/commit/c854b6cb39a9b9f3275230e01766936d04331a78
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi.c
M include/hw/virtio/virtio-scsi.h
Log Message:
-----------
virtio-scsi: clean up virtio_scsi_handle_cmd_vq()
virtio_scsi_handle_cmd_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20220427143541.119567-6-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 9d66a1fe6b1f83bc27ce78c1d56bece967340052
https://github.com/qemu/qemu/commit/9d66a1fe6b1f83bc27ce78c1d56bece967340052
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/scsi/virtio-scsi.c
M include/hw/virtio/virtio-scsi.h
Log Message:
-----------
virtio-scsi: move request-related items from .h to .c
There is no longer a need to expose the request and related APIs in
virtio-scsi.h since there are no callers outside virtio-scsi.c.
Note the block comment in VirtIOSCSIReq has been adjusted to meet the
coding style.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20220427143541.119567-7-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: d9e3d630902529b5252891ef7e6b1123ac488c3a
https://github.com/qemu/qemu/commit/d9e3d630902529b5252891ef7e6b1123ac488c3a
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M accel/tcg/tcg-accel-ops-icount.h
M accel/tcg/tcg-accel-ops-mttcg.h
M accel/tcg/tcg-accel-ops-rr.h
M accel/tcg/tcg-accel-ops.h
M block/coroutines.h
M bsd-user/arm/target_syscall.h
M bsd-user/i386/target.h
M bsd-user/i386/target_arch_sysarch.h
M bsd-user/x86_64/target_arch_sysarch.h
M hw/i386/e820_memory_layout.h
M hw/net/can/ctu_can_fd_frame.h
M hw/net/can/ctu_can_fd_regs.h
M hw/nvme/nvme.h
M hw/usb/hcd-dwc2.h
M include/block/block-hmp-cmds.h
M include/crypto/tls-cipher-suites.h
M include/hw/acpi/generic_event_device.h
M include/hw/i2c/arm_sbcon_i2c.h
M include/hw/misc/bcm2835_cprman.h
M include/hw/misc/bcm2835_cprman_internals.h
M include/hw/misc/stm32f4xx_exti.h
M include/hw/misc/stm32f4xx_syscfg.h
M include/hw/misc/xlnx-versal-pmc-iou-slcr.h
M include/hw/net/mv88w8618_eth.h
M include/hw/nubus/mac-nubus-bridge.h
M include/hw/pci-host/remote.h
M include/hw/riscv/boot_opensbi.h
M include/hw/riscv/shakti_c.h
M include/hw/rtc/sun4v-rtc.h
M include/hw/rtc/xlnx-zynqmp-rtc.h
M include/hw/rx/rx62n.h
M include/hw/sensor/emc141x_regs.h
M include/hw/ssi/xlnx-versal-ospi.h
M include/hw/timer/bcm2835_systmr.h
M include/hw/tricore/tricore_testdevice.h
M include/hw/usb/dwc2-regs.h
M include/hw/usb/hcd-musb.h
M include/hw/usb/xlnx-usb-subsystem.h
M include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
M include/hw/watchdog/wdt_imx2.h
M include/qemu/help-texts.h
M include/qemu/qemu-plugin.h
M include/sysemu/block-backend-global-state.h
M plugins/plugin.h
M target/arm/translate-a32.h
M target/arm/vec_internal.h
M target/avr/cpu-qom.h
M target/hexagon/hex_arch_types.h
M target/hexagon/hex_regs.h
M target/i386/hax/hax-accel-ops.h
M target/i386/nvmm/nvmm-accel-ops.h
M target/i386/sev.h
M target/i386/whpx/whpx-accel-ops.h
M target/i386/whpx/whpx-internal.h
M target/xtensa/core-de233_fpu/core-isa.h
M target/xtensa/core-dsp3400/core-isa.h
M tests/qtest/fuzz/fuzz.h
M tools/virtiofsd/passthrough_seccomp.h
Log Message:
-----------
Clean up header guards that don't match their file name
Header guard symbols should match their file name to make guard
collisions less likely.
Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220506134911.2856099-2-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[Change to generated file ebpf/rss.bpf.skeleton.h backed out]
Commit: 4b850ffe62ff2d0d70cf234512f48e0c1d1a587e
https://github.com/qemu/qemu/commit/4b850ffe62ff2d0d70cf234512f48e0c1d1a587e
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M block/copy-on-read.h
M bsd-user/arm/target_arch.h
M bsd-user/arm/target_arch_cpu.h
M bsd-user/arm/target_arch_elf.h
M bsd-user/arm/target_arch_reg.h
M bsd-user/arm/target_arch_signal.h
M bsd-user/arm/target_arch_sigtramp.h
M bsd-user/arm/target_arch_sysarch.h
M bsd-user/arm/target_arch_thread.h
M bsd-user/arm/target_arch_vmparam.h
M bsd-user/bsd-file.h
M bsd-user/errno_defs.h
M bsd-user/freebsd/host-os.h
M bsd-user/freebsd/target_os_elf.h
M bsd-user/freebsd/target_os_siginfo.h
M bsd-user/freebsd/target_os_signal.h
M bsd-user/freebsd/target_os_stack.h
M bsd-user/freebsd/target_os_thread.h
M bsd-user/freebsd/target_os_user.h
M bsd-user/freebsd/target_os_vmparam.h
M bsd-user/i386/target_arch.h
M bsd-user/i386/target_arch_cpu.h
M bsd-user/i386/target_arch_elf.h
M bsd-user/i386/target_arch_reg.h
M bsd-user/i386/target_arch_sigtramp.h
M bsd-user/i386/target_arch_thread.h
M bsd-user/i386/target_arch_vmparam.h
M bsd-user/netbsd/host-os.h
M bsd-user/netbsd/target_os_elf.h
M bsd-user/netbsd/target_os_siginfo.h
M bsd-user/netbsd/target_os_signal.h
M bsd-user/netbsd/target_os_stack.h
M bsd-user/netbsd/target_os_thread.h
M bsd-user/openbsd/host-os.h
M bsd-user/openbsd/target_os_elf.h
M bsd-user/openbsd/target_os_siginfo.h
M bsd-user/openbsd/target_os_signal.h
M bsd-user/openbsd/target_os_stack.h
M bsd-user/openbsd/target_os_thread.h
M bsd-user/syscall_defs.h
M bsd-user/x86_64/target_arch.h
M bsd-user/x86_64/target_arch_cpu.h
M bsd-user/x86_64/target_arch_elf.h
M bsd-user/x86_64/target_arch_reg.h
M bsd-user/x86_64/target_arch_signal.h
M bsd-user/x86_64/target_arch_sigtramp.h
M bsd-user/x86_64/target_arch_thread.h
M bsd-user/x86_64/target_arch_vmparam.h
M crypto/ivgen-plain.h
M include/chardev/char-socket.h
M include/hw/i2c/i2c_mux_pca954x.h
M include/hw/input/lm832x.h
M include/hw/intc/exynos4210_combiner.h
M include/hw/intc/nios2_vic.h
M include/hw/ppc/pnv_pnor.h
M include/hw/s390x/s390-pci-clp.h
M include/hw/tricore/tc27x_soc.h
M include/hw/virtio/vhost-user-fs.h
M include/hw/virtio/vhost-user-i2c.h
M include/hw/virtio/vhost-user-rng.h
M include/hw/virtio/vhost-user-vsock.h
M include/hw/virtio/vhost-vsock-common.h
M include/qemu/cpu-float.h
M include/qemu/crc-ccitt.h
M include/qemu/keyval.h
M include/ui/dbus-display.h
M include/ui/dbus-module.h
M target/ppc/power8-pmu.h
M target/riscv/sbi_ecall_interface.h
M tests/qtest/libqmp.h
M tests/qtest/migration-helpers.h
M ui/dbus.h
Log Message:
-----------
Clean up ill-advised or unusual header guards
Leading underscores are ill-advised because such identifiers are
reserved. Trailing underscores are merely ugly. Strip both.
Our header guards commonly end in _H. Normalize the exceptions.
Macros should be ALL_CAPS. Normalize the exception.
Done with scripts/clean-header-guards.pl.
include/hw/xen/interface/ and tools/virtiofsd/ left alone, because
these were imported from Xen and libfuse respectively.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220506134911.2856099-3-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 969f8416b1ca89e58c4c4935cc3947f40dc1f386
https://github.com/qemu/qemu/commit/969f8416b1ca89e58c4c4935cc3947f40dc1f386
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/exec/memopidx.h
M include/tcg/tcg-ldst.h
M target/alpha/cpu-param.h
M target/arm/cpu-param.h
M target/cris/cpu-param.h
M target/hppa/cpu-param.h
M target/i386/cpu-param.h
M target/m68k/cpu-param.h
M target/microblaze/cpu-param.h
M target/mips/cpu-param.h
M target/nios2/cpu-param.h
M target/openrisc/cpu-param.h
M target/ppc/cpu-param.h
M target/riscv/cpu-param.h
M target/s390x/cpu-param.h
M target/sh4/cpu-param.h
M target/sparc/cpu-param.h
M target/tricore/cpu-param.h
M target/xtensa/cpu-param.h
M tcg/tcg-internal.h
Log Message:
-----------
Normalize header guard symbol definition
We commonly define the header guard symbol without an explicit value.
Normalize the exceptions.
Done with scripts/clean-header-guards.pl.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220506134911.2856099-4-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 12bdd7560f8e4cd44a5dda3952c1a26dd2e2168a
https://github.com/qemu/qemu/commit/12bdd7560f8e4cd44a5dda3952c1a26dd2e2168a
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M bsd-user/arm/target.h
M bsd-user/x86_64/target.h
M chardev/chardev-internal.h
M include/block/block_int-global-state.h
M include/exec/translator.h
M include/fpu/softfloat-helpers.h
M include/hw/gpio/aspeed_gpio.h
M include/hw/intc/rx_icu.h
M include/hw/misc/aspeed_hace.h
M include/hw/misc/aspeed_lpc.h
M include/hw/misc/aspeed_sbc.h
M include/hw/net/allwinner-sun8i-emac.h
M include/hw/rtc/m48t59.h
M include/hw/rtc/mc146818rtc.h
M include/qemu/plugin-memory.h
M include/qemu/selfmap.h
M include/user/syscall-trace.h
M linux-user/hexagon/target_signal.h
M target/avr/cpu.h
M target/hexagon/attribs.h
M target/xtensa/core-de233_fpu/core-matmap.h
M target/xtensa/core-dsp3400/core-matmap.h
Log Message:
-----------
Clean up decorations and whitespace around header guards
Cleaned up with scripts/clean-header-guards.pl.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220506134911.2856099-5-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: de658e34c71a2b218a32fd6516a13f4249c26bc0
https://github.com/qemu/qemu/commit/de658e34c71a2b218a32fd6516a13f4249c26bc0
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/block/virtio-blk.c
M include/qemu/coroutine.h
M util/qemu-coroutine.c
Log Message:
-----------
coroutine: Rename qemu_coroutine_inc/dec_pool_size()
It's true that these functions currently affect the batch size in which
coroutines are reused (i.e. moved from the global release pool to the
allocation pool of a specific thread), but this is a bug and will be
fixed in a separate patch.
In fact, the comment in the header file already just promises that it
influences the pool size, so reflect this in the name of the functions.
As a nice side effect, the shorter function name makes some line
wrapping unnecessary.
Cc: qemu-stable@nongnu.org
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220510151020.105528-2-kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 9119582d6e091a91d052d647f5eafa382109dcbd
https://github.com/qemu/qemu/commit/9119582d6e091a91d052d647f5eafa382109dcbd
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M util/qemu-coroutine.c
Log Message:
-----------
coroutine: Revert to constant batch size
Commit 4c41c69e changed the way the coroutine pool is sized because for
virtio-blk devices with a large queue size and heavy I/O, it was just
too small and caused coroutines to be deleted and reallocated soon
afterwards. The change made the size dynamic based on the number of
queues and the queue size of virtio-blk devices.
There are two important numbers here: Slightly simplified, when a
coroutine terminates, it is generally stored in the global release pool
up to a certain pool size, and if the pool is full, it is freed.
Conversely, when allocating a new coroutine, the coroutines in the
release pool are reused if the pool already has reached a certain
minimum size (the batch size), otherwise we allocate new coroutines.
The problem after commit 4c41c69e is that it not only increases the
maximum pool size (which is the intended effect), but also the batch
size for reusing coroutines (which is a bug). It means that in cases
with many devices and/or a large queue size (which defaults to the
number of vcpus for virtio-blk-pci), many thousand coroutines could be
sitting in the release pool without being reused.
This is not only a waste of memory and allocations, but it actually
makes the QEMU process likely to hit the vm.max_map_count limit on Linux
because each coroutine requires two mappings (its stack and the guard
page for the stack), causing it to abort() in qemu_alloc_stack() because
when the limit is hit, mprotect() starts to fail with ENOMEM.
In order to fix the problem, change the batch size back to 64 to avoid
uselessly accumulating coroutines in the release pool, but keep the
dynamic maximum pool size so that coroutines aren't freed too early
in heavy I/O scenarios.
Note that this fix doesn't strictly make it impossible to hit the limit,
but this would only happen if most of the coroutines are actually in use
at the same time, not just sitting in a pool. This is the same behaviour
as we already had before commit 4c41c69e. Fully preventing this would
require allowing qemu_coroutine_create() to return an error, but it
doesn't seem to be a scenario that people hit in practice.
Cc: qemu-stable@nongnu.org
Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2079938
Fixes: 4c41c69e05fe28c0f95f8abd2ebf407e95a4f04b
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220510151020.105528-3-kwolf@redhat.com>
Tested-by: Hiroki Narukawa <hnarukaw@yahoo-corp.jp>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 631bd20a03d0931276e3469179a8fc6d63d1172d
https://github.com/qemu/qemu/commit/631bd20a03d0931276e3469179a8fc6d63d1172d
Author: Hanna Reitz <hreitz@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qemu-iotests/testrunner.py
Log Message:
-----------
iotests/testrunner: Flush after run_test()
When stdout is not a terminal, the buffer may not be flushed at each end
of line, so we should flush after each test is done. This is especially
apparent when run by check-block, in two ways:
First, when running make check-block -jX with X > 1, progress indication
was missing, even though testrunner.py does theoretically print each
test's status once it has been run, even in multi-processing mode.
Flushing after each test restores this progress indication.
Second, sometimes make check-block failed altogether, with an error
message that "too few tests [were] run". I presume that's because one
worker process in the job pool did not get to flush its stdout before
the main process exited, and so meson did not get to see that worker's
test results. In any case, by flushing at the end of run_test(), the
problem has disappeared for me.
Signed-off-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <20220506134215.10086-1-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 725a13a43a15191deef1622545a172a7fe969c43
https://github.com/qemu/qemu/commit/725a13a43a15191deef1622545a172a7fe969c43
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qemu-iotests/testrunner.py
Log Message:
-----------
tests/qemu-iotests: print intent to run a test in TAP mode
When running I/O tests using TAP output mode, we get a single TAP test
with a sub-test reported for each I/O test that is run. The output looks
something like this:
1..123
ok qcow2 011
ok qcow2 012
ok qcow2 013
ok qcow2 217
...
If everything runs or fails normally this is fine, but periodically we
have been seeing the test harness abort early before all 123 tests have
been run, just leaving a fairly useless message like
TAP parsing error: Too few tests run (expected 123, got 107)
we have no idea which tests were running at the time the test harness
abruptly exited. This change causes us to print a message about our
intent to run each test, so we have a record of what is active at the
time the harness exits abnormally.
1..123
# running qcow2 011
ok qcow2 011
# running qcow2 012
ok qcow2 012
# running qcow2 013
ok qcow2 013
# running qcow2 217
ok qcow2 217
...
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220509124134.867431-2-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: a3f8d67d9cc2df7e03d395022ca4f9af989ac822
https://github.com/qemu/qemu/commit/a3f8d67d9cc2df7e03d395022ca4f9af989ac822
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/buildtest-template.yml
Log Message:
-----------
.gitlab-ci.d: export meson testlog.txt as an artifact
When running 'make check' we only get a summary of progress on the
console. Fortunately meson/ninja have saved the raw test output to a
logfile. Exposing this log will make it easier to debug failures that
happen in CI.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220509124134.867431-3-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 87f040e4027af58fa19e6229a3da00cdefbe4b44
https://github.com/qemu/qemu/commit/87f040e4027af58fa19e6229a3da00cdefbe4b44
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/block/fdc.c
Log Message:
-----------
hw/block/fdc: Prevent end-of-track overrun (CVE-2021-3507)
Per the 82078 datasheet, if the end-of-track (EOT byte in
the FIFO) is more than the number of sectors per side, the
command is terminated unsuccessfully:
* 5.2.5 DATA TRANSFER TERMINATION
The 82078 supports terminal count explicitly through
the TC pin and implicitly through the underrun/over-
run and end-of-track (EOT) functions. For full sector
transfers, the EOT parameter can define the last
sector to be transferred in a single or multisector
transfer. If the last sector to be transferred is a par-
tial sector, the host can stop transferring the data in
mid-sector, and the 82078 will continue to complete
the sector as if a hardware TC was received. The
only difference between these implicit functions and
TC is that they return "abnormal termination" result
status. Such status indications can be ignored if they
were expected.
* 6.1.3 READ TRACK
This command terminates when the EOT specified
number of sectors have been read. If the 82078
does not find an I D Address Mark on the diskette
after the second· occurrence of a pulse on the
INDX# pin, then it sets the IC code in Status Regis-
ter 0 to "01" (Abnormal termination), sets the MA bit
in Status Register 1 to "1", and terminates the com-
mand.
* 6.1.6 VERIFY
Refer to Table 6-6 and Table 6-7 for information
concerning the values of MT and EC versus SC and
EOT value.
* Table 6·6. Result Phase Table
* Table 6-7. Verify Command Result Phase Table
Fix by aborting the transfer when EOT > # Sectors Per Side.
Cc: qemu-stable@nongnu.org
Cc: Hervé Poussineau <hpoussin@reactos.org>
Fixes: baca51faff0 ("floppy driver: disk geometry auto detect")
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/339
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211118115733.4038610-2-philmd@redhat.com>
Reviewed-by: Hanna Reitz <hreitz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 0946a2805a3b91bacec545e89f332202d7dfdcf1
https://github.com/qemu/qemu/commit/0946a2805a3b91bacec545e89f332202d7dfdcf1
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/fdc-test.c
Log Message:
-----------
tests/qtest/fdc-test: Add a regression test for CVE-2021-3507
Add the reproducer from https://gitlab.com/qemu-project/qemu/-/issues/339
Without the previous commit, when running 'make check-qtest-i386'
with QEMU configured with '--enable-sanitizers' we get:
==4028352==ERROR: AddressSanitizer: heap-buffer-overflow on address
0x619000062a00 at pc 0x5626d03c491a bp 0x7ffdb4199410 sp 0x7ffdb4198bc0
READ of size 786432 at 0x619000062a00 thread T0
#0 0x5626d03c4919 in __asan_memcpy (qemu-system-i386+0x1e65919)
#1 0x5626d1c023cc in flatview_write_continue softmmu/physmem.c:2787:13
#2 0x5626d1bf0c0f in flatview_write softmmu/physmem.c:2822:14
#3 0x5626d1bf0798 in address_space_write softmmu/physmem.c:2914:18
#4 0x5626d1bf0f37 in address_space_rw softmmu/physmem.c:2924:16
#5 0x5626d1bf14c8 in cpu_physical_memory_rw softmmu/physmem.c:2933:5
#6 0x5626d0bd5649 in cpu_physical_memory_write
include/exec/cpu-common.h:82:5
#7 0x5626d0bd0a07 in i8257_dma_write_memory hw/dma/i8257.c:452:9
#8 0x5626d09f825d in fdctrl_transfer_handler hw/block/fdc.c:1616:13
#9 0x5626d0a048b4 in fdctrl_start_transfer hw/block/fdc.c:1539:13
#10 0x5626d09f4c3e in fdctrl_write_data hw/block/fdc.c:2266:13
#11 0x5626d09f22f7 in fdctrl_write hw/block/fdc.c:829:9
#12 0x5626d1c20bc5 in portio_write softmmu/ioport.c:207:17
0x619000062a00 is located 0 bytes to the right of 512-byte region
[0x619000062800,0x619000062a00)
allocated by thread T0 here:
#0 0x5626d03c66ec in posix_memalign (qemu-system-i386+0x1e676ec)
#1 0x5626d2b988d4 in qemu_try_memalign util/oslib-posix.c:210:11
#2 0x5626d2b98b0c in qemu_memalign util/oslib-posix.c:226:27
#3 0x5626d09fbaf0 in fdctrl_realize_common hw/block/fdc.c:2341:20
#4 0x5626d0a150ed in isabus_fdc_realize hw/block/fdc-isa.c:113:5
#5 0x5626d2367935 in device_set_realized hw/core/qdev.c:531:13
SUMMARY: AddressSanitizer: heap-buffer-overflow (qemu-system-i386+0x1e65919)
in __asan_memcpy
Shadow bytes around the buggy address:
0x0c32800044f0: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c3280004510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c3280004520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c3280004530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
=>0x0c3280004540:[fa]fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004550: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004560: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004570: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004580: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c3280004590: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
Shadow byte legend (one shadow byte represents 8 application bytes):
Addressable: 00
Heap left redzone: fa
Freed heap region: fd
==4028352==ABORTING
[ kwolf: Added snapshot=on to prevent write file lock failure ]
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 36339f500d0365a1971bb22818d7af030584d4bd
https://github.com/qemu/qemu/commit/36339f500d0365a1971bb22818d7af030584d4bd
Author: Eric Blake <eblake@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M blockdev-nbd.c
M include/block/nbd.h
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: Pass max connections to blockdev layer
The next patch wants to adjust whether the NBD server code advertises
MULTI_CONN based on whether it is known if the server limits to
exactly one client. For a server started by QMP, this information is
obtained through nbd_server_start (which can support more than one
export); but for qemu-nbd (which supports exactly one export), it is
controlled only by the command-line option -e/--shared. Since we
already have a hook function used by qemu-nbd, it's easiest to just
alter its signature to fit our needs.
Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <20220512004924.417153-2-eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: b8b6125634e3f47d95525e4acde392b07282f014
https://github.com/qemu/qemu/commit/b8b6125634e3f47d95525e4acde392b07282f014
Author: Eric Blake <eblake@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
M blockdev-nbd.c
M docs/interop/nbd.txt
M docs/tools/qemu-nbd.rst
M include/block/nbd.h
M nbd/server.c
M qapi/block-export.json
A tests/qemu-iotests/tests/nbd-multiconn
A tests/qemu-iotests/tests/nbd-multiconn.out
M tests/qemu-iotests/tests/nbd-qemu-allocation.out
Log Message:
-----------
nbd/server: Allow MULTI_CONN for shared writable exports
According to the NBD spec, a server that advertises
NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
not see any cache inconsistencies: when properly separated by a single
flush, actions performed by one client will be visible to another
client, regardless of which client did the flush.
We always satisfy these conditions in qemu - even when we support
multiple clients, ALL clients go through a single point of reference
into the block layer, with no local caching. The effect of one client
is instantly visible to the next client. Even if our backend were a
network device, we argue that any multi-path caching effects that
would cause inconsistencies in back-to-back actions not seeing the
effect of previous actions would be a bug in that backend, and not the
fault of caching in qemu. As such, it is safe to unconditionally
advertise CAN_MULTI_CONN for any qemu NBD server situation that
supports parallel clients.
Note, however, that we don't want to advertise CAN_MULTI_CONN when we
know that a second client cannot connect (for historical reasons,
qemu-nbd defaults to a single connection while nbd-server-add and QMP
commands default to unlimited connections; but we already have
existing means to let either style of NBD server creation alter those
defaults). This is visible by no longer advertising MULTI_CONN for
'qemu-nbd -r' without -e, as in the iotest nbd-qemu-allocation.
The harder part of this patch is setting up an iotest to demonstrate
behavior of multiple NBD clients to a single server. It might be
possible with parallel qemu-io processes, but I found it easier to do
in python with the help of libnbd, and help from Nir and Vladimir in
writing the test.
Signed-off-by: Eric Blake <eblake@redhat.com>
Suggested-by: Nir Soffer <nsoffer@redhat.com>
Suggested-by: Vladimir Sementsov-Ogievskiy <v.sementsov-og@mail.ru>
Message-Id: <20220512004924.417153-3-eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 96a573a0ba175f47bb893268d7b5e911773b052b
https://github.com/qemu/qemu/commit/96a573a0ba175f47bb893268d7b5e911773b052b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
R tests/qemu-iotests/common.config
M tests/qemu-iotests/common.rc
Log Message:
-----------
qemu-iotests: inline common.config into common.rc
common.rc has some complicated logic to find the common.config that
dates back to xfstests and is completely unnecessary now. Just include
the contents of the file.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220505094723.732116-1-pbonzini@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 8017df79a0863789eaab1153514e41c69c79260f
https://github.com/qemu/qemu/commit/8017df79a0863789eaab1153514e41c69c79260f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/optionrom/Makefile
Log Message:
-----------
pc-bios/optionrom: detect -fno-pie
Do not rely on the detection that was done in the configure script,
since in the future we may want to cross-compile this file.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d12ab4882a67739e7d2b8ac89cdc3428c8a866aa
https://github.com/qemu/qemu/commit/d12ab4882a67739e7d2b8ac89cdc3428c8a866aa
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M pc-bios/optionrom/Makefile
Log Message:
-----------
pc-bios/optionrom: compile with -Wno-array-bounds
Avoids the following bogus warning:
pvh_main.c: In function ‘pvh_load_kernel’:
pvh_main.c:101:42: warning: array subscript 0 is outside array bounds of
‘uint16_t[0]’ {aka ‘short unsigned int[]’} [-Warray-bounds]
101 | uint32_t ebda_paddr = ((uint32_t)*((uint16_t *)EBDA_BASE_ADDR))
<< 4;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Cc: qemu-stable@nongnu.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8f939a65f5b11a47865f18037d069899af700a99
https://github.com/qemu/qemu/commit/8f939a65f5b11a47865f18037d069899af700a99
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: do not consult nonexistent host leaves
When cache_info_passthrough is requested, QEMU passes the host values
of the cache information CPUID leaves down to the guest. However,
it blindly assumes that the CPUID leaf exists on the host, and this
cannot be guaranteed: for example, KVM has recently started to
synthesize AMD leaves up to 0x80000021 in order to provide accurate
CPU bug information to guests.
Querying a nonexistent host leaf fills the output arguments of
host_cpuid with data that (albeit deterministic) is nonsensical
as cache information, namely the data in the highest Intel CPUID
leaf. If said highest leaf is not ECX-dependent, this can even
cause an infinite loop when kvm_arch_init_vcpu prepares the input
to KVM_SET_CPUID2. The infinite loop is only terminated by an
abort() when the array gets full.
Reported-by: Maxim Levitsky <mlevitsk@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 86b2014fcae739d46cb8ed2e6ac7db80d25195b1
https://github.com/qemu/qemu/commit/86b2014fcae739d46cb8ed2e6ac7db80d25195b1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M scripts/checkpatch.pl
Log Message:
-----------
checkpatch: fix g_malloc check
Use the string equality operator "eq", and ensure that $1 is defined by
using "(try|)" instead of "(try)?". The alternative "((?:try)?)" is
longer and less readable.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7243e25624d15037102f6ee320443820b35e6adb
https://github.com/qemu/qemu/commit/7243e25624d15037102f6ee320443820b35e6adb
Author: Juan Quintela <quintela@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson: Make mremap() detecting works correctly
Without this (at least in Fedora 35) it don't detect mremap()
correctly.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20220502131119.2345-1-quintela@redhat.com>
[Also switch the LEGACY_RDMA_REG_MR test to cc.links, otherwise
Debian fails to build. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9a981cdc944f3fdc9d73fc073b57684106c509fb
https://github.com/qemu/qemu/commit/9a981cdc944f3fdc9d73fc073b57684106c509fb
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/pc_piix.c
M hw/xen/xen_pt.c
M hw/xen/xen_pt.h
M hw/xen/xen_pt_graphics.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/xen/xen_pt: Confine igd-passthrough-isa-bridge to XEN
igd-passthrough-isa-bridge is only requested in xen_pt but was
implemented in pc_piix.c. This caused xen_pt to dependend on i386/pc
which is hereby resolved.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20220326165825.30794-2-shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1dd29e1ec34a68cdb9605ca046b883d1b2d72792
https://github.com/qemu/qemu/commit/1dd29e1ec34a68cdb9605ca046b883d1b2d72792
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/xen/xen_pt.c
M hw/xen/xen_pt.h
M hw/xen/xen_pt_graphics.c
Log Message:
-----------
hw/xen/xen_pt: Resolve igd_passthrough_isa_bridge_create() indirection
Now that igd_passthrough_isa_bridge_create() is implemented within the
xen context it may use Xen* data types directly and become
xen_igd_passthrough_isa_bridge_create(). This resolves an indirection.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20220326165825.30794-3-shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: eb28e57ec9d25b875d6c6e6bb91115b1cb037034
https://github.com/qemu/qemu/commit/eb28e57ec9d25b875d6c6e6bb91115b1cb037034
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/libqos/pci-pc.c
M tests/qtest/libqos/pci-spapr.c
M tests/qtest/libqos/pci.c
M tests/qtest/libqos/pci.h
Log Message:
-----------
tests/qtest/libqos/pci: Introduce pio_limit
At the moment the IO space limit is hardcoded to
QPCI_PIO_LIMIT = 0x10000. When accesses are performed to a bar,
the base address of this latter is compared against the limit
to decide whether we perform an IO or a memory access.
On ARM, we cannot keep this PIO limit as the arm-virt machine
uses [0x3eff0000, 0x3f000000 ] for the IO space map and we
are mandated to allocate at 0x0.
Add a new flag in QPCIBar indicating whether it is an IO bar
or a memory bar. This flag is set on QPCIBar allocation and
provisionned based on the BAR configuration. Then the new flag
is used in access functions and in iomap() function.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220504152025.1785704-2-eric.auger@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f0c8c875fe2534395324bcf4075a6dbf2138594a
https://github.com/qemu/qemu/commit/f0c8c875fe2534395324bcf4075a6dbf2138594a
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/e1000e-test.c
M tests/qtest/libqos/pci.h
M tests/qtest/vhost-user-blk-test.c
M tests/qtest/virtio-blk-test.c
M tests/qtest/virtio-net-test.c
M tests/qtest/virtio-rng-test.c
Log Message:
-----------
tests/qtest/libqos: Skip hotplug tests if pci root bus is not hotpluggable
ARM does not not support hotplug on pcie.0. Add a flag on the bus
which tells if devices can be hotplugged and skip hotplug tests
if the bus cannot be hotplugged. This is a temporary solution to
enable the other pci tests on aarch64.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220504152025.1785704-3-eric.auger@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6385bd52332dcec1d400260b8c528b1192f93966
https://github.com/qemu/qemu/commit/6385bd52332dcec1d400260b8c528b1192f93966
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/libqos/arm-virt-machine.c
A tests/qtest/libqos/generic-pcihost.c
A tests/qtest/libqos/generic-pcihost.h
M tests/qtest/libqos/meson.build
Log Message:
-----------
tests/qtest/libqos: Add generic pci host bridge in arm-virt machine
Up to now the virt-machine node contains a virtio-mmio node.
However no driver produces any PCI interface node. Hence, PCI
tests cannot be run with aarch64 binary.
Add a GPEX driver node that produces a pci interface node. This latter
then can be consumed by all the pci tests. One of the first motivation
was to be able to run the virtio-iommu-pci tests.
We still face an issue with pci hotplug tests as hotplug cannot happen
on the pcie root bus and require a generic root port. This will be
addressed later on.
We force cpu=max along with aarch64/virt machine as some PCI tests
require high MMIO regions to be available.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20220504152025.1785704-4-eric.auger@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9ba7d14a3ba7f8a87d231c1b025c64f9f3cdeb30
https://github.com/qemu/qemu/commit/9ba7d14a3ba7f8a87d231c1b025c64f9f3cdeb30
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/nseries.c
M hw/core/machine.c
M hw/hppa/machine.c
M hw/i386/pc.c
M hw/nvram/fw_cfg.c
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/prep.c
M hw/ppc/spapr.c
M hw/s390x/ipl.c
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
M include/hw/boards.h
M include/sysemu/sysemu.h
M qapi/machine.json
M softmmu/bootdevice.c
M softmmu/globals.c
M softmmu/vl.c
Log Message:
-----------
machine: use QAPI struct for boot configuration
As part of converting -boot to a property with a QAPI type, define
the struct and use it throughout QEMU to access boot configuration.
machine_boot_parse takes care of doing the QemuOpts->QAPI conversion by
hand, for now.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414165300.555321-2-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 74deba589dc1131a9e3dd117af5e91ec7422b171
https://github.com/qemu/qemu/commit/74deba589dc1131a9e3dd117af5e91ec7422b171
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M include/hw/boards.h
M softmmu/vl.c
Log Message:
-----------
machine: add boot compound property
Make -boot syntactic sugar for a compound property "-machine
boot.{order,menu,...}".
machine_boot_parse is replaced by the setter for the property.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414165300.555321-3-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 99c427daf1d13ee1428fee32e5b2f867b6d4f49c
https://github.com/qemu/qemu/commit/99c427daf1d13ee1428fee32e5b2f867b6d4f49c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M qapi/machine.json
M softmmu/vl.c
Log Message:
-----------
machine: add mem compound property
Make -m syntactic sugar for a compound property "-machine
mem.{size,max-size,slots}". The new property does not have
the magic conversion to megabytes of unsuffixed arguments,
and also does not understand that "0" means the default size
(you have to leave it out to get the default). This means
that we need to convert the QemuOpts by hand to a QDict.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414165300.555321-4-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 91b02d6a5f3a7de7c8b14878a824fa18beb6f75f
https://github.com/qemu/qemu/commit/91b02d6a5f3a7de7c8b14878a824fa18beb6f75f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M hw/core/numa.c
M hw/sparc/sun4m.c
M include/hw/boards.h
M softmmu/vl.c
Log Message:
-----------
machine: make memory-backend a link property
Handle HostMemoryBackend creation and setting of ms->ram entirely in
machine_run_board_init.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414165300.555321-5-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 59753d84762557a0f0efbeb0733e923b9d33f48d
https://github.com/qemu/qemu/commit/59753d84762557a0f0efbeb0733e923b9d33f48d
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M softmmu/vl.c
Log Message:
-----------
machine: move more memory validation to Machine object
This allows setting memory properties without going through
vl.c, and have them validated just the same.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220414165300.555321-6-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 751541c654c5bf9dfd62566f46f55d4228e943ee
https://github.com/qemu/qemu/commit/751541c654c5bf9dfd62566f46f55d4228e943ee
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M slirp
Log Message:
-----------
slirp: bump submodule past 4.7 release
Version 4.7 of slirp provides a new timer API that works better with CFI,
together with several other improvements:
* Allow disabling the internal DHCP server !22
* Support Unix sockets in hostfwd !103
* IPv6 DNS proxying support !110
* bootp: add support for UEFI HTTP boot !111
and bugfixes.
The submodule update also includes 2 commits to fix warnings in the
Win32 build.
Reviewed-by: Marc-André Lureau <malureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a06eb568bdcdb9cedd46fb3c984d514fe5d115b8
https://github.com/qemu/qemu/commit/a06eb568bdcdb9cedd46fb3c984d514fe5d115b8
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/slirp.c
Log Message:
-----------
net: slirp: introduce a wrapper struct for QemuTimer
This struct will be extended in the next few patches to support the
new slirp_handle_timer() call. For that we need to store an additional
"int" for each SLIRP timer, in addition to the cb_opaque.
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Reviewed-by: Marc-André Lureau <malureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9324404fb3a93e99962a94f7a74dbc3af75bf360
https://github.com/qemu/qemu/commit/9324404fb3a93e99962a94f7a74dbc3af75bf360
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
M net/slirp.c
Log Message:
-----------
net: slirp: switch to slirp_new
Replace slirp_init with slirp_new, so that a more recent cfg.version
can be specified. The function appeared in version 4.1.0.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: dbac409bffe103a9185989261ccf98907eab8ac1
https://github.com/qemu/qemu/commit/dbac409bffe103a9185989261ccf98907eab8ac1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/slirp.c
Log Message:
-----------
net: slirp: add support for CFI-friendly timer API
libslirp 4.7 introduces a CFI-friendly version of the .timer_new callback.
The new callback replaces the function pointer with an enum; invoking the
callback is done with a new function slirp_handle_timer.
Support the new API so that CFI can be made compatible with using a system
libslirp.
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Reviewed-by: Marc-André Lureau <malureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8ca517a84c1d7ab7f23f4afd9b896070ee89e057
https://github.com/qemu/qemu/commit/8ca517a84c1d7ab7f23f4afd9b896070ee89e057
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
Log Message:
-----------
net: slirp: allow CFI with libslirp >= 4.7
slirp 4.7 introduces a new CFI-friendly timer callback that does
not pass function pointers within libslirp as callbacks for timers.
Check the version number and, if it is new enough, allow using CFI
even with a system libslirp.
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Reviewed-by: Marc-André Lureau <malureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6676eeb4062782cb41bec90f1d38f12ddf569b13
https://github.com/qemu/qemu/commit/6676eeb4062782cb41bec90f1d38f12ddf569b13
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/qemu/coroutine.h
M util/qemu-coroutine-lock.c
Log Message:
-----------
coroutine-lock: qemu_co_queue_next is a coroutine-only qemu_co_enter_next
qemu_co_queue_next is basically the same as qemu_co_enter_next but
without a QemuLockable argument. That's perfectly fine, but only
as long as the function is marked coroutine_fn. If used outside
coroutine context, qemu_co_queue_wait will attempt to take the lock
and that is just broken: if you are calling qemu_co_queue_next outside
coroutine context, the lock is going to be a QemuMutex which cannot be
taken twice by the same thread.
The patch adds the marker and reimplements qemu_co_queue_next in terms of
qemu_co_enter_next_impl, to remove duplicated code and to clarify that the
latter also works in coroutine context.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20220427130830.150180-2-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9a28215e356448184c6a5867f2c61a254faa2d16
https://github.com/qemu/qemu/commit/9a28215e356448184c6a5867f2c61a254faa2d16
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/qemu/coroutine.h
M ui/console.c
M util/qemu-coroutine-lock.c
Log Message:
-----------
coroutine-lock: introduce qemu_co_queue_enter_all
Because qemu_co_queue_restart_all does not release the lock, it should
be used only in coroutine context. Introduce a new function that,
like qemu_co_enter_next, does release the lock, and use it whenever
qemu_co_queue_restart_all was used outside coroutine context.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20220427130830.150180-3-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 15adc2699606b473f11eb3828d532d31be7137cd
https://github.com/qemu/qemu/commit/15adc2699606b473f11eb3828d532d31be7137cd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M block/io.c
M include/qemu/coroutine.h
M util/qemu-coroutine-lock.c
Log Message:
-----------
coroutine-lock: qemu_co_queue_restart_all is a coroutine-only
qemu_co_enter_all
qemu_co_queue_restart_all is basically the same as qemu_co_enter_all
but without a QemuLockable argument. That's perfectly fine, but only as
long as the function is marked coroutine_fn. If used outside coroutine
context, qemu_co_queue_wait will attempt to take the lock and that
is just broken: if you are calling qemu_co_queue_restart_all outside
coroutine context, the lock is going to be a QemuMutex which cannot be
taken twice by the same thread.
The patch adds the marker to qemu_co_queue_restart_all and to its sole
non-coroutine_fn caller; it then reimplements the function in terms of
qemu_co_enter_all_impl, to remove duplicated code and to clarify that the
latter also works in coroutine context.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20220427130830.150180-4-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1256299850b6401f7788924014095add9c4eaf42
https://github.com/qemu/qemu/commit/1256299850b6401f7788924014095add9c4eaf42
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-backend.c
Log Message:
-----------
vhost-backend: do not depend on CONFIG_VHOST_VSOCK
The vsock callbacks .vhost_vsock_set_guest_cid and
.vhost_vsock_set_running are the only ones to be conditional
on #ifdef CONFIG_VHOST_VSOCK. This is different from any other
device-dependent callbacks like .vhost_scsi_set_endpoint, and it
also broke when CONFIG_VHOST_VSOCK was changed to a per-target
symbol.
It would be possible to also use the CONFIG_DEVICES include, but
really there is no reason for most virtio files to be per-target
so just remove the #ifdef to fix the issue.
Reported-by: Dov Murik <dovmurik@linux.ibm.com>
Fixes: 9972ae314f ("build: move vhost-vsock configuration to Kconfig")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d9a4aab2f7699d097795e10d8aacaa0b9cb699cb
https://github.com/qemu/qemu/commit/d9a4aab2f7699d097795e10d8aacaa0b9cb699cb
Author: Kshitij Suri <kshitij.suri@nutanix.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M ui/meson.build
Log Message:
-----------
meson: link libpng independent of vnc
Currently png support is dependent on vnc for linking object file to
libpng. This commit makes the parameter independent of vnc as it breaks
system emulator with --disable-vnc unless --disable-png is added.
Fixes: 9a0a119a38 ("Added parameter to take screenshot with screendump as PNG",
2022-04-27)
Signed-off-by: Kshitij Suri <kshitij.suri@nutanix.com>
Message-Id: <20220510161932.228481-1-kshitij.suri@nutanix.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c6d608b606c94a36fd00e01bc334a8947ee1b628
https://github.com/qemu/qemu/commit/c6d608b606c94a36fd00e01bc334a8947ee1b628
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M softmmu/vl.c
Log Message:
-----------
vl: make machine type deprecation a warning
error_report should generally be followed by a failure; if we can proceed
anyway, that is just a warning and should be communicated properly to
the user with warn_report.
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220511175043.27327-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: acedc6158c7bd1430db620d4dc8f62c638264f49
https://github.com/qemu/qemu/commit/acedc6158c7bd1430db620d4dc8f62c638264f49
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M scripts/kvm/vmxcap
Log Message:
-----------
vmxcap: add tertiary execution controls
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4f18ef4f835350decda7c27d961ff2a9bf5f0ae5
https://github.com/qemu/qemu/commit/4f18ef4f835350decda7c27d961ff2a9bf5f0ae5
Author: Alex Williamson <alex.williamson@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/vfio/common.c
M hw/vfio/migration.c
M include/standard-headers/linux/input-event-codes.h
M include/standard-headers/linux/virtio_config.h
M include/standard-headers/linux/virtio_crypto.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-generic/mman-common.h
M linux-headers/asm-mips/mman.h
M linux-headers/linux/kvm.h
M linux-headers/linux/psci.h
M linux-headers/linux/userfaultfd.h
M linux-headers/linux/vfio.h
M linux-headers/linux/vhost.h
Log Message:
-----------
linux-headers: Update to v5.18-rc6
Update to c5eb0a61238d ("Linux 5.18-rc6"). Mechanical search and
replace of vfio defines with white space massaging.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Commit: e967cf995f0ff62468c5cb3f20b04ceb51fc0f71
https://github.com/qemu/qemu/commit/e967cf995f0ff62468c5cb3f20b04ceb51fc0f71
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/openrisc/openrisc_sim.c
Log Message:
-----------
hw/openrisc: page-align FDT address
The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.
Cc: Stafford Horne <shorne@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Commit: e3cf3cd78695851c1e14c31893f8f95c27a60936
https://github.com/qemu/qemu/commit/e3cf3cd78695851c1e14c31893f8f95c27a60936
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/openrisc/openrisc_sim.c
Log Message:
-----------
hw/openrisc: support 4 serial ports in or1ksim
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Commit: 6d192cb708cb2d9a607a638c7d412aa46b33bef7
https://github.com/qemu/qemu/commit/6d192cb708cb2d9a607a638c7d412aa46b33bef7
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/openrisc/openrisc_sim.c
Log Message:
-----------
hw/openrisc: use right OMPIC size variable
This appears to be a copy and paste error. The UART size was used
instead of the much smaller OMPIC size. But actually that smaller OMPIC
size is wrong too and doesn't allow the IPI to work in Linux. So set it
to the old value.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Commit: ad6cb5413fe65079dd429ce0a4097a672fe56acc
https://github.com/qemu/qemu/commit/ad6cb5413fe65079dd429ce0a4097a672fe56acc
Author: Stafford Horne <shorne@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/openrisc/cpu.c
Log Message:
-----------
target/openrisc: Do not reset delay slot flag on early tb exit
This was found when running linux crypto algorithm selftests used by
wireguard. We found that randomly the tests would fail. We found
through investigation that a combination of a tick timer interrupt,
raised when executing a delay slot instruction at a page boundary caused
the issue.
This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec.
On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was
being used as a fallback. The OpenRISC set_pc implementation clears
dflag, which caused the exception handling logic to not account for the
delay slot. This was the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.
Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Commit: 58d5381a3d65e4b903d9454adb489f17c5a398da
https://github.com/qemu/qemu/commit/58d5381a3d65e4b903d9454adb489f17c5a398da
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/crypto.json
M qapi/machine.json
M qapi/misc.json
M qga/qapi-schema.json
Log Message:
-----------
qapi: Fix malformed "Since:" section tags
"Since X.Y" is not recognized as a tagged section, and therefore not
formatted as such in generated documentation. Fix by adding the
required colon.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220422132807.1704411-1-armbru@redhat.com>
Reviewed-by: Andrea Bolognani <abologna@redhat.com>
Commit: 17ae78483b9a8e1c7485f5e50a9fb63a9b25e372
https://github.com/qemu/qemu/commit/17ae78483b9a8e1c7485f5e50a9fb63a9b25e372
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/run-state.json
Log Message:
-----------
qapi: Drop stray trailing symbol
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220503073737.84223-2-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: fac8b8a5e23cf4b6651f4f6c8131cfd645855ffe
https://github.com/qemu/qemu/commit/fac8b8a5e23cf4b6651f4f6c8131cfd645855ffe
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/ui.json
Log Message:
-----------
qapi: Fix comment indentation
It should start on the very first column.
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220503073737.84223-3-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 16a714c1751e5a91de5083f70203888e19506690
https://github.com/qemu/qemu/commit/16a714c1751e5a91de5083f70203888e19506690
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/block-core.json
M qapi/block.json
M qapi/crypto.json
M qapi/machine.json
M qapi/migration.json
Log Message:
-----------
qapi: Add missing separators between sections
This only affects readability. The generated documentation
doesn't change.
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220503073737.84223-4-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: a9a6de1092979c825068f88c740156c9bb1fcffe
https://github.com/qemu/qemu/commit/a9a6de1092979c825068f88c740156c9bb1fcffe
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/block-core.json
M qapi/block.json
M qapi/char.json
M qapi/common.json
M qapi/control.json
M qapi/machine.json
M qapi/migration.json
M qapi/misc-target.json
M qapi/replay.json
M qapi/run-state.json
M qapi/ui.json
Log Message:
-----------
qapi: Drop unnecessary empty lines in comments
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220503073737.84223-5-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 28f96dc7b2ddcd547bf9d77601f556df11a75fe7
https://github.com/qemu/qemu/commit/28f96dc7b2ddcd547bf9d77601f556df11a75fe7
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/audio.json
M qapi/block-core.json
M qapi/block.json
M qapi/char.json
M qapi/control.json
M qapi/crypto.json
M qapi/job.json
M qapi/machine-target.json
M qapi/machine.json
M qapi/misc-target.json
M qapi/run-state.json
M qapi/ui.json
Log Message:
-----------
qapi: Drop unnecessary empty lines outside of comments
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220503073737.84223-6-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 61b6cfe4b90f57ae799987e99a4b0b1a08937356
https://github.com/qemu/qemu/commit/61b6cfe4b90f57ae799987e99a4b0b1a08937356
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/block-core.json
M qapi/block-export.json
M qapi/block.json
M qapi/char.json
M qapi/dump.json
M qapi/machine.json
M qapi/misc-target.json
M qapi/misc.json
M qapi/run-state.json
M qapi/sockets.json
M qapi/ui.json
Log Message:
-----------
qapi: Drop unnecessary whitespace in comments
The only instances that get changed are those in which the
additional whitespace was not (or couldn't possibly be) used for
alignment purposes.
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Message-Id: <20220503073737.84223-7-abologna@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 3fbbffbe8ba6bb2840e6585607c590d7b25bb7fa
https://github.com/qemu/qemu/commit/3fbbffbe8ba6bb2840e6585607c590d7b25bb7fa
Author: Andrea Bolognani <abologna@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/block-core.json
M qapi/block.json
M qapi/char.json
M qapi/control.json
M qapi/crypto.json
M qapi/migration.json
M qapi/sockets.json
M qapi/ui.json
Log Message:
-----------
qapi: Stop using whitespace for alignment in comments
Perfectly aligned things look pretty, but keeping them that
way as the schema evolves requires churn, and in some cases
newly-added lines are not aligned properly.
Overall, trying to align things is just not worth the trouble.
Signed-off-by: Andrea Bolognani <abologna@redhat.com>
Message-Id: <20220503073737.84223-8-abologna@redhat.com>
Message-Id: <20220503073737.84223-9-abologna@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Two patches squashed together]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 1d3fa3a3c0087dec4783e8548e6bd5020a80cbbf
https://github.com/qemu/qemu/commit/1d3fa3a3c0087dec4783e8548e6bd5020a80cbbf
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M scripts/qapi/expr.py
Log Message:
-----------
qapi/expr: Enforce feature naming rules again
Commit e42648dccd "qapi/expr.py: Remove single-letter variable"
accidentally removed the check for "only lower case letters and
hyphens". Restore it.
Fixes: e42648dccdd1defe8f35f247966cd7283f865cd6
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220510061645.3209195-2-armbru@redhat.com>
Commit: 47b594b7a08beccf2b3a8be06be6afc9c015dd4f
https://github.com/qemu/qemu/commit/47b594b7a08beccf2b3a8be06be6afc9c015dd4f
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/devel/qapi-code-gen.rst
Log Message:
-----------
docs/devel/qapi-code-gen: Belatedly document feature naming rules
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220510061645.3209195-3-armbru@redhat.com>
Commit: ac5e361ec9571f82319e3f61d35d8191e68a6a75
https://github.com/qemu/qemu/commit/ac5e361ec9571f82319e3f61d35d8191e68a6a75
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/pragma.json
Log Message:
-----------
qapi/pragma: Tidy up comments
Commit 05ebf841ef "qapi: Enforce command naming rules" inserted new
code between a comment and the code it applies to. Move the comment
back to its code, and add one for the new code.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220510081433.3289762-1-armbru@redhat.com>
Commit: c82f981a675a0e388a0417a7d282ce23b9592a2b
https://github.com/qemu/qemu/commit/c82f981a675a0e388a0417a7d282ce23b9592a2b
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/unit/crypto-tls-x509-helpers.c
M tests/unit/test-crypto-tlssession.c
Log Message:
-----------
tests: fix encoding of IP addresses in x509 certs
We need to encode just the address bytes, not the whole struct sockaddr
data. Add a test case to validate that we're matching on SAN IP
addresses correctly.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-2-berrange@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 1644adb53a1e768e97ad013d8f0f1fa5cc35794f
https://github.com/qemu/qemu/commit/1644adb53a1e768e97ad013d8f0f1fa5cc35794f
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/unit/crypto-tls-x509-helpers.h
Log Message:
-----------
tests: add more helper macros for creating TLS x509 certs
These macros are more suited to the general consumers of certs in the
test suite, where we don't need to exercise every single possible
permutation.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-3-berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 372b96990908bbbebc5ab6817942d4b05ee9fc97
https://github.com/qemu/qemu/commit/372b96990908bbbebc5ab6817942d4b05ee9fc97
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/meson.build
M tests/qtest/migration-test.c
M tests/unit/crypto-tls-psk-helpers.c
M tests/unit/crypto-tls-psk-helpers.h
Log Message:
-----------
tests: add migration tests of TLS with PSK credentials
This validates that we correctly handle migration success and failure
scenarios when using TLS with pre shared keys.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-4-berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: b9f2c6c4fad7fe52929439a09de41a7daea534c5
https://github.com/qemu/qemu/commit/b9f2c6c4fad7fe52929439a09de41a7daea534c5
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
M tests/qtest/meson.build
M tests/qtest/migration-test.c
Log Message:
-----------
tests: add migration tests of TLS with x509 credentials
This validates that we correctly handle migration success and failure
scenarios when using TLS with x509 certificates. There are quite a few
different scenarios that matter in relation to hostname validation.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-5-berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
dgilbert: Manual merge due to ifdef change in 3
Commit: 8431f0b5d28b5971b063132103e1c3a2b786815d
https://github.com/qemu/qemu/commit/8431f0b5d28b5971b063132103e1c3a2b786815d
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests: convert XBZRLE migration test to use common helper
Most of the XBZRLE migration test logic is common with the rest of the
precopy tests, so it can use the helper with just one small tweak.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-6-berrange@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: ae7a950c71463e8fb50cc9ff7c23ee55c65136eb
https://github.com/qemu/qemu/commit/ae7a950c71463e8fb50cc9ff7c23ee55c65136eb
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests: convert multifd migration tests to use common helper
Most of the multifd migration test logic is common with the rest of the
precopy tests, so it can use the helper without difficulty. The only
exception of the multifd cancellation test which tries to run multiple
migrations in a row.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-7-berrange@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 290fb6d2a466da0247837d4af91f700f4706bcce
https://github.com/qemu/qemu/commit/290fb6d2a466da0247837d4af91f700f4706bcce
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests: add multifd migration tests of TLS with PSK credentials
This validates that we correctly handle multifd migration success
and failure scenarios when using TLS with pre shared keys.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-8-berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: b5cdd48fa237e73cac4e5060a5402f6fa49405c7
https://github.com/qemu/qemu/commit/b5cdd48fa237e73cac4e5060a5402f6fa49405c7
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests: add multifd migration tests of TLS with x509 credentials
This validates that we correctly handle multifd migration success
and failure scenarios when using TLS with x509 certificates. There
are quite a few different scenarios that matter in relation to
hostname validation, but we skip a couple as we can assume that
the non-multifd coverage applies to some extent.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-9-berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: bc7ed4e384f32004da57cd6387c2683d00ad326f
https://github.com/qemu/qemu/commit/bc7ed4e384f32004da57cd6387c2683d00ad326f
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/migration-helpers.c
M tests/qtest/migration-helpers.h
M tests/qtest/migration-test.c
Log Message:
-----------
tests: ensure migration status isn't reported as failed
Various methods in the migration test call 'query_migrate' to fetch the
current status and then access a particular field. Almost all of these
cases expect the migration to be in a non-failed state. In the case of
'wait_for_migration_pass' in particular, if the status is 'failed' then
it will get into an infinite loop. By validating that the status is
not 'failed' the test suite will assert rather than hang when getting
into an unexpected state.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220426160048.812266-10-berrange@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: ca3f76f66517eada9befc85feeaa48dcb7793e07
https://github.com/qemu/qemu/commit/ca3f76f66517eada9befc85feeaa48dcb7793e07
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson.build: Fix docker-test-build@alpine when including linux/errqueue.h
A build error happens in alpine CI when linux/errqueue.h is included
in io/channel-socket.c, due to redefining of 'struct __kernel_timespec':
===
ninja: job failed: [...]
In file included from /usr/include/linux/errqueue.h:6,
from ../io/channel-socket.c:29:
/usr/include/linux/time_types.h:7:8: error: redefinition of 'struct
__kernel_timespec'
7 | struct __kernel_timespec {
| ^~~~~~~~~~~~~~~~~
In file included from /usr/include/liburing.h:19,
from /builds/user/qemu/include/block/aio.h:18,
from /builds/user/qemu/include/io/channel.h:26,
from /builds/user/qemu/include/io/channel-socket.h:24,
from ../io/channel-socket.c:24:
/usr/include/liburing/compat.h:9:8: note: originally defined here
9 | struct __kernel_timespec {
| ^~~~~~~~~~~~~~~~~
ninja: subcommand failed
===
As above error message suggests, 'struct __kernel_timespec' was already
defined by liburing/compat.h.
Fix alpine CI by adding test to disable liburing in configure step if a
redefinition happens between linux/errqueue.h and liburing/compat.h.
[dgilbert: This has been fixed in Alpine issue 13813 and liburing]
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Message-Id: <20220513062836.965425-2-leobras@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: ef694312c84e3329e9f9d2baa03d9383d031f82f
https://github.com/qemu/qemu/commit/ef694312c84e3329e9f9d2baa03d9383d031f82f
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M chardev/char-io.c
M hw/remote/mpqemu-link.c
M include/io/channel.h
M io/channel-buffer.c
M io/channel-command.c
M io/channel-file.c
M io/channel-socket.c
M io/channel-tls.c
M io/channel-websock.c
M io/channel.c
M migration/rdma.c
M scsi/pr-manager-helper.c
M tests/unit/test-io-channel-socket.c
Log Message:
-----------
QIOChannel: Add flags on io_writev and introduce io_flush callback
Add flags to io_writev and introduce io_flush as optional callback to
QIOChannelClass, allowing the implementation of zero copy writes by
subclasses.
How to use them:
- Write data using qio_channel_writev*(...,QIO_CHANNEL_WRITE_FLAG_ZERO_COPY),
- Wait write completion with qio_channel_flush().
Notes:
As some zero copy write implementations work asynchronously, it's
recommended to keep the write buffer untouched until the return of
qio_channel_flush(), to avoid the risk of sending an updated buffer
instead of the buffer state during write.
As io_flush callback is optional, if a subclass does not implement it, then:
- io_flush will return 0 without changing anything.
Also, some functions like qio_channel_writev_full_all() were adapted to
receive a flag parameter. That allows shared code between zero copy and
non-zero copy writev, and also an easier implementation on new flags.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20220513062836.965425-3-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 5edfe3aab0642a7707c25e84a48905eefc359174
https://github.com/qemu/qemu/commit/5edfe3aab0642a7707c25e84a48905eefc359174
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/io/channel-socket.h
M io/channel-socket.c
Log Message:
-----------
QIOChannelSocket: Implement io_writev zero copy flag & io_flush for
CONFIG_LINUX
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_socket_flush() was implemented by counting how many times
sendmsg(...,MSG_ZEROCOPY) was successfully called, and then reading the
socket's error queue, in order to find how many of them finished sending.
Flush will loop until those counters are the same, or until some error occurs.
Notes on using writev() with QIO_CHANNEL_WRITE_FLAG_ZERO_COPY:
1: Buffer
- As MSG_ZEROCOPY tells the kernel to use the same user buffer to avoid copying,
some caution is necessary to avoid overwriting any buffer before it's sent.
If something like this happen, a newer version of the buffer may be sent
instead.
- If this is a problem, it's recommended to call qio_channel_flush() before
freeing
or re-using the buffer.
2: Locked memory
- When using MSG_ZERCOCOPY, the buffer memory will be locked after queued, and
unlocked after it's sent.
- Depending on the size of each buffer, and how often it's sent, it may require
a larger amount of locked memory than usually available to non-root user.
- If the required amount of locked memory is not available, writev_zero_copy
will return an error, which can abort an operation like migration,
- Because of this, when an user code wants to add zero copy as a feature, it
requires a mechanism to disable it, so it can still be accessible to less
privileged users.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20220513062836.965425-4-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 678f91985fd252afbe5f9ce59ad4de496d152bab
https://github.com/qemu/qemu/commit/678f91985fd252afbe5f9ce59ad4de496d152bab
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M migration/migration.c
M migration/migration.h
M migration/socket.c
M monitor/hmp-cmds.c
M qapi/migration.json
Log Message:
-----------
migration: Add zero-copy-send parameter for QMP/HMP for Linux
Add property that allows zero-copy migration of memory pages
on the sending side, and also includes a helper function
migrate_use_zero_copy_send() to check if it's enabled.
No code is introduced to actually do the migration, but it allow
future implementations to enable/disable this feature.
On non-Linux builds this parameter is compiled-out.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220513062836.965425-5-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: f3212e0552a9c988f21072511c169c2f05f30752
https://github.com/qemu/qemu/commit/f3212e0552a9c988f21072511c169c2f05f30752
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M migration/channel.c
M migration/migration.c
M migration/migration.h
M migration/multifd.c
Log Message:
-----------
migration: Add migrate_use_tls() helper
A lot of places check parameters.tls_creds in order to evaluate if TLS is
in use, and sometimes call migrate_get_current() just for that test.
Add new helper function migrate_use_tls() in order to simplify testing
for TLS usage.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220513062836.965425-6-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 8bd4b46133e519eccbfdb9f0368fa2dbf287650a
https://github.com/qemu/qemu/commit/8bd4b46133e519eccbfdb9f0368fa2dbf287650a
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M migration/multifd.c
M migration/multifd.h
M migration/ram.c
Log Message:
-----------
multifd: multifd_send_sync_main now returns negative on error
Even though multifd_send_sync_main() currently emits error_reports, it's
callers don't really check it before continuing.
Change multifd_send_sync_main() to return -1 on error and 0 on success.
Also change all it's callers to make use of this change and possibly fail
earlier.
(This change is important to next patch on multifd zero copy
implementation, to make it sure an error in zero-copy flush does not go
unnoticed.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-Id: <20220513062836.965425-7-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: e75cbd134a4ae5c2c3aea31fe949748363504319
https://github.com/qemu/qemu/commit/e75cbd134a4ae5c2c3aea31fe949748363504319
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M migration/multifd.c
Log Message:
-----------
multifd: Send header packet without flags if zero-copy-send is enabled
Since d48c3a0445 ("multifd: Use a single writev on the send side"),
sending the header packet and the memory pages happens in the same
writev, which can potentially make the migration faster.
Using channel-socket as example, this works well with the default copying
mechanism of sendmsg(), but with zero-copy-send=true, it will cause
the migration to often break.
This happens because the header packet buffer gets reused quite often,
and there is a high chance that by the time the MSG_ZEROCOPY mechanism get
to send the buffer, it has already changed, sending the wrong data and
causing the migration to abort.
It means that, as it is, the buffer for the header packet is not suitable
for sending with MSG_ZEROCOPY.
In order to enable zero copy for multifd, send the header packet on an
individual write(), without any flags, and the remanining pages with a
writev(), as it was happening before. This only changes how a migration
with zero-copy-send=true works, not changing any current behavior for
migrations with zero-copy-send=false.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220513062836.965425-8-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 0b5e4860a384a7d5373f27a014413e924458f07e
https://github.com/qemu/qemu/commit/0b5e4860a384a7d5373f27a014413e924458f07e
Author: Leonardo Bras <leobras@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M migration/migration.c
M migration/multifd.c
M migration/multifd.h
M migration/socket.c
Log Message:
-----------
multifd: Implement zero copy write in multifd migration (multifd-zero-copy)
Implement zero copy send on nocomp_send_write(), by making use of QIOChannel
writev + flags & flush interface.
Change multifd_send_sync_main() so flush_zero_copy() can be called
after each iteration in order to make sure all dirty pages are sent before
a new iteration is started. It will also flush at the beginning and at the
end of migration.
Also make it return -1 if flush_zero_copy() fails, in order to cancel
the migration process, and avoid resuming the guest in the target host
without receiving all current RAM.
This will work fine on RAM migration because the RAM pages are not usually
freed,
and there is no problem on changing the pages content between
writev_zero_copy() and
the actual sending of the buffer, because this change will dirty the page and
cause it to be re-sent on a next iteration anyway.
A lot of locked memory may be needed in order to use multifd migration
with zero-copy enabled, so disabling the feature should be necessary for
low-privileged users trying to perform multifd migrations.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220513062836.965425-9-leobras@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Commit: 9de983df782de65eb1dcd87d15fa88ab96d254b1
https://github.com/qemu/qemu/commit/9de983df782de65eb1dcd87d15fa88ab96d254b1
Author: Ivan Shcherbakov <ivan@sysprogs.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/whpx/whpx-all.c
Log Message:
-----------
WHPX: fixed TPR/CR8 translation issues affecting VM debugging
This patch fixes the following error that would occur when trying to resume
a WHPX-accelerated VM from a breakpoint:
qemu: WHPX: Failed to set interrupt state registers, hr=c0350005
The error arises from an incorrect CR8 value being passed to
WHvSetVirtualProcessorRegisters() that doesn't match the
value set via WHvSetVirtualProcessorInterruptControllerState2().
Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0d3aa615d180f3bc1a719b97cebf6e76a9936fea
https://github.com/qemu/qemu/commit/0d3aa615d180f3bc1a719b97cebf6e76a9936fea
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/vss-win32/meson.build
Log Message:
-----------
qga-vss: Add auto generated headers to dependencies
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220512154906.331399-1-kkostiuk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7804807eb54e79b2e2926a69820218367130c229
https://github.com/qemu/qemu/commit/7804807eb54e79b2e2926a69820218367130c229
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/vss-win32/requester.cpp
Log Message:
-----------
qga-vss: Use the proper operator to free memory
volume_name_wchar is allocated by 'void* operator new [](long long unsigned int)
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220512154909.331481-1-kkostiuk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 27b6bc641d001b2042bf9716e06c89ae1697c668
https://github.com/qemu/qemu/commit/27b6bc641d001b2042bf9716e06c89ae1697c668
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: Remove the deprecated cpu model 'Icelake-Client'
Icelake, is the codename for Intel 3rd generation Xeon Scalable server
processors. There isn't ever client variants. This "Icelake-Client" CPU
model was added wrongly and imaginarily.
It has been deprecated since v5.2, now it's time to remove it completely
from code.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1647247859-4947-1-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9e299477613edb3d61b85b43dfe51aa4a7a106af
https://github.com/qemu/qemu/commit/9e299477613edb3d61b85b43dfe51aa4a7a106af
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/qdev-properties.c
M include/hw/qdev-properties.h
Log Message:
-----------
qdev-properties: Add a new macro with bitmask check for uint64_t property
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-2-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 10bd3d57c92e57024e52c760ea0f5c342f7662bf
https://github.com/qemu/qemu/commit/10bd3d57c92e57024e52c760ea0f5c342f7662bf
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add lbr-fmt vPMU option to support guest LBR
The Last Branch Recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors which records a running trace of the most
recent branches taken by the processor in the LBR stack. This option
indicates the LBR format to enable for guest perf.
The LBR feature is enabled if below conditions are met:
1) KVM is enabled and the PMU is enabled.
2) msr-based-feature IA32_PERF_CAPABILITIES is supporterd on KVM.
3) Supported returned value for lbr_fmt from above msr is non-zero.
4) Guest vcpu model does support FEAT_1_ECX.CPUID_EXT_PDCM.
5) User-provided lbr-fmt value doesn't violate its bitmask (0x3f).
6) Target guest LBR format matches that of host.
Co-developed-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-3-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c332ed53e741e1585c604988ab1c5f06ddbf2765
https://github.com/qemu/qemu/commit/c332ed53e741e1585c604988ab1c5f06ddbf2765
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Add kvm_get_one_msr helper
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-4-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 74731cac3f908fc3c360fd3a41ce4df79311ee9f
https://github.com/qemu/qemu/commit/74731cac3f908fc3c360fd3a41ce4df79311ee9f
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Enable support for XSAVES based features
There're some new features, including Arch LBR, depending
on XSAVES/XRSTORS support, the new instructions will
save/restore data based on feature bits enabled in XCR0 | XSS.
This patch adds the basic support for related CPUID enumeration
and meanwhile changes the name from FEAT_XSAVE_COMP_{LO|HI} to
FEAT_XSAVE_XCR0_{LO|HI} to differentiate clearly the feature
bits in XCR0 and those in XSS.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-5-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 164e257cdd83cedb8fcace1de22ec5473e394124
https://github.com/qemu/qemu/commit/164e257cdd83cedb8fcace1de22ec5473e394124
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add XSAVES support for Arch LBR
Define Arch LBR bit in XSS and save/restore structure
for XSAVE area size calculation.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-6-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 838a86a84984e702b3ed4140b58dc60fc1c5d44e
https://github.com/qemu/qemu/commit/838a86a84984e702b3ed4140b58dc60fc1c5d44e
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Add MSR access interface for Arch LBR
In the first generation of Arch LBR, the max support
Arch LBR depth is 32, both host and guest use the value
to set depth MSR. This can simplify the implementation
of patch given the side-effect of mismatch of host/guest
depth MSR: XRSTORS will reset all recording MSRs to 0s
if the saved depth mismatches MSR_ARCH_LBR_DEPTH.
In most of the cases Arch LBR is not in active status,
so check the control bit before save/restore the big
chunck of Arch LBR MSRs.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-7-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 41c5d37ab830a874daba5519e33c80e4cb0dfe08
https://github.com/qemu/qemu/commit/41c5d37ab830a874daba5519e33c80e4cb0dfe08
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/machine.c
Log Message:
-----------
target/i386: Enable Arch LBR migration states in vmstate
The Arch LBR record MSRs and control MSRs will be migrated
to destination guest if the vcpus were running with Arch
LBR active.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-8-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6f5c562322a07750ac802805a3eb83190b379ac7
https://github.com/qemu/qemu/commit/6f5c562322a07750ac802805a3eb83190b379ac7
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: introduce helper to access supported CPUID
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6a2e0352c3c66695feaf03786025d5648c17427b
https://github.com/qemu/qemu/commit/6a2e0352c3c66695feaf03786025d5648c17427b
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Support Arch LBR in CPUID enumeration
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6b5c97e933f9a322dd052bc69e449169bd06e094
https://github.com/qemu/qemu/commit/6b5c97e933f9a322dd052bc69e449169bd06e094
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M crypto/secret_common.c
M crypto/tlscredsanon.c
M crypto/tlscredspsk.c
M crypto/tlscredsx509.c
M docs/about/deprecated.rst
M docs/about/removed-features.rst
Log Message:
-----------
crypto: make loaded property read-only
The ``loaded=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``loaded`` was the last option) or caused options to be
effectively ignored as if they were not given. The property is therefore
useless and was deprecated in 6.0; make it read-only now.
The patch is best reviewed with "-b".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8fec565f9ab5022688b3823b9d067b12aede7eb9
https://github.com/qemu/qemu/commit/8fec565f9ab5022688b3823b9d067b12aede7eb9
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M backends/rng.c
M docs/about/deprecated.rst
M docs/about/removed-features.rst
Log Message:
-----------
rng: make opened property read-only
The ``opened=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``opened`` was the last option) or caused errors. The property
is therefore useless and was deprecated in 6.0; make it read-only now.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ea6dfa10f6cc8199b4a7c8f3edc66a9b0ef3074d
https://github.com/qemu/qemu/commit/ea6dfa10f6cc8199b4a7c8f3edc66a9b0ef3074d
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/soundhw.c
Log Message:
-----------
soundhw: remove ability to create multiple soundcards
The usefulness of enabling a dozen soundcards is dubious. Simplify the
code by allowing a single instance of -soundhw, with no support for
parsing either comma-separated values or 'soundhw all'.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0420b0f04084c4d4be70069836905d61fa87492b
https://github.com/qemu/qemu/commit/0420b0f04084c4d4be70069836905d61fa87492b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/soundhw.c
M include/hw/audio/soundhw.h
Log Message:
-----------
soundhw: extract soundhw help to a separate function
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c69657d0a92543c8508c7c62efd886e7693a796e
https://github.com/qemu/qemu/commit/c69657d0a92543c8508c7c62efd886e7693a796e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/soundhw.c
Log Message:
-----------
soundhw: unify initialization for ISA and PCI soundhw
Use qdev_new instead of distinguishing isa_create_simple/pci_create_simple.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 631a687699acdd8b0a97668440125ba68113e130
https://github.com/qemu/qemu/commit/631a687699acdd8b0a97668440125ba68113e130
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/soundhw.c
M softmmu/vl.c
Log Message:
-----------
soundhw: move help handling to vl.c
This will allow processing "-audio model=help" even if the backend
part of the option is missing.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4296e0a4b2c539ac11c243f49a87b75299e9ad17
https://github.com/qemu/qemu/commit/4296e0a4b2c539ac11c243f49a87b75299e9ad17
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M audio/audio.c
M audio/audio.h
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/audio/intel-hda.c
M hw/audio/soundhw.c
M include/hw/audio/soundhw.h
M qemu-options.hx
M softmmu/vl.c
Log Message:
-----------
introduce -audio as a replacement for -soundhw
-audio is used like "-audio pa,model=sb16". It is almost as simple as
-soundhw, but it reuses the -audiodev parsing machinery and attaches an
audiodev to the newly-created device. The main 'feature' is that
it knows about adding the codec device for model=intel-hda, and adding
the audiodev to the codec device.
In the future, it could be extended to support default models or
builtin devices, just like -nic, or even a default backend. For now,
keep it simple.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3584e7532b287e26542a1613cdd1391096d1ad04
https://github.com/qemu/qemu/commit/3584e7532b287e26542a1613cdd1391096d1ad04
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M Makefile
Log Message:
-----------
build: remove useless dependency
qemu-plugins.symbols is now processed in Meson.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a125bde23b53a42436d61197e5c05db841a8c9e4
https://github.com/qemu/qemu/commit/a125bde23b53a42436d61197e5c05db841a8c9e4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: remove another dead variable
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e71b80fa5bcc0b153c52db77cedc2ffc37ee426b
https://github.com/qemu/qemu/commit/e71b80fa5bcc0b153c52db77cedc2ffc37ee426b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: remove duplicate help messages
These messages are already emitted by scripts/meson-parse-buildoptions.sh.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bbe1b36ad2e403b74c5ac503dd97ca77febe8539
https://github.com/qemu/qemu/commit/bbe1b36ad2e403b74c5ac503dd97ca77febe8539
Author: Halil Pasic <pasic@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/virtio-bus.c
Log Message:
-----------
virtio: fix feature negotiation for ACCESS_PLATFORM
Unlike most virtio features ACCESS_PLATFORM is considered mandatory by
QEMU, i.e. the driver must accept it if offered by the device. The
virtio specification says that the driver SHOULD accept the
ACCESS_PLATFORM feature if offered, and that the device MAY fail to
operate if ACCESS_PLATFORM was offered but not negotiated.
While a SHOULD ain't exactly a MUST, we are certainly allowed to fail
the device when the driver fences ACCESS_PLATFORM. With commit
2943b53f68 ("virtio: force VIRTIO_F_IOMMU_PLATFORM") we already made the
decision to do so whenever the get_dma_as() callback is implemented (by
the bus), which in practice means for the entirety of virtio-pci.
That means, if the device needs to translate I/O addresses, then
ACCESS_PLATFORM is mandatory. The aforementioned commit tells us in the
commit message that this is for security reasons. More precisely if we
were to allow a less then trusted driver (e.g. an user-space driver, or
a nested guest) to make the device bypass the IOMMU by not negotiating
ACCESS_PLATFORM, then the guest kernel would have no ability to
control/police (by programming the IOMMU) what pieces of guest memory
the driver may manipulate using the device. Which would break security
assumptions within the guest.
If ACCESS_PLATFORM is offered not because we want the device to utilize
an IOMMU and do address translation, but because the device does not
have access to the entire guest RAM, and needs the driver to grant
access to the bits it needs access to (e.g. confidential guest support),
we still require the guest to have the corresponding logic and to accept
ACCESS_PLATFORM. If the driver does not accept ACCESS_PLATFORM, then
things are bound to go wrong, and we may see failures much less graceful
than failing the device because the driver didn't negotiate
ACCESS_PLATFORM.
So let us make ACCESS_PLATFORM mandatory for the driver regardless
of whether the get_dma_as() callback is implemented or not.
Signed-off-by: Halil Pasic <pasic@linux.ibm.com>
Fixes: 2943b53f68 ("virtio: force VIRTIO_F_IOMMU_PLATFORM")
Message-Id: <20220307112939.2780117-1-pasic@linux.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Commit: 7087e6bc621e1f2bc7e2e2434dfd1042a16487bf
https://github.com/qemu/qemu/commit/7087e6bc621e1f2bc7e2e2434dfd1042a16487bf
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: correct the value used for error_setg_errno()
error_setg_errno() expects a normal errno value, not a negated
one, so we should use ENOTSUP instead of -ENOSUP.
Fixes: Coverity CID 1487174
Fixes: ("intel_iommu: support snoop control")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220401022824.9337-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: cc8bf170bf1c28af7e6dc31095cf9884c6aa9228
https://github.com/qemu/qemu/commit/cc8bf170bf1c28af7e6dc31095cf9884c6aa9228
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci/cxl: Add a CXL component type (interface)
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of as a PCIe device with
extra functionality when enumerated and enabled. For this reason, CXL
does here, and will continue to add on to existing PCI code paths.
Host bridges will typically need to be handled specially and so they can
implement this newly introduced interface or not. All other components
should implement this interface. Implementing this interface allows the
core PCI code to treat these devices as special where appropriate.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4ca6953587efd73a5f92b53ca299a0d95b58589e
https://github.com/qemu/qemu/commit/4ca6953587efd73a5f92b53ca299a0d95b58589e
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/Kconfig
A hw/cxl/Kconfig
A hw/cxl/cxl-component-utils.c
A hw/cxl/meson.build
M hw/meson.build
A include/hw/cxl/cxl.h
A include/hw/cxl/cxl_component.h
A include/hw/cxl/cxl_pci.h
Log Message:
-----------
hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extended PCIe header space. CXL components will minimally implement some
subset of CXL.mem and CXL.cache registers defined in 8.2.5 of the CXL
2.0 specification. Two headers and a utility library are introduced to
support the minimum functionality needed to enumerate components.
The cxl_pci header manages bits associated with PCI, specifically the
DVSEC and related fields. The cxl_component.h variant has data
structures and APIs that are useful for drivers implementing any of the
CXL 2.0 components. The library takes care of making use of the DVSEC
bits and the CXL.[mem|cache] registers. Per spec, the registers are
little endian.
None of the mechanisms required to enumerate a CXL capable hostbridge
are introduced at this point.
Note that the CXL.mem and CXL.cache registers used are always 4B wide.
It's possible in the future that this constraint will not hold.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a1610c1bd60b7a5aff3c2c6272a9b6096c4f91a9
https://github.com/qemu/qemu/commit/a1610c1bd60b7a5aff3c2c6272a9b6096c4f91a9
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add entry for Compute Express Link Emulation
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-4-Jonathan.Cameron@huawei.com>
Commit: 66ce1522b0833f3d15b28cc6125237ebb188864e
https://github.com/qemu/qemu/commit/66ce1522b0833f3d15b28cc6125237ebb188864e
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/hw/cxl/cxl.h
A include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Introduce a CXL device (8.2.8)
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically catered towards the eventual
implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0
specification.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7ea8a1eb656aa6b4d28414a7acce0c3a0666ba17
https://github.com/qemu/qemu/commit/7ea8a1eb656aa6b4d28414a7acce0c3a0666ba17
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A hw/cxl/cxl-device-utils.c
M hw/cxl/meson.build
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement the CAP array (8.2.8.1-2)
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignment are managed by softmmu memory core.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 78a2981e7d74a646b4706ce6f2b53b6d5d364ead
https://github.com/qemu/qemu/commit/78a2981e7d74a646b4706ce6f2b53b6d5d364ead
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-device-utils.c
A hw/cxl/cxl-mailbox-utils.c
M hw/cxl/meson.build
M include/hw/cxl/cxl.h
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement basic mailbox (8.2.8.4)
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit communication
between the host OS and the firmware running on the device. For our
purposes, we emulate both the firmware, implemented primarily in
cxl-mailbox-utils.c, and the hardware.
No commands are implemented yet.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3f53c3fab7c71e41aa31ecacb3892a0f8382fea7
https://github.com/qemu/qemu/commit/3f53c3fab7c71e41aa31ecacb3892a0f8382fea7
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-device-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Add memory device utilities
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulated may want to handle commands
differently, and therefore would need a mechanism to opt in/out of the
specific generic handlers. As such, this is considered sufficient for
now, but may need more depth in the future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c520f36440dd0eafc155d5a21893620809479932
https://github.com/qemu/qemu/commit/c520f36440dd0eafc155d5a21893620809479932
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cf1095cbd7e3fecb58f54e4f532f302b9580183d
https://github.com/qemu/qemu/commit/cf1095cbd7e3fecb58f54e4f532f302b9580183d
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Timestamp implementation (8.2.9.3)
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cb90c7af8258fd24206fdb12977792500e30019e
https://github.com/qemu/qemu/commit/cb90c7af8258fd24206fdb12977792500e30019e
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add log commands (8.2.9.4) + CEL
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
commands are supported. It is useful both to determine which spec'd
optional commands are supported, as well as provide a list of vendor
specified commands that might be used. The CEL is already created as
part of mailbox initialization, but here it is now exported to hosts
that use these log commands.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-11-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 71978130cfbb86ad8b7d2fe2b42fa19ecdf3eb13
https://github.com/qemu/qemu/commit/71978130cfbb86ad8b7d2fe2b42fa19ecdf3eb13
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
Log Message:
-----------
hw/pxb: Use a type for realizing expanders
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-12-Jonathan.Cameron@huawei.com>
Commit: a0d02773d9c905f358904186c11af6db487e573e
https://github.com/qemu/qemu/commit/a0d02773d9c905f358904186c11af6db487e573e
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/pci/pci_bus.h
Log Message:
-----------
hw/pci/cxl: Create a CXL bus type
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 035af8e26a749dc190594c08e1ccfbbc5ded94d9
https://github.com/qemu/qemu/commit/035af8e26a749dc190594c08e1ccfbbc5ded94d9
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M hw/i386/pc.c
M include/hw/boards.h
M include/hw/cxl/cxl.h
Log Message:
-----------
cxl: Machine level control on whether CXL support is enabled
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-14-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4dc21a2b9df3578966cb662e2608164e74a6c017
https://github.com/qemu/qemu/commit/4dc21a2b9df3578966cb662e2608164e74a6c017
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci/pci.c
M include/hw/pci/pci.h
M scripts/device-crash-test
Log Message:
-----------
hw/pxb: Allow creation of a CXL PXB (host bridge)
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an operating system that is unaware of CXL should still be able
to enumerate this topology as if it were PCIe.
One can create multiple CXL PXB host bridges, but a host bridge can only
be connected to the main root bus. Host bridges cannot appear elsewhere
in the topology.
Note that as of this patch, the ACPI tables needed for the host bridge
(specifically, an ACPI object in _SB named ACPI0016 and the CEDT) aren't
created. So while this patch internally creates it, it cannot be
properly used by an operating system or other system software.
Also necessary is to add an exception to scripts/device-crash-test
similar to that for exiting pxb as both must created on a PCIexpress
host bus.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan.Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-15-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: df4ce697ba1473da399a6985baf8581a055e2580
https://github.com/qemu/qemu/commit/df4ce697ba1473da399a6985baf8581a055e2580
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A tests/qtest/cxl-test.c
M tests/qtest/meson.build
Log Message:
-----------
qtest/cxl: Introduce initial test for pxb-cxl only.
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-16-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 15b661d45629df89d91bc05c267ad14e4e88cd97
https://github.com/qemu/qemu/commit/15b661d45629df89d91bc05c267ad14e4e88cd97
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci-bridge/Kconfig
A hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/meson.build
M hw/pci-bridge/pcie_root_port.c
M hw/pci/pci.c
Log Message:
-----------
hw/cxl/rp: Add a root port
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to a
specific CXL host bridge. For example:
-device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4
Like the host bridge patch, the ACPI tables aren't generated at this
point and so system software cannot use it.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3ffeefc00b0951a199d2d0f750b9435356646d45
https://github.com/qemu/qemu/commit/3ffeefc00b0951a199d2d0f750b9435356646d45
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/Kconfig
A hw/mem/cxl_type3.c
M hw/mem/meson.build
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_pci.h
M include/hw/pci/pci_ids.h
Log Message:
-----------
hw/cxl/device: Add a memory device (8.2.8.5)
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a normal PCIe device, the
memory traffic is on an entirely separate bus conceptually (using the
same physical wires as PCIe, but different protocol).
Once the CXL topology is fully configure and address decoders committed,
the guest physical address for the memory device is part of a larger
window which is owned by the platform. The creation of these windows
is later in this series.
The following example will create a 256M device in a 512M window:
-object "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M"
-device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0"
Note: Dropped PCDIMM info interfaces for now. They can be added if
appropriate at a later date.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-18-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 87135e5047d073aee19ea0c5e1e0f203ebac5363
https://github.com/qemu/qemu/commit/87135e5047d073aee19ea0c5e1e0f203ebac5363
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly program
the HDMs, the HDM decoders must be modeled.
There are two ways the HDM decoders can be implemented, the legacy
mechanism is through the PCIe DVSEC programming from CXL 1.1 (8.1.3.8),
and MMIO is found in 8.2.5.12 of the spec. For now, 8.1.3.8 is not
implemented.
Much of CXL device logic is implemented in cxl-utils. The HDM decoder
however is implemented directly by the device implementation.
Whilst the implementation currently does no validity checks on the
encoder set up, future work will add sanity checking specific to
the type of cxl component.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-19-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: dfcbca2cd48a01a89f01e50e3cfe195a2a01c0a7
https://github.com/qemu/qemu/commit/dfcbca2cd48a01a89f01e50e3cfe195a2a01c0a7
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add some trivial commands
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-20-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2a89b10178e49cb3fc521f6a538c66a37ea79833
https://github.com/qemu/qemu/commit/2a89b10178e49cb3fc521f6a538c66a37ea79833
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Plumb real Label Storage Area (LSA) sizing
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-21-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a53335e5700817f4773094b7dc1a789cf63477bc
https://github.com/qemu/qemu/commit/a53335e5700817f4773094b7dc1a789cf63477bc
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement get/set Label Storage Area (LSA)
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-22-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0d89344c8e8377b9f2d000006f3512520bfabcc5
https://github.com/qemu/qemu/commit/0d89344c8e8377b9f2d000006f3512520bfabcc5
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
qtests/cxl: Add initial root port and CXL type3 tests
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-23-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8510ba91b975e1b4eb2fe5ac3cd6682141ca2edf
https://github.com/qemu/qemu/commit/8510ba91b975e1b4eb2fe5ac3cd6682141ca2edf
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/acpi-build.c
M hw/i386/pc.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/cxl/cxl.h
Log Message:
-----------
hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicate the PCI express case for the aml_build but
the implementations will diverge when the CXL specific _OSC is
introduced.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-24-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7286c83aaed9c8b9728cc2d145d38cdb4cd10506
https://github.com/qemu/qemu/commit/7286c83aaed9c8b9728cc2d145d38cdb4cd10506
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/acpi/Kconfig
A hw/acpi/cxl-stub.c
A hw/acpi/cxl.c
M hw/acpi/meson.build
M hw/i386/acpi-build.c
A include/hw/acpi/cxl.h
Log Message:
-----------
acpi/cxl: Add _OSC implementation (9.14.2)
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
iasl -d decodes the result of this patch as:
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SUPC, Zero)
Name (CTRC, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host
Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")
/* Unknown UUID */)))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
SUPP = CDW2 /* \_SB_.PC0C._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
CDW3 = Local0
If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown
UUID */))
{
CreateDWordField (Arg3, 0x0C, CDW4)
CreateDWordField (Arg3, 0x10, CDW5)
SUPC = CDW4 /* \_SB_.PC0C._OSC.CDW4 */
CTRC = CDW5 /* \_SB_.PC0C._OSC.CDW5 */
CDW5 |= One
}
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-25-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2b36e05bbf90badca8083fcbb1db21288dd8487a
https://github.com/qemu/qemu/commit/2b36e05bbf90badca8083fcbb1db21288dd8487a
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/acpi/cxl.c
M hw/i386/acpi-build.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/acpi/cxl.h
M include/hw/pci/pci_bridge.h
Log Message:
-----------
acpi/cxl: Create the CEDT (9.14.1)
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware software
is able to use this initiate the proper _OSC method, and get the _UID
which is referenced by the CEDT. Therefore the existence of an ACPI0016
device allows a CXL aware driver perform the necessary actions. For a
CXL capable OS, this works. For a CXL unaware OS, this works.
CEDT awaremess requires more. The motivation for ACPI0017 is to provide
the possibility of having a Linux CXL module that can work on a legacy
Linux kernel. Linux core PCI/ACPI which won't be built as a module,
will see the _CID of PNP0A08 and bind a driver to it. If we later loaded
a driver for ACPI0016, Linux won't be able to bind it to the hardware
because it has already bound the PNP0A08 driver. The ACPI0017 device is
an opportunity to have an object to bind a driver will be used by a
Linux driver to walk the CXL topology and do everything that we would
have preferred to do with ACPI0016.
There is another motivation for an ACPI0017 device which isn't
implemented here. An operating system needs an attach point for a
non-volatile region provider that understands cross-hostbridge
interleaving. Since QEMU emulation doesn't support interleaving yet,
this is more important on the OS side, for now.
As of CXL 2.0 spec, only 1 sub structure is defined, the CXL Host Bridge
Structure (CHBS) which is primarily useful for telling the OS exactly
where the MMIO for the host bridge is.
Link:
https://lore.kernel.org/linux-cxl/20210115034911.nkgpzc756d6qmjpl@intel.com/T/#t
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-26-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6acd79c8a69010f12ffd23f1598c4f34b5839da2
https://github.com/qemu/qemu/commit/6acd79c8a69010f12ffd23f1598c4f34b5839da2
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl/component: Add utils for interleave parameter encoding/decoding
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-27-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ef9195d86d65ab7204dfef2e1946a984964a0a23
https://github.com/qemu/qemu/commit/ef9195d86d65ab7204dfef2e1946a984964a0a23
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A hw/cxl/cxl-host-stubs.c
A hw/cxl/cxl-host.c
M hw/cxl/meson.build
M include/hw/cxl/cxl.h
M qapi/machine.json
M qemu-options.hx
M softmmu/vl.c
Log Message:
-----------
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window
targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b0bfa1645cc7d0558b7a6d3511176dba34161433
https://github.com/qemu/qemu/commit/b0bfa1645cc7d0558b7a6d3511176dba34161433
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/acpi/cxl.c
Log Message:
-----------
acpi/cxl: Introduce CFMWS structures in CEDT
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-29-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0bd04d42224c27b6ecc2ad50cd1d575c23b57908
https://github.com/qemu/qemu/commit/0bd04d42224c27b6ecc2ad50cd1d575c23b57908
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/Kconfig
M hw/pci-host/gpex-acpi.c
Log Message:
-----------
hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-30-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2f2f08f2cbcfb12bfbf422211ca69ab0644a18a7
https://github.com/qemu/qemu/commit/2f2f08f2cbcfb12bfbf422211ca69ab0644a18a7
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci/pcie_port.c
M include/hw/pci/pcie_port.h
Log Message:
-----------
pci/pcie_port: Add pci_find_port_by_pn()
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-31-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ab82e3736e8b73852c5cebd4167efd8fb4545c17
https://github.com/qemu/qemu/commit/ab82e3736e8b73852c5cebd4167efd8fb4545c17
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
CXL/cxl_component: Add cxl_get_hb_cstate()
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-32-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 871a8c154f889a65ecd4f2a4a26ac6f8c83d386a
https://github.com/qemu/qemu/commit/871a8c154f889a65ecd4f2a4a26ac6f8c83d386a
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
mem/cxl_type3: Add read and write functions for associated hostmem.
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device specific address space to access the
hostmem->mr to fullfil the actual operation. Note that failed writes
are silent, but failed reads return poison. Note this is based
loosely on:
https://lore.kernel.org/qemu-devel/20200817161853.593247-6-f4bug@amsat.org/
[RFC PATCH 0/9] hw/misc: Add support for interleaved memory accesses
Only lightly tested so far. More complex test cases yet to be written.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-33-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 193c621a75a0b964966c7125da3f181698346827
https://github.com/qemu/qemu/commit/193c621a75a0b964966c7125da3f181698346827
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-host-stubs.c
M hw/cxl/cxl-host.c
M include/hw/cxl/cxl.h
Log Message:
-----------
cxl/cxl-host: Add memops for CFMWS region.
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the current implementation does
not support:
* switches
* multiple HDM decoders at a given level.
* unaligned accesses across the interleave boundaries
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: afcf251f40325fb54ed4f2d91f59fd003b2079b5
https://github.com/qemu/qemu/commit/afcf251f40325fb54ed4f2d91f59fd003b2079b5
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl/component Add a dumb HDM decoder handler
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-35-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c8cd94469ecfac56600d5c8ebe098962af4af916
https://github.com/qemu/qemu/commit/c8cd94469ecfac56600d5c8ebe098962af4af916
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/pc: Enable CXL fixed memory windows
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-Id: <20220429144110.25167-36-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4e082d4990e7b15d019bbdba3bef96c14b383d52
https://github.com/qemu/qemu/commit/4e082d4990e7b15d019bbdba3bef96c14b383d52
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A tests/data/acpi/q35/CEDT.cxl
A tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: q35: Allow addition of a CXL test.
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-37-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 115afe6eb8ec7bab7071d93c73356c6016cd2331
https://github.com/qemu/qemu/commit/115afe6eb8ec7bab7071d93c73356c6016cd2331
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
qtests/bios-tables-test: Add a test for CXL emulation.
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-38-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d410702480509a3d880f89316f449da616bb459f
https://github.com/qemu/qemu/commit/d410702480509a3d880f89316f449da616bb459f
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/data/acpi/q35/CEDT.cxl
M tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Add tables for CXL emulation.
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-39-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d8efd58c3da725aa23f019313e7c251db67c40ba
https://github.com/qemu/qemu/commit/d8efd58c3da725aa23f019313e7c251db67c40ba
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
qtest/cxl: Add more complex test cases with CFMWs
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-40-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 26a19f8eef2e1a50d483e5ffe3a7be8885636572
https://github.com/qemu/qemu/commit/26a19f8eef2e1a50d483e5ffe3a7be8885636572
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/device-emulation.rst
A docs/system/devices/cxl.rst
Log Message:
-----------
docs/cxl: Add initial Compute eXpress Link (CXL) documentation.
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which is relevant to either
users of QEMU emulation of CXL or to those interested in the
implementation. Much of CXL is concerned with specific elements of
the protocol, management of memory pooling etc which is simply
not relevant to what is currently planned for CXL emulation
in QEMU. All comments welcome
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-43-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5b2495134ca5a2bc7b5769de9fa319850330a06f
https://github.com/qemu/qemu/commit/5b2495134ca5a2bc7b5769de9fa319850330a06f
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
Log Message:
-----------
vhost: Track descriptor chain in private at SVQ
The device could have access to modify them, and it definitely have
access when we implement packed vq. Harden SVQ maintaining a private
copy of the descriptor chain. Other fields like buffer addresses are
already maintained sepparatedly.
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-2-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9196f03db90e303cc93bc91e56f5294ad0685c83
https://github.com/qemu/qemu/commit/9196f03db90e303cc93bc91e56f5294ad0685c83
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
Log Message:
-----------
vhost: Fix device's used descriptor dequeue
Only the first one of them were properly enqueued back.
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-3-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0b3d6f273322b9ba4476695b8f7888f71395edf0
https://github.com/qemu/qemu/commit/0b3d6f273322b9ba4476695b8f7888f71395edf0
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vdpa: Fix bad index calculus at vhost_vdpa_get_vring_base
Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-4-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0ff598b346408958133e17e552bfd3556ef631ee
https://github.com/qemu/qemu/commit/0ff598b346408958133e17e552bfd3556ef631ee
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vdpa: Fix index calculus at vhost_vdpa_svqs_start
With the introduction of MQ the index of the vq needs to be calculated
with the device model vq_index.
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220512175747.142058-5-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c486f74114e7632b7e11f5bc11eeb76fbcb3f5f2
https://github.com/qemu/qemu/commit/c486f74114e7632b7e11f5bc11eeb76fbcb3f5f2
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/virtio-net.c
M hw/virtio/virtio-crypto.c
Log Message:
-----------
hw/virtio: Replace g_memdup() by g_memdup2()
Per
https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
The old API took the size of the memory to duplicate as a guint,
whereas most memory functions take memory sizes as a gsize. This
made it easy to accidentally pass a gsize to g_memdup(). For large
values, that would lead to a silent truncation of the size from 64
to 32 bits, and result in a heap area being returned which is
significantly smaller than what the caller expects. This can likely
be exploited in various modules to cause a heap buffer overflow.
Replace g_memdup() by the safer g_memdup2() wrapper.
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20220512175747.142058-6-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 71bbd5abe0d9505bce9d545efb91383f5ba3fdb1
https://github.com/qemu/qemu/commit/71bbd5abe0d9505bce9d545efb91383f5ba3fdb1
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
Log Message:
-----------
vhost: Fix element in vhost_svq_add failure
Coverity rightly reports that is not free in that case.
Fixes: Coverity CID 1487559
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-7-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eabc607485f7174d30bcc0d289c47a2b5da64b28
https://github.com/qemu/qemu/commit/eabc607485f7174d30bcc0d289c47a2b5da64b28
Author: David Woodhouse <dwmw2@infradead.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/pc.c
M hw/i386/x86.c
M target/i386/kvm/kvm-cpu.c
Log Message:
-----------
target/i386: Fix sanity check on max APIC ID / X2APIC enablement
The check on x86ms->apic_id_limit in pc_machine_done() had two problems.
Firstly, we need KVM to support the X2APIC API in order to allow IRQ
delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(),
which was done elsewhere in *some* cases but not all.
Secondly, microvm needs the same check. So move it from pc_machine_done()
to x86_cpus_init() where it will work for both.
The check in kvm_cpu_instance_init() is now redundant and can be dropped.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Acked-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20220314142544.150555-1-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c3fbaf775067e7b648f7733b5fbeb7d8eb5c4eff
https://github.com/qemu/qemu/commit/c3fbaf775067e7b648f7733b5fbeb7d8eb5c4eff
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Support IR-only mode without DMA translation
By setting none of the SAGAW bits we can indicate to a guest that DMA
translation isn't supported. Tested by booting Windows 10, as well as
Linux guests with the fix at https://git.kernel.org/torvalds/c/c40aaaac10
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Peter Xu <peterx@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220314142544.150555-2-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e4991dfc07c02e92614b50413ad1a8cb8fce797a
https://github.com/qemu/qemu/commit/e4991dfc07c02e92614b50413ad1a8cb8fce797a
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Only allow interrupt remapping to be enabled if it's supported
We should probably check if we were meant to be exposing IR, before
letting the guest turn the IRE bit on.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Peter Xu <peterx@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220314142544.150555-3-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6dd2af645cfab46a7fe43dadf5aea4283a47b785
https://github.com/qemu/qemu/commit/6dd2af645cfab46a7fe43dadf5aea4283a47b785
Author: David Woodhouse <dwmw2@infradead.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Fix irqchip / X2APIC configuration checks
We don't need to check kvm_enable_x2apic(). It's perfectly OK to support
interrupt remapping even if we can't address CPUs above 254. Kind of
pointless, but still functional.
The check on kvm_enable_x2apic() needs to happen *anyway* in order to
allow CPUs above 254 even without an IOMMU, so allow that to happen
elsewhere.
However, we do require the *split* irqchip in order to rewrite I/OAPIC
destinations. So fix that check while we're here.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Acked-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20220314142544.150555-4-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 53d6beb292422ceace0e32878a10194e20516eec
https://github.com/qemu/qemu/commit/53d6beb292422ceace0e32878a10194e20516eec
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: remove VTD_FR_RESERVED_ERR
This fault reason is not used and is duplicated with SPT.2 condition
code. So let's remove it.
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220210092815.45174-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 6eb6e82a35737db73198a1b39d77ca1e88f05295
https://github.com/qemu/qemu/commit/6eb6e82a35737db73198a1b39d77ca1e88f05295
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: block output address in interrupt address range
According to vtd spec v3.3 3.14:
"""
Software must not program paging-structure entries to remap any
address to the interrupt address range. Untranslated requests and
translation requests that result in an address in the interrupt range
will be blocked with condition code LGN.4 or SGN.8.
"""
This patch blocks the request that result in interrupt address range.
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220210092815.45174-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 76380bd2ba05f8c431edae05b619b088c21275d9
https://github.com/qemu/qemu/commit/76380bd2ba05f8c431edae05b619b088c21275d9
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: update root_scalable before switching as during post_load
We need check whether passthrough is enabled during
vtd_switch_address_space() by checking the context entries. This
requires the root_scalable to be set correctly otherwise we may try to
check legacy rsvd bits instead of scalable ones.
Fixing this by updating root_scalable before switching the address
spaces during post_load.
Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220317080522.14621-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 970f18581ae517cb98f4e7cd0721aaeeb7dc82b4
https://github.com/qemu/qemu/commit/970f18581ae517cb98f4e7cd0721aaeeb7dc82b4
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: update iq_dw during post load
We need to update iq_dw according to the DMA_IRQ_REG during post
load. Otherwise we may get wrong IOTLB invalidation descriptor after
migration.
Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220317080522.14621-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 3d6c8e33393b12a96b44f1051777bbfbf95a598a
https://github.com/qemu/qemu/commit/3d6c8e33393b12a96b44f1051777bbfbf95a598a
Author: Ilya Maximets <i.maximets@ovn.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/vhost_net.c
Log Message:
-----------
vhost_net: Print feature masks in hex
"0x200000000" is much more readable than "8589934592".
The change saves one step (conversion) while debugging.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Message-Id: <20220318140440.596019-1-i.maximets@ovn.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 639124c0096eae40a43f0f5357a01a78f8cb792f
https://github.com/qemu/qemu/commit/639124c0096eae40a43f0f5357a01a78f8cb792f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-scsi-pci.c
M hw/virtio/vhost-user-blk-pci.c
M hw/virtio/vhost-user-fs-pci.c
M hw/virtio/vhost-user-i2c-pci.c
M hw/virtio/vhost-user-input-pci.c
M hw/virtio/vhost-user-rng-pci.c
M hw/virtio/vhost-user-scsi-pci.c
M hw/virtio/vhost-user-vsock-pci.c
M hw/virtio/vhost-vsock-pci.c
M hw/virtio/virtio-9p-pci.c
M hw/virtio/virtio-balloon-pci.c
M hw/virtio/virtio-blk-pci.c
M hw/virtio/virtio-input-host-pci.c
M hw/virtio/virtio-input-pci.c
M hw/virtio/virtio-iommu-pci.c
M hw/virtio/virtio-net-pci.c
M hw/virtio/virtio-pci.c
R hw/virtio/virtio-pci.h
M hw/virtio/virtio-rng-pci.c
M hw/virtio/virtio-scsi-pci.c
M hw/virtio/virtio-serial-pci.c
A include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio: move virtio-pci.h into shared include space
This allows other device classes that will be exposed via PCI to be
able to do so in the appropriate hw/ directory. I resisted the
temptation to re-order headers to be more aesthetically pleasing.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200925125147.26943-4-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-2-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2df890338b4b8fa636fead410004cf4bc6b1ce1a
https://github.com/qemu/qemu/commit/2df890338b4b8fa636fead410004cf4bc6b1ce1a
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/virtio-pci.c
Log Message:
-----------
virtio-pci: add notification trace points
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200925125147.26943-6-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-3-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: dbf8a789ced4acb151fd3c8445db20b973bcfba8
https://github.com/qemu/qemu/commit/dbf8a789ced4acb151fd3c8445db20b973bcfba8
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/vhost-user.c
Log Message:
-----------
hw/virtio: add vhost_user_[read|write] trace points
These are useful when trying to debug the initial vhost-user
negotiation, especially when it hard to get logging from the low level
library on the other side.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-4-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3a41b3c5e0fde6e999812d10af0e02192af9de45
https://github.com/qemu/qemu/commit/3a41b3c5e0fde6e999812d10af0e02192af9de45
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: clean up request/reply description
It is not necessary to mention which side is sending/receiving
each payload; it is more interesting to say which is the request
and which is the reply. This also matches what vhost-user-gpu.rst
already does.
While at it, ensure that all messages list both the request and
the reply payload.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-2-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-5-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 4f36f50d34e727f20098c8910b08a256be71f0ff
https://github.com/qemu/qemu/commit/4f36f50d34e727f20098c8910b08a256be71f0ff
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: rewrite section on ring state machine
This section is using the word "back-end" to refer to the
"slave's back-end", and talking about the "client" for
what the rest of the document calls the "slave".
Rework it to free the use of the term "back-end", which in
the next patch will replace "slave".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-3-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-6-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 799149d9c29a4dc220cf09166fb1b91e0ba8acfa
https://github.com/qemu/qemu/commit/799149d9c29a4dc220cf09166fb1b91e0ba8acfa
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user-gpu.rst
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: replace master/slave with front-end/back-end
This matches the nomenclature that is generally used. Also commonly used
is client/server, but it is not as clear because sometimes the front-end
exposes a passive (server) socket that the back-end connects to.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-4-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-7-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6b66681e9c08aeda599203f977d9a76db43d8c4c
https://github.com/qemu/qemu/commit/6b66681e9c08aeda599203f977d9a76db43d8c4c
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: add clarifying language about protocol negotiation
Make the language about feature negotiation explicitly clear about the
handling of the VHOST_USER_F_PROTOCOL_FEATURES feature bit. Try and
avoid the sort of bug introduced in vhost.rs REPLY_ACK processing:
https://github.com/rust-vmm/vhost/pull/24
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Jiang Liu <gerry@linux.alibaba.com>
Message-Id: <20210226111619.21178-1-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-8-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ecd20431a5b6e8f2ee3a44e421fe17db94ab3448
https://github.com/qemu/qemu/commit/ecd20431a5b6e8f2ee3a44e421fe17db94ab3448
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M subprojects/libvhost-user/libvhost-user.c
M subprojects/libvhost-user/libvhost-user.h
Log Message:
-----------
libvhost-user: expose vu_request_to_string
This is useful for more human readable debug messages in vhost-user
programs.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-9-alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4c57b02e482bbded40c2d88000dd834a858ae91c
https://github.com/qemu/qemu/commit/4c57b02e482bbded40c2d88000dd834a858ae91c
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/devel/index-internals.rst
A docs/devel/virtio-backends.rst
Log Message:
-----------
docs/devel: start documenting writing VirtIO devices
While writing my own VirtIO devices I've gotten confused with how
things are structured and what sort of shared infrastructure there is.
If we can document how everything is supposed to work we can then
maybe start cleaning up inconsistencies in the code.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20220309164929.19395-1-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-10-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e798d75109c870220d626f14a18d078300067746
https://github.com/qemu/qemu/commit/e798d75109c870220d626f14a18d078300067746
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/hw/virtio/vhost.h
Log Message:
-----------
include/hw: start documenting the vhost API
While trying to get my head around the nest of interactions for vhost
devices I though I could start by documenting the key API functions.
This patch documents the main API hooks for creating and starting a
vhost device as well as how the configuration changes are handled.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220321153037.3622127-11-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f3d93b9adc045048634cf17aaf469831852f7020
https://github.com/qemu/qemu/commit/f3d93b9adc045048634cf17aaf469831852f7020
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
hw/virtio/vhost-user: don't suppress F_CONFIG when supported
Previously we would silently suppress VHOST_USER_PROTOCOL_F_CONFIG
during the protocol negotiation if the QEMU stub hadn't implemented
the vhost_dev_config_notifier. However this isn't the only way we can
handle config messages, the existing vdc->get/set_config can do this
as well.
Lightly re-factor the code to check for both potential methods and
instead of silently squashing the feature error out. It is unlikely
that a vhost-user backend expecting to handle CONFIG messages will
behave correctly if they never get sent.
Fixes: 1c3e5a2617 ("vhost-user: back SET/GET_CONFIG requests with a protocol
feature")
Cc: Maxime Coquelin <maxime.coquelin@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-13-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8619b7fb86d48732181850c1e6dea1294d2b92d1
https://github.com/qemu/qemu/commit/8619b7fb86d48732181850c1e6dea1294d2b92d1
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
virtio/vhost-user: dynamically assign VhostUserHostNotifiers
At a couple of hundred bytes per notifier allocating one for every
potential queue is very wasteful as most devices only have a few
queues. Instead of having this handled statically dynamically assign
them and track in a GPtrArray.
[AJB: it's hard to trigger the vhost notifiers code, I assume as it
requires a KVM guest with appropriate backend]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-14-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 09a13da23ffb1941a5251b552ffdf38a842a601a
https://github.com/qemu/qemu/commit/09a13da23ffb1941a5251b552ffdf38a842a601a
Author: Jonah Palmer <jonah.palmer@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/9pfs/virtio-9p-device.c
M hw/block/vhost-user-blk.c
M hw/block/virtio-blk.c
M hw/char/virtio-serial-bus.c
M hw/display/virtio-gpu-base.c
M hw/input/virtio-input.c
M hw/net/virtio-net.c
M hw/scsi/virtio-scsi.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user-i2c.c
M hw/virtio/vhost-user-rng.c
M hw/virtio/vhost-user-vsock.c
M hw/virtio/vhost-vsock-common.c
M hw/virtio/vhost-vsock.c
M hw/virtio/virtio-balloon.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio-iommu.c
M hw/virtio/virtio-mem.c
M hw/virtio/virtio-pmem.c
M hw/virtio/virtio-rng.c
M hw/virtio/virtio.c
M include/hw/virtio/vhost-vsock-common.h
M include/hw/virtio/virtio-gpu.h
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: drop name parameter for virtio_init()
This patch drops the name parameter for the virtio_init function.
The pair between the numeric device ID and the string device ID
(name) of a virtio device already exists, but not in a way that
lets us map between them.
This patch lets us do this and removes the need for the name
parameter in the virtio_init function.
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <1648819405-25696-2-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8fd62d0542192b3d490ff0e070f8eeb756e4b3cd
https://github.com/qemu/qemu/commit/8fd62d0542192b3d490ff0e070f8eeb756e4b3cd
Author: Jonah Palmer <jonah.palmer@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/display/vhost-user-gpu.c
M hw/input/vhost-user-input.c
M hw/net/virtio-net.c
M hw/scsi/vhost-scsi.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user-rng.c
M hw/virtio/vhost-vsock-common.c
M hw/virtio/vhost.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: add vhost support for virtio devices
This patch adds a get_vhost() callback function for VirtIODevices that
returns the device's corresponding vhost_dev structure, if the vhost
device is running. This patch also adds a vhost_started flag for
VirtIODevices.
Previously, a VirtIODevice wouldn't be able to tell if its corresponding
vhost device was active or not.
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <1648819405-25696-3-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f96c910a23c391fe03cf5f6fd0e55340ce4c4a88
https://github.com/qemu/qemu/commit/f96c910a23c391fe03cf5f6fd0e55340ce4c4a88
Author: Michael S. Tsirkin <mst@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user: more master/slave things
we switched to front-end/back-end, but newer patches
reintroduced old language. Fix this up.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ec0e808cd16341b0fdf3f35a4b1bbb2acdc6687c
https://github.com/qemu/qemu/commit/ec0e808cd16341b0fdf3f35a4b1bbb2acdc6687c
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG
The specification for VHOST_USER_ADD/REM_MEM_REG messages is unclear
in several points, which has led to clients having incompatible
implementations. This changes the specification to be more explicit
about them:
* VHOST_USER_ADD_MEM_REG is not specified as receiving a file
descriptor, though it obviously does need to do so. All
implementations agree on this one, fix the specification.
* VHOST_USER_REM_MEM_REG is not specified as receiving a file
descriptor either, and it also has no reason to do so. rust-vmm does
not send file descriptors for removing a memory region (in agreement
with the specification), libvhost-user and QEMU do (which is a bug),
though libvhost-user doesn't actually make any use of it.
Change the specification so that for compatibility QEMU's behaviour
becomes legal, even if discouraged, but rust-vmm's behaviour becomes
the explicitly recommended mode of operation.
* VHOST_USER_ADD_MEM_REG doesn't have a documented return value, which
is the desired behaviour in the non-postcopy case. It also implemented
like this in QEMU and rust-vmm, though libvhost-user is buggy and
sometimes sends an unexpected reply. This will be fixed in a separate
patch.
However, in postcopy mode it does reply like VHOST_USER_SET_MEM_TABLE.
This behaviour is shared between libvhost-user and QEMU; rust-vmm
doesn't implement postcopy mode yet. Mention it explicitly in the
spec.
* The specification doesn't mention how VHOST_USER_REM_MEM_REG
identifies the memory region to be removed. Change it to describe the
existing behaviour of libvhost-user (guest address, user address and
size must match).
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220407133657.155281-2-kwolf@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: d4e25e4877b78eb813706fc868963e56c8d30adc
https://github.com/qemu/qemu/commit/d4e25e4877b78eb813706fc868963e56c8d30adc
Author: Francisco Iglesias <frasse.iglesias@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/hw/pci/pcie_host.h
Log Message:
-----------
include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits). Below is the formula taken from Table
7-1 in [1].
"
Memory Address | PCI Express Configuration Space
A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8
"
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-2-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 433742fa183618c1467dcf10f380f8fadc4a77ea
https://github.com/qemu/qemu/commit/433742fa183618c1467dcf10f380f8fadc4a77ea
Author: Francisco Iglesias <frasse.iglesias@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/hw/pci/pcie_host.h
Log Message:
-----------
include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c24ff22e399e09dd6c52accb3641901fae696a6b
https://github.com/qemu/qemu/commit/c24ff22e399e09dd6c52accb3641901fae696a6b
Author: Xiaoyao Li <xiaoyao.li@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/i386/x86.c
M include/hw/i386/microvm.h
M include/hw/i386/pc.h
M include/hw/i386/x86.h
Log Message:
-----------
hw/i386: Make pit a property of common x86 base machine type
Both pc and microvm have pit property individually. Let's just make it
the property of common x86 base machine type.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-Id: <20220310122811.807794-2-xiaoyao.li@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 94e20ed006061d67d575ee9ef74fb48c09c6a499
https://github.com/qemu/qemu/commit/94e20ed006061d67d575ee9ef74fb48c09c6a499
Author: Xiaoyao Li <xiaoyao.li@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/microvm.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M include/hw/i386/microvm.h
M include/hw/i386/x86.h
Log Message:
-----------
hw/i386: Make pic a property of common x86 base machine type
Legacy PIC (8259) cannot be supported for TDX guests since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Make PIC the property of common x86 machine type. Hence all x86
machines, including microvm, can disable it.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-Id: <20220310122811.807794-3-xiaoyao.li@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 01206ef6187ac0b8a05fdd7cc9f3879fc3d8a5e5
https://github.com/qemu/qemu/commit/01206ef6187ac0b8a05fdd7cc9f3879fc3d8a5e5
Author: Wei Huang <wei.huang2@amd.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
hw/i386/amd_iommu: Fix IOMMU event log encoding errors
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID 1487116/1487200/1487190/1487232/1487115/1487258
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Message-Id: <20220422055146.3312226-1-wei.huang2@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1fa1fff076ae6f7fa616a269cf04c4034b4372c3
https://github.com/qemu/qemu/commit/1fa1fff076ae6f7fa616a269cf04c4034b4372c3
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: setup vhost_dev and notifiers for cvq only when feature is
negotiated
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when needed.
Fixes: 22288fe ("virtio-net: vhost control virtqueue support")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-2-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ec3c3e89d1ea8de80f86a6cf52f90624917be081
https://github.com/qemu/qemu/commit/ec3c3e89d1ea8de80f86a6cf52f90624917be081
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >=
dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
0 0x00007f8ce3ff3387 in raise () at /lib64/libc.so.6
1 0x00007f8ce3ff4a78 in abort () at /lib64/libc.so.6
2 0x00007f8ce3fec1a6 in __assert_fail_base () at /lib64/libc.so.6
3 0x00007f8ce3fec252 in () at /lib64/libc.so.6
4 0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>,
idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:563
5 0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>,
idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:558
6 0x0000558f52d7329a in vhost_virtqueue_mask (hdev=0x558f55c01800,
vdev=0x558f568f91f0, n=2, mask=<optimized out>) at ../hw/virtio/vhost.c:1557
7 0x0000558f52c6b89a in virtio_pci_set_guest_notifier
(d=d@entry=0x558f568f0f60, n=n@entry=2, assign=assign@entry=true,
with_irqfd=with_irqfd@entry=false)
at ../hw/virtio/virtio-pci.c:974
8 0x0000558f52c6c0d8 in virtio_pci_set_guest_notifiers (d=0x558f568f0f60,
nvqs=3, assign=true) at ../hw/virtio/virtio-pci.c:1019
9 0x0000558f52bf091d in vhost_net_start (dev=dev@entry=0x558f568f91f0,
ncs=0x558f56937cd0, data_queue_pairs=data_queue_pairs@entry=1, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:361
10 0x0000558f52d4e5e7 in virtio_net_set_status (status=<optimized out>,
n=0x558f568f91f0) at ../hw/net/virtio-net.c:289
11 0x0000558f52d4e5e7 in virtio_net_set_status (vdev=0x558f568f91f0, status=15
'\017') at ../hw/net/virtio-net.c:370
12 0x0000558f52d6c4b2 in virtio_set_status (vdev=vdev@entry=0x558f568f91f0,
val=val@entry=15 '\017') at ../hw/virtio/virtio.c:1945
13 0x0000558f52c69eff in virtio_pci_common_write (opaque=0x558f568f0f60,
addr=<optimized out>, val=<optimized out>, size=<optimized out>) at
../hw/virtio/virtio-pci.c:1292
14 0x0000558f52d15d6e in memory_region_write_accessor (mr=0x558f568f19d0,
addr=20, value=<optimized out>, size=1, shift=<optimized out>, mask=<optimized
out>, attrs=...)
at ../softmmu/memory.c:492
15 0x0000558f52d127de in access_with_adjusted_size (addr=addr@entry=20,
value=value@entry=0x7f8cdbffe748, size=size@entry=1, access_size_min=<optimized
out>, access_size_max=<optimized out>, access_fn=0x558f52d15cf0
<memory_region_write_accessor>, mr=0x558f568f19d0, attrs=...) at
../softmmu/memory.c:554
16 0x0000558f52d157ef in memory_region_dispatch_write
(mr=mr@entry=0x558f568f19d0, addr=20, data=<optimized out>, op=<optimized out>,
attrs=attrs@entry=...)
at ../softmmu/memory.c:1504
17 0x0000558f52d078e7 in flatview_write_continue (fv=fv@entry=0x7f8accbc3b90,
addr=addr@entry=103079215124, attrs=..., ptr=ptr@entry=0x7f8ce6300028,
len=len@entry=1, addr1=<optimized out>, l=<optimized out>, mr=0x558f568f19d0)
at /home/opc/qemu-upstream/include/qemu/host-utils.h:165
18 0x0000558f52d07b06 in flatview_write (fv=0x7f8accbc3b90, addr=103079215124,
attrs=..., buf=0x7f8ce6300028, len=1) at ../softmmu/physmem.c:2822
19 0x0000558f52d0b36b in address_space_write (as=<optimized out>,
addr=<optimized out>, attrs=..., buf=buf@entry=0x7f8ce6300028, len=<optimized
out>)
at ../softmmu/physmem.c:2914
20 0x0000558f52d0b3da in address_space_rw (as=<optimized out>, addr=<optimized
out>, attrs=...,
attrs@entry=..., buf=buf@entry=0x7f8ce6300028, len=<optimized out>,
is_write=<optimized out>) at ../softmmu/physmem.c:2924
21 0x0000558f52dced09 in kvm_cpu_exec (cpu=cpu@entry=0x558f55c2da60) at
../accel/kvm/kvm-all.c:2903
22 0x0000558f52dcfabd in kvm_vcpu_thread_fn (arg=arg@entry=0x558f55c2da60) at
../accel/kvm/kvm-accel-ops.c:49
23 0x0000558f52f9f04a in qemu_thread_start (args=<optimized out>) at
../util/qemu-thread-posix.c:556
24 0x00007f8ce4392ea5 in start_thread () at /lib64/libpthread.so.0
25 0x00007f8ce40bb9fd in clone () at /lib64/libc.so.6
The cause for the assert failure is due to that the vhost_dev index
for the ctrl vq was not aligned with actual one in use by the guest.
Upon multiqueue feature negotiation in virtio_net_set_multiqueue(),
if guest doesn't support multiqueue, the guest vq layout would shrink
to a single queue pair, consisting of 3 vqs in total (rx, tx and ctrl).
This results in ctrl_vq taking a different vhost_dev group index than
the default. We can map vq to the correct vhost_dev group by checking
if MQ is supported by guest and successfully negotiated. Since the
MQ feature is only present along with CTRL_VQ, we ensure the index
2 is only meant for the control vq while MQ is not supported by guest.
Fixes: 22288fe ("virtio-net: vhost control virtqueue support")
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-3-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 703ba58d684d9fa0c8e3c5e3133469f0a49bf138
https://github.com/qemu/qemu/commit/703ba58d684d9fa0c8e3c5e3133469f0a49bf138
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa
... such that no memory leaks on dangling net clients in case of
error.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-4-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 113ea37c41c86577a09895186142393be7a341e5
https://github.com/qemu/qemu/commit/113ea37c41c86577a09895186142393be7a341e5
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/vhost_net.c
Log Message:
-----------
vhost-net: fix improper cleanup in vhost_net_start
vhost_net_start() missed a corresponding stop_one() upon error from
vhost_set_vring_enable(). While at it, make the error handling for
err_start more robust. No real issue was found due to this though.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-5-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5617d25ebd737b5b00158a012e24d0bb08c6c8bb
https://github.com/qemu/qemu/commit/5617d25ebd737b5b00158a012e24d0bb08c6c8bb
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: backend feature should set only once
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev's.
To fix it, send down ioctl only once via the first
vhost_dev with index 0. Toggle the polarity of the
vhost_vdpa_one_time_request() test should do the
trick.
Fixes: 4d191cfdc7de ("vhost-vdpa: classify one time request")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <1651890498-24478-6-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2edd7374d3a99778fb7f624c22984ada10c447c5
https://github.com/qemu/qemu/commit/2edd7374d3a99778fb7f624c22984ada10c447c5
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request()
The name vhost_vdpa_one_time_request() was confusing. No
matter whatever it returns, its typical occurrence had
always been at requests that only need to be applied once.
And the name didn't suggest what it actually checks for.
Change it to vhost_vdpa_first_dev() with polarity flipped
for better readibility of code. That way it is able to
reflect what the check is really about.
This call is applicable to request which performs operation
only once, before queues are set up, and usually at the beginning
of the caller function. Document the requirement for it in place.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Message-Id: <1651890498-24478-7-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Commit: 81bfa74048a6cf71883bdf63e1116870622e638a
https://github.com/qemu/qemu/commit/81bfa74048a6cf71883bdf63e1116870622e638a
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: don't handle mq request in userspace handler for vhost-vdpa
virtio_queue_host_notifier_read() tends to read pending event
left behind on ioeventfd in the vhost_net_stop() path, and
attempts to handle outstanding kicks from userspace vq handler.
However, in the ctrl_vq handler, virtio_net_handle_mq() has a
recursive call into virtio_net_set_status(), which may lead to
segmentation fault as shown in below stack trace:
0 0x000055f800df1780 in qdev_get_parent_bus (dev=0x0) at ../hw/core/qdev.c:376
1 0x000055f800c68ad8 in virtio_bus_device_iommu_enabled (vdev=vdev@entry=0x0)
at ../hw/virtio/virtio-bus.c:331
2 0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>) at
../hw/virtio/vhost.c:318
3 0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>,
buffer=0x7fc19bec5240, len=2052, is_write=1, access_len=2052) at
../hw/virtio/vhost.c:336
4 0x000055f800d71867 in vhost_virtqueue_stop (dev=dev@entry=0x55f8037ccc30,
vdev=vdev@entry=0x55f8044ec590, vq=0x55f8037cceb0, idx=0) at
../hw/virtio/vhost.c:1241
5 0x000055f800d7406c in vhost_dev_stop (hdev=hdev@entry=0x55f8037ccc30,
vdev=vdev@entry=0x55f8044ec590) at ../hw/virtio/vhost.c:1839
6 0x000055f800bf00a7 in vhost_net_stop_one (net=0x55f8037ccc30,
dev=0x55f8044ec590) at ../hw/net/vhost_net.c:315
7 0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590,
ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:423
8 0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>,
n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
9 0x000055f800d4e628 in virtio_net_set_status (vdev=vdev@entry=0x55f8044ec590,
status=15 '\017') at ../hw/net/virtio-net.c:370
10 0x000055f800d534d8 in virtio_net_handle_ctrl (iov_cnt=<optimized out>,
iov=<optimized out>, cmd=0 '\000', n=0x55f8044ec590) at
../hw/net/virtio-net.c:1408
11 0x000055f800d534d8 in virtio_net_handle_ctrl (vdev=0x55f8044ec590,
vq=0x7fc1a7e888d0) at ../hw/net/virtio-net.c:1452
12 0x000055f800d69f37 in virtio_queue_host_notifier_read (vq=0x7fc1a7e888d0) at
../hw/virtio/virtio.c:2331
13 0x000055f800d69f37 in virtio_queue_host_notifier_read
(n=n@entry=0x7fc1a7e8894c) at ../hw/virtio/virtio.c:3575
14 0x000055f800c688e6 in virtio_bus_cleanup_host_notifier (bus=<optimized out>,
n=n@entry=14) at ../hw/virtio/virtio-bus.c:312
15 0x000055f800d73106 in vhost_dev_disable_notifiers
(hdev=hdev@entry=0x55f8035b51b0, vdev=vdev@entry=0x55f8044ec590)
at ../../../include/hw/virtio/virtio-bus.h:35
16 0x000055f800bf00b2 in vhost_net_stop_one (net=0x55f8035b51b0,
dev=0x55f8044ec590) at ../hw/net/vhost_net.c:316
17 0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590,
ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:423
18 0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>,
n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
19 0x000055f800d4e628 in virtio_net_set_status (vdev=0x55f8044ec590, status=15
'\017') at ../hw/net/virtio-net.c:370
20 0x000055f800d6c4b2 in virtio_set_status (vdev=0x55f8044ec590, val=<optimized
out>) at ../hw/virtio/virtio.c:1945
21 0x000055f800d11d9d in vm_state_notify (running=running@entry=false,
state=state@entry=RUN_STATE_SHUTDOWN) at ../softmmu/runstate.c:333
22 0x000055f800d04e7a in do_vm_stop (state=state@entry=RUN_STATE_SHUTDOWN,
send_stop=send_stop@entry=false) at ../softmmu/cpus.c:262
23 0x000055f800d04e99 in vm_shutdown () at ../softmmu/cpus.c:280
24 0x000055f800d126af in qemu_cleanup () at ../softmmu/runstate.c:812
25 0x000055f800ad5b13 in main (argc=<optimized out>, argv=<optimized out>,
envp=<optimized out>) at ../softmmu/main.c:51
For now, temporarily disable handling MQ request from the ctrl_vq
userspace hanlder to avoid the recursive virtio_net_set_status()
call. Some rework is needed to allow changing the number of
queues without going through a full virtio_net_set_status cycle,
particularly for vhost-vdpa backend.
This patch will need to be reverted as soon as future patches of
having the change of #queues handled in userspace is merged.
Fixes: 402378407db ("vhost-vdpa: multiqueue support")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-8-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9240f34fea7fd866b950abd520e962b696a10cba
https://github.com/qemu/qemu/commit/9240f34fea7fd866b950abd520e962b696a10cba
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M contrib/vhost-user-scsi/vhost-user-scsi.c
Log Message:
-----------
vhost-user-scsi: avoid unlink(NULL) with fd passing
Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
Program conventions for vhost-user-scsi") introduced fd-passing support
as part of implementing the vhost-user backend program conventions.
When fd passing is used the UNIX domain socket path is NULL and we must
not call unlink(2).
The unlink(2) call is necessary when the listen socket, lsock, was
created successfully since that means the UNIX domain socket is visible
in the file system.
Fixes: Coverity CID 1488353
Fixes: 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend Program
conventions for vhost-user-scsi")
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220516155701.1789638-1-stefanha@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 22f6cf31739f3e791f3bf11c6cbe0c09a6ffdb48
https://github.com/qemu/qemu/commit/22f6cf31739f3e791f3bf11c6cbe0c09a6ffdb48
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
net/vmnet: add vmnet dependency and customizable option
vmnet.framework dependency is added with 'vmnet' option
to enable or disable it. Default value is 'auto'.
used vmnet features are available since macOS 11.0,
but new backend can be built and work properly with
subset of them on 10.15 too.
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 7e1143d66010c7bdfebe5f2bacb3ce5505eed9bf
https://github.com/qemu/qemu/commit/7e1143d66010c7bdfebe5f2bacb3ce5505eed9bf
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/clients.h
M net/meson.build
M net/net.c
A net/vmnet-bridged.m
A net/vmnet-common.m
A net/vmnet-host.c
A net/vmnet-shared.c
A net/vmnet_int.h
M qapi/net.json
Log Message:
-----------
net/vmnet: add vmnet backends to qapi/net
Create separate netdevs for each vmnet operating mode:
- vmnet-host
- vmnet-shared
- vmnet-bridged
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: a3a07182c7367bb5f8701c441ef877b1c4f9a94b
https://github.com/qemu/qemu/commit/a3a07182c7367bb5f8701c441ef877b1c4f9a94b
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/vmnet-common.m
M net/vmnet-shared.c
M net/vmnet_int.h
Log Message:
-----------
net/vmnet: implement shared mode (vmnet-shared)
Interaction with vmnet.framework in different modes
differs only on configuration stage, so we can create
common `send`, `receive`, etc. procedures and reuse them.
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Phillip Tennen <phillip@axleos.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 4317d015872bb6b11a0c88827f38e64bb5d5311e
https://github.com/qemu/qemu/commit/4317d015872bb6b11a0c88827f38e64bb5d5311e
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/vmnet-host.c
Log Message:
-----------
net/vmnet: implement host mode (vmnet-host)
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3eafaaf1370f772f469b59dae9c11396e2224229
https://github.com/qemu/qemu/commit/3eafaaf1370f772f469b59dae9c11396e2224229
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M net/vmnet-bridged.m
Log Message:
-----------
net/vmnet: implement bridged mode (vmnet-bridged)
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 15737be6624df555eb2aa2637467d7e869605ecc
https://github.com/qemu/qemu/commit/15737be6624df555eb2aa2637467d7e869605ecc
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qemu-options.hx
Log Message:
-----------
net/vmnet: update qemu-options.hx
Update qemu-options.hx to support vmnet networking backend.
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3bd325df87741e582d7582c2556df37f1aad800b
https://github.com/qemu/qemu/commit/3bd325df87741e582d7582c2556df37f1aad800b
Author: Vladislav Yaroshchuk <vladislav.yaroshchuk@jetbrains.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hmp-commands.hx
Log Message:
-----------
net/vmnet: update hmp-commands.hx
Update HMP for supporting vmnet.
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: ce6595f64c145e0fd0c34fd38ba371ef83233acc
https://github.com/qemu/qemu/commit/ce6595f64c145e0fd0c34fd38ba371ef83233acc
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/net/tulip.c
Log Message:
-----------
tulip: Assign default MAC address if not specified
The MAC of the tulip card is stored in the EEPROM and at startup
tulip_fill_eeprom() is called to initialize the EEPROM with the MAC
address given on the command line, e.g.:
-device tulip,mac=00:11:22:33:44:55
In case the mac address was not given on the command line,
tulip_fill_eeprom() initializes the MAC in EEPROM with 00:00:00:00:00:00
which breaks e.g. a HP-UX guest.
Fix this problem by moving qemu_macaddr_default_if_unset() a few lines
up, so that a default mac address is assigned before tulip_fill_eeprom()
initializes the EEPROM.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: aed4e1876c3ead4ce5873340fa7a9f9cc6e4bf4d
https://github.com/qemu/qemu/commit/aed4e1876c3ead4ce5873340fa7a9f9cc6e4bf4d
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
seabios-hppa: Update SeaBIOS-hppa to VERSION 5
New features and fixes in SeaBIOS for hppa/parisc:
* STI firmware now contains additional fonts built-in, which
can be selected with qemu command-line options:
-fw_cfg opt/font,string=1 - a HP 8x16 font
-fw_cfg opt/font,string=2 - a HP 6x13 font
-fw_cfg opt/font,string=3 - a HP 10x20 font
-fw_cfg opt/font,string=4 - a Linux 16x32 font
* Fixed PS/2 keyboard emulation when running in graphical mode.
This allows to type boot commands in the firmware boot menu if
qemu was started with "-boot menu=on" (and no linux kernel was
given on the qemu command line).
* Fix firmware rendenzvous code to clear all pending external intrrupts
before entering the waiting loop.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 811d0d7ec5a9b89999ff4650c56084e066733551
https://github.com/qemu/qemu/commit/811d0d7ec5a9b89999ff4650c56084e066733551
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Introduce constant for max cursor size
Add the constant NGLE_MAX_SPRITE_SIZE which defines the currently
maximum supported cursor size.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 70886153a72e1ee279e41d19175dd61776ff2da5
https://github.com/qemu/qemu/commit/70886153a72e1ee279e41d19175dd61776ff2da5
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Use human-readable variable names instead of reg_xxx
Convert the variable names of some registers to human-readable and
understandable names.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 6cf53d31ef56c1e0f996e1a74354317ebd01642c
https://github.com/qemu/qemu/commit/6cf53d31ef56c1e0f996e1a74354317ebd01642c
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Fix vertical X11 cursor position in HP-UX
Drop the hard-coded value of 1146 lines which seems to work with HP-UX
11, but not with HP-UX 10. Instead encode the screen height in byte 0 of
active_lines_low and byte 3 of misc_video as it's expected by the Xorg
X11 graphics driver.
This potentially allows for higher vertical screen resolutions than
1280x1024 with X11.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 786ea185b548a9d62217dc9c94f81cf6e52b2c67
https://github.com/qemu/qemu/commit/786ea185b548a9d62217dc9c94f81cf6e52b2c67
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Allow to turn cursor on or off
Bit 0x80 in the cursor_cntrl register specifies if the cursor
should be visible. Prevent rendering the cursor if it's invisible.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: fdb335b1efaada3165fe1bbc8234a5ea8a96bcb9
https://github.com/qemu/qemu/commit/fdb335b1efaada3165fe1bbc8234a5ea8a96bcb9
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Emulate screen blanking
The misc_video and misc_ctrl registers control the visibility of the
screen. Start with the screen turned on, and hide or show the screen
based on the control registers.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 741128acc4721a1e002b482af13fb1f1418c46d8
https://github.com/qemu/qemu/commit/741128acc4721a1e002b482af13fb1f1418c46d8
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/artist.c
Log Message:
-----------
artist: Fix X cursor position calculation in X11
The X cursor postion can be calculated based on the backporch and
interleave values. In the emulation we ignore the HP-UX settings for
backporch and use instead twice the size of the emulated cursor. With
those changes the X-position of the graphics cursor is now finally
working correctly on HP-UX 10 and HP-UX 11.
Based on coding in Xorg X11R6.6
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 81c08825350b8aad6fcbad92bf04092dc4fa632c
https://github.com/qemu/qemu/commit/81c08825350b8aad6fcbad92bf04092dc4fa632c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Postpone interpretation of stage 2 descriptor attribute bits
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access. In QEMU we implement this
by having get_phys_addr() fill in an ARMCacheAttrs struct, and we
convert both the stage 1 and stage 2 attribute bit formats to the
same encoding (an 8-bit attribute value matching the MAIR_EL1 fields,
plus a 2-bit shareability value).
The new FEAT_S2FWB feature allows the guest to enable a different
interpretation of the attribute bits in the stage 2 descriptors.
These bits can now be used to control details of how the stage 1 and
2 attributes should be combined (for instance they can say "always
use the stage 1 attributes" or "ignore the stage 1 attributes and
always be Device memory"). This means we need to pass the raw bit
information for stage 2 down to the function which combines the stage
1 and stage 2 information.
Add a field to ARMCacheAttrs that indicates whether the attrs field
should be interpreted as MAIR format, or as the raw stage 2 attribute
bits from the descriptor, and store the appropriate values when
filling in cacheattrs.
We only need to interpret the attrs field in a few places:
* in do_ats_write(), where we know to expect a MAIR value
(there is no ATS instruction to do a stage-2-only walk)
* in S1_ptw_translate(), where we want to know whether the
combined S1 + S2 attributes indicate Device memory that
should provoke a fault
* in combine_cacheattrs(), which does the S1 + S2 combining
Update those places accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-2-peter.maydell@linaro.org
Commit: 60f372e39314906dcd22984f9e32dc9d9f0dc18c
https://github.com/qemu/qemu/commit/60f372e39314906dcd22984f9e32dc9d9f0dc18c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
Factor out the part of combine_cacheattrs() that is specific to
handling HCR_EL2.FWB == 0. This is the part where we combine the
memory type and cacheability attributes.
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
logic remains in combine_cacheattrs() because it holds regardless
(this is the equivalent of the pseudocode EffectiveShareability()
function).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
Commit: 150dcda7084eeaebc58dcc81e9f6de559436a8c0
https://github.com/qemu/qemu/commit/150dcda7084eeaebc58dcc81e9f6de559436a8c0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement FEAT_S2FWB
Implement the handling of FEAT_S2FWB; the meat of this is in the new
combined_attrs_fwb() function which combines S1 and S2 attributes
when HCR_EL2.FWB is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
Commit: fe02aff983862276344559c08cf8588ab057a7ec
https://github.com/qemu/qemu/commit/fe02aff983862276344559c08cf8588ab057a7ec
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_S2FWB for -cpu max
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
Commit: ec1c9570ab0eef72ece00a326f336c388c0cbebc
https://github.com/qemu/qemu/commit/ec1c9570ab0eef72ece00a326f336c388c0cbebc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FEAT_IDST
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
read accesses to the feature ID space should report a syndrome code
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
The feature ID space is defined to be:
op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7}
In our implementation we might return the EC_UNCATEGORIZED syndrome
value for a system register access in four cases:
* no reginfo struct in the hashtable
* cp_access_ok() fails (ie ri->access doesn't permit the access)
* ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime
* ri->type includes ARM_CP_RAISES_EXC, and the readfn raises
an UNDEF exception at runtime
We have very few regdefs that set ARM_CP_RAISES_EXC, and none of
them are in the feature ID space. (In the unlikely event that any
are added in future they would need to take care of setting the
correct syndrome themselves.) This patch deals with the other
three cases, and enables FEAT_IDST for AArch64 -cpu max.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
Commit: ab44f5b37478a0e495dc5d4095159b5ed939d879
https://github.com/qemu/qemu/commit/ab44f5b37478a0e495dc5d4095159b5ed939d879
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-a64.h
Log Message:
-----------
target/arm: Drop unsupported_encoding() macro
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using something we
hadn't yet implemented. Now we completely cover the A64 instruction
set it is barely used. The only remaining uses are for five
instructions whose semantics are "UNDEF, unless being run under
external halting debug":
* HLT (when not being used for semihosting)
* DCPSR1, DCPS2, DCPS3
* DRPS
QEMU doesn't implement external halting debug, so for us the UNDEF is
the architecturally correct behaviour (because it's not possible to
execute these instructions with halting debug enabled). The
LOG_UNIMP doesn't serve a useful purpose; replace these uses of
unsupported_encoding() with unallocated_encoding(), and delete the
macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
Commit: a5228b15b3a5fa9c48814a55b809cdc199e7e8db
https://github.com/qemu/qemu/commit/a5228b15b3a5fa9c48814a55b809cdc199e7e8db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
We allow a GICv3 to be connected to any CPU, but we don't do anything
to handle the case where the CPU type doesn't in hardware have a
GICv3 CPU interface and so the various GIC configuration fields
(gic_num_lrs, vprebits, vpribits) are not specified.
The current behaviour is that we will add the EL1 CPU interface
registers, but will not put in the EL2 CPU interface registers, even
if the CPU has EL2, which will leave the GIC in a broken state and
probably result in the guest crashing as it tries to set it up. This
only affects the virt board when using the cortex-a15 or cortex-a7
CPU types (both 32-bit) with -machine gic-version=3 (or 'max')
and -machine virtualization=on.
Instead of failing to set up the EL2 registers, if the CPU doesn't
define the GIC configuration set it to a reasonable default, matching
the standard configuration for most Arm CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
Commit: 999243d3b20c135b73c81e5a9a85a4b60fc17150
https://github.com/qemu/qemu/commit/999243d3b20c135b73c81e5a9a85a4b60fc17150
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
Commit: 05ff42b3e57cb180919ea1a627850fbf55f074a0
https://github.com/qemu/qemu/commit/05ff42b3e57cb180919ea1a627850fbf55f074a0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
emulated GICv3 supports. We're currently using this also as the
value we reset the KVM GICv3 ICC_BPR registers to, but this is only
right by accident.
We want to make the emulated GICv3 use a configurable number of
priority bits, which means that GIC_MIN_BPR will no longer be a
constant. Replace the uses in the KVM reset code with literal 0,
plus a constant explaining why this is reasonable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
Commit: 8e3b3e06e8d8b929be21999b7e62581051a1fe57
https://github.com/qemu/qemu/commit/8e3b3e06e8d8b929be21999b7e62581051a1fe57
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Support configurable number of physical priority bits
The GICv3 code has always supported a configurable number of virtual
priority and preemption bits, but our implementation currently
hardcodes the number of physical priority bits at 8. This is not
what most hardware implementations provide; for instance the
Cortex-A53 provides only 5 bits of physical priority.
Make the number of physical priority/preemption bits driven by fields
in the GICv3CPUState, the way that we already do for virtual
priority/preemption bits. We set cs->pribits to 8, so there is no
behavioural change in this commit. A following commit will add the
machinery for CPUs to set this to the correct value for their
implementation.
Note that changing the number of priority bits would be a migration
compatibility break, because the semantics of the icc_apr[][] array
changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org
Commit: 5176bd2d9e3b6712ec44a01cd2624a11b04903b9
https://github.com/qemu/qemu/commit/5176bd2d9e3b6712ec44a01cd2624a11b04903b9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/machine.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits. Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is enabled for 7.0 and earlier versioned board
models to retain the legacy "always use 8 bits" behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
Commit: 7c26ba1a9b81b13dc586d2e5f7fde4043d6a3ba0
https://github.com/qemu/qemu/commit/7c26ba1a9b81b13dc586d2e5f7fde4043d6a3ba0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Provide ich_num_aprs()
We previously open-coded the expression for the number of virtual APR
registers and the assertion that it was not going to cause us to
overflow the cs->ich_apr[] array. Factor this out into a new
ich_num_aprs() function, for consistency with the icc_num_aprs()
function we just added for the physical APR handling.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
Commit: 6dc7877a5edd2faf0d4b3fdf5b55ef162057a986
https://github.com/qemu/qemu/commit/6dc7877a5edd2faf0d4b3fdf5b55ef162057a986
Author: Chris Howard <cvz185@web.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
Fix aarch64 debug register names.
Give all the debug registers their correct names including the
index, rather than having multiple registers all with the
same name string, which is confusing when viewed over the
gdbstub interface.
Signed-off-by: CHRIS HOWARD <cvz185@web.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c69c896c49aca0c3452349b7be7cf5fe8bb3a75
https://github.com/qemu/qemu/commit/2c69c896c49aca0c3452349b7be7cf5fe8bb3a75
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/adc/zynq-xadc.c
M include/hw/adc/zynq-xadc.h
Log Message:
-----------
hw/adc/zynq-xadc: Use qemu_irq typedef
Except hw/core/irq.c which implements the forward-declared opaque
qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
using the typedef. Fix this single exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20220509202035.50335-1-philippe.mathieu.daude@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 65ca016f2b68bd1cc99f447d886830aef5ede29d
https://github.com/qemu/qemu/commit/65ca016f2b68bd1cc99f447d886830aef5ede29d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm/helper.c: Delete stray obsolete comment
In commit 88ce6c6ee85d we switched from directly fishing the number
of breakpoints and watchpoints out of the ID register fields to
abstracting out functions to do this job, but we forgot to delete the
now-obsolete comment in define_debug_regs() about the relation
between the ID field value and the actual number of breakpoints and
watchpoints. Delete the obsolete comment.
Reported-by: CHRIS HOWARD <cvz185@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131801.4082712-1-peter.maydell@linaro.org
Commit: e5e83a2099dffce321875bf0ee35fb526cb43af6
https://github.com/qemu/qemu/commit/e5e83a2099dffce321875bf0ee35fb526cb43af6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Make number of counters in PMCR follow the CPU
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.
This means that we now supply 6 counters instead of 4 for:
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
Cortex-A76, Neoverse-N1, '-cpu max'
This CPU goes from 4 to 8 counters:
A64FX
These CPUs remain with 4 counters:
Cortex-A7, Cortex-A8
This CPU goes down from 4 to 3 counters:
Cortex-R5
Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset. This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.
This change was originally landed in commit f7fb73b8cdd3f7 (during
the 6.0 release cycle) but was then reverted by commit
21c2dd77a6aa517 before that release because it did not work with KVM.
This version fixes that by creating the scratch vCPU in
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
if the vCPU has a PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Added the correct value for a64fx]
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
Commit: a383017d0330efa9ae728b1cd14cdaeacb89e0c7
https://github.com/qemu/qemu/commit/a383017d0330efa9ae728b1cd14cdaeacb89e0c7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Fix incorrect non-secure flash dtb node name
In the virt board with secure=on we put two nodes in the dtb
for flash devices: one for the secure-only flash, and one
for the non-secure flash. We get the reg properties for these
correct, but in the DT node name, which by convention includes
the base address of devices, we used the wrong address. Fix it.
Spotted by dtc, which will complain
Warning (unique_unit_address): /flash@0: duplicate unit-address (also used in
node /secflash@0)
if you dump the dtb from QEMU with -machine dumpdtb=file.dtb
and then decompile it with dtc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131316.4081539-2-peter.maydell@linaro.org
Commit: 0f4e634092c9220496b8668efb00c5ad647425c3
https://github.com/qemu/qemu/commit/0f4e634092c9220496b8668efb00c5ad647425c3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
The virt board generates a gpio-keys node in the dtb, but it
incorrectly gives this node #size-cells and #address-cells
properties. If you dump the dtb with 'machine dumpdtb=file.dtb'
and run it through dtc, dtc will warn about this:
Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
Remove the bogus properties.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131316.4081539-3-peter.maydell@linaro.org
Commit: 6165de325cd2ef11e70c20217ce9ad3b34fbf6e5
https://github.com/qemu/qemu/commit/6165de325cd2ef11e70c20217ce9ad3b34fbf6e5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/musicpal.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx_csu_dma.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf5208.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/net/fsl_etsec/etsec.c
M hw/net/lan9118.c
M hw/rtc/exynos4210_rtc.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/altera_timer.c
M hw/timer/arm_timer.c
M hw/timer/digic-timer.c
M hw/timer/etraxfs_timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/grlib_gptimer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/mss-timer.c
M hw/timer/sh_timer.c
M hw/timer/slavio_timer.c
M hw/timer/xilinx_timer.c
M include/hw/ptimer.h
M tests/unit/ptimer-test.c
Log Message:
-----------
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
The traditional ptimer behaviour includes a collection of weird edge
case behaviours. In 2016 we improved the ptimer implementation to
fix these and generally make the behaviour more flexible, with
ptimers opting in to the new behaviour by passing an appropriate set
of policy flags to ptimer_init(). For backwards-compatibility, we
defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old
weird behaviour.
This turns out to be a poor choice of name, because people writing
new devices which use ptimers are misled into thinking that the
default is probably a sensible choice of flags, when in fact it is
almost always not what you want. Rename PTIMER_POLICY_DEFAULT to
PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that
new devices should not be using it.
The code-change part of this commit was produced by
sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l
PTIMER_POLICY_DEFAULT)
with the exception of a test name string change in
tests/unit/ptimer-test.c which was added manually.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
Commit: c6bc2e27b30a5e9a1638817dce3c582ce444c62d
https://github.com/qemu/qemu/commit/c6bc2e27b30a5e9a1638817dce3c582ce444c62d
Author: Florian Lugou <florian.lugou@provenrun.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix PAuth keys access checks for disabled SEL2
As per the description of the HCR_EL2.APK field in the ARMv8 ARM,
Pointer Authentication keys accesses should only be trapped to Secure
EL2 if it is enabled.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517145242.1215271-1-florian.lugou@provenrun.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0fdf71dd35fbd1398ace218704ea0309192f64c8
https://github.com/qemu/qemu/commit/0fdf71dd35fbd1398ace218704ea0309192f64c8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable FEAT_HCX for -cpu max
This feature adds a new register, HCRX_EL2, which controls
many of the newer AArch64 features. So far the register is
effectively RES0, because none of the new features are done.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517054850.177016-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f70016f60a3c37c55b643734d57eec5c1751c131
https://github.com/qemu/qemu/commit/f70016f60a3c37c55b643734d57eec5c1751c131
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/boot.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
We had a few CPTR_* bits defined, but missed quite a few.
Complete all of the fields up to ARMv9.2.
Use FIELD_EX64 instead of manual extract32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517054850.177016-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e882f40e2b36ad673c04ec59c4faba314bec78a
https://github.com/qemu/qemu/commit/9e882f40e2b36ad673c04ec59c4faba314bec78a
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/static_checks.yml
Log Message:
-----------
gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobs
The 'check-patch' and 'check-dco' jobs only need Python and git for
checking the patches, so it's not really necessary to use a container
here that has all the other build dependencies installed. By using a
lightweight Alpine container, we can improve the runtime here quite a
bit, cutting it down from ca. 1:30 minutes to ca. 45 seconds.
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220516082310.33876-1-thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 3f182dde9aabd306d39fe1ecbc9bfd7290228c32
https://github.com/qemu/qemu/commit/3f182dde9aabd306d39fe1ecbc9bfd7290228c32
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/containers.yml
M .gitlab-ci.d/custom-runners/ubuntu-20.04-aarch32.yml
M .gitlab-ci.d/custom-runners/ubuntu-20.04-aarch64.yml
M scripts/ci/setup/build-environment.yml
R tests/docker/dockerfiles/ubuntu1804.docker
M tests/lcitool/refresh
Log Message:
-----------
Remove Ubuntu 18.04 container support from the repository
According to our "Supported build platforms" policy, we now do not support
Ubuntu 18.04 anymore. Remove the related container files and entries from
our CI.
Message-Id: <20220516115912.120951-1-thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8944b82ed57d2c620ab30a3f19a82f511b05be62
https://github.com/qemu/qemu/commit/8944b82ed57d2c620ab30a3f19a82f511b05be62
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: fix registration of ABRT handler for QEMU cleanup
qtest_init registers a hook to cleanup the running QEMU process
should g_assert() fire before qtest_quit is called. When the first
hook is registered, it is supposed to triggere registration of the
SIGABRT handler. Unfortunately the logic in hook_list_is_empty is
inverted, so the SIGABRT handler never gets registered, unless
2 or more QEMU processes are run concurrently. This caused qtest
to leak QEMU processes anytime g_assert triggers.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220513154906.206715-2-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 3a9ce9c4e8a92f0c9a2e5218b12e259ac29df581
https://github.com/qemu/qemu/commit/3a9ce9c4e8a92f0c9a2e5218b12e259ac29df581
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: use prctl(PR_SET_PDEATHSIG) as fallback to kill QEMU
Although we register a ABRT handler to kill off QEMU when g_assert()
triggers, we want an extra safety net. The QEMU process might be
non-functional and thus not have responded to SIGTERM. The test script
might also have crashed with SEGV, in which case the cleanup handlers
won't ever run.
Using the Linux specific prctl(PR_SET_PDEATHSIG) syscall, we
can ensure that QEMU gets sent SIGKILL as soon as the controlling
qtest exits, if nothing else has correctly told it to quit.
Note, technically the death signal is sent when the *thread* that
called fork() exits. IOW, if you are calling qtest_init() in one
thread, letting that thread exit, and then expecting to run
qtest_quit() in a different thread, things are not going to work
out. Fortunately that is not a scenario that exists in qtests,
as pairs of qtest_init and qtest_quit are always called from the
same thread.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220513154906.206715-3-berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 6b46ae6b64a861597b8db13905498f266d5689ed
https://github.com/qemu/qemu/commit/6b46ae6b64a861597b8db13905498f266d5689ed
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M docs/about/build-platforms.rst
M include/qemu/osdep.h
Log Message:
-----------
docs/about: Update the support statement for Windows
Our support statement for Windows currently talks about "Vista / Server
2008" - which is related to the API of Windows, and this is not easy
to understand for the non-technical users. Additionally, glib sets the
_WIN32_WINNT macro to 0x0601 already, which indicates the Windows 7 API,
so QEMU effectively depends on the Windows 7 API, too.
Thus let's bump the _WIN32_WINNT setting in QEMU to the same level as
glib uses and adjust our support statement in the documentation to
something similar that we're using for Linux and the *BSD systems
(i.e. only the two most recent versions), which should hopefully be
easier to understand for the users now.
And since we're nowadays also compile-testing QEMU with MSYS2 on Windows
itself, I think we could mention this build environment here, too.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/880
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20220513063958.1181443-1-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: eca2c89284d0941b42a84e50c1c1ef01f1f00eed
https://github.com/qemu/qemu/commit/eca2c89284d0941b42a84e50c1c1ef01f1f00eed
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/vm/netbsd
M tests/vm/openbsd
Log Message:
-----------
tests/vm: Add capstone to the NetBSD and OpenBSD VMs
The Capstone library that is shipped with NetBSD and OpenBSD works
fine when compiling QEMU, so let's enable this in our build-test
VMs to get a little bit more build-test coverage.
Message-Id: <20220516145823.148450-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a6e1e13dabc5a0a6f2d040245e6590593dc66338
https://github.com/qemu/qemu/commit/a6e1e13dabc5a0a6f2d040245e6590593dc66338
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M meson.build
Log Message:
-----------
capstone: Allow version 3.0.5 again
According to
https://lore.kernel.org/qemu-devel/20200921174118.39352-1-richard.henderson@linaro.org/
there was an issue with Capstone 3.0.4 from Ubuntu 18, which was the reason
for bumping our minimum Capstone requirement to version 4.0. And indeed,
compiling with that version 3.0.4 from Ubuntu 18.04 still fails (after
allowing it with a hack in meson.build). But now that we've dropped support
for Ubuntu 18.04, that issue is not relevant anymore. Compiling with Capstone
version 3.0.5 (e.g. used in Ubuntu 20.04) seems to work fine, so let's allow
that version again.
Message-Id: <20220516145823.148450-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 71a6b7009b79880795af257e34a39f884edf15e5
https://github.com/qemu/qemu/commit/71a6b7009b79880795af257e34a39f884edf15e5
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/windows.yml
M .gitmodules
R capstone
M configure
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
capstone: Remove the capstone submodule
Now that we allow compiling with Capstone v3.0.5 again, all our supported
build hosts should provide at least this version of the disassembler
library, so we do not need to ship this as a submodule anymore.
Message-Id: <20220516145823.148450-4-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: fe5e2935896f19a0b17259cb5c32a6f1e3bb5164
https://github.com/qemu/qemu/commit/fe5e2935896f19a0b17259cb5c32a6f1e3bb5164
Author: Dylan Reid <dylan@rivosinc.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix VS mode hypervisor CSR access
VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.
Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.
Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0a8a8b98c89beaf2e9ce78cbac3393767d8d847f
https://github.com/qemu/qemu/commit/0a8a8b98c89beaf2e9ce78cbac3393767d8d847f
Author: eopXD <eop.chen@sifive.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Fix early exit condition for whole register load/store
Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 757d8b2159c8ca1795b09dd3618dddb7374f88e5
https://github.com/qemu/qemu/commit/757d8b2159c8ca1795b09dd3618dddb7374f88e5
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Pass correct hartid while updating mtimecmp
timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.
Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 619382a6e72acd08fdc1ac35f381b751aeb38abc
https://github.com/qemu/qemu/commit/619382a6e72acd08fdc1ac35f381b751aeb38abc
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Move Zhinx* extensions on ISA string
This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f25c3f31e41a1117fcdd5efe511b4f3c1ac9baae
https://github.com/qemu/qemu/commit/f25c3f31e41a1117fcdd5efe511b4f3c1ac9baae
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add short-isa-string option
Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.
For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier) with FPU support caused a kernel panic.
Operating Systems which short-isa-string might be helpful:
1. Linux (5.17 or earlier)
2. FreeBSD (at least 14.0-CURRENT)
3. OpenBSD (at least current development version)
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 05cca61e079dbf418e4e7f00256625c0141c7ea5
https://github.com/qemu/qemu/commit/05cca61e079dbf418e4e7f00256625c0141c7ea5
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/riscv/spike.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Make CPU config error handling generous (virt/spike)
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
virt/spike machines. It now just prints error message and quits (without
coredumps and aborts).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 62657d44823b3cc07df66476ed8626a41a22c2a0
https://github.com/qemu/qemu/commit/62657d44823b3cc07df66476ed8626a41a22c2a0
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines. It now just prints error message and
quits (without coredumps and aborts).
This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 37e80f819aaf7ccee40f99b9b66c01502db1b0b5
https://github.com/qemu/qemu/commit/37e80f819aaf7ccee40f99b9b66c01502db1b0b5
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix coding style on "G" expansion
Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id:
<91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 42d33407c9dc4065894d66abb5160d1b0412cf09
https://github.com/qemu/qemu/commit/42d33407c9dc4065894d66abb5160d1b0412cf09
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Disable "G" by default
Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G". Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 99b3a06ab3eef5d57d6e6f7dd5aacb2cb62843d5
https://github.com/qemu/qemu/commit/99b3a06ab3eef5d57d6e6f7dd5aacb2cb62843d5
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Change "G" expansion
On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fec08831a4dc2737c5c2330848c19e69694e8f4e
https://github.com/qemu/qemu/commit/fec08831a4dc2737c5c2330848c19e69694e8f4e
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: FP extension requirements
QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.
This commit adds certain checks for consistent FP arithmetic:
- F requires Zicsr
- Zfinx requires Zicsr
- Zfh/Zfhmin require F
- D requires F
- V requires D
Because F/D/Zicsr are enabled by default (and an error will not occur unless
we manually disable one or more of prerequisites), this commit just enforces
the user to give consistent combinations.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 217c761c2809fcc4f0691a9d2d05280e2b2844f8
https://github.com/qemu/qemu/commit/217c761c2809fcc4f0691a9d2d05280e2b2844f8
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Move/refactor ISA extension checks
We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5eecc1ba0e6745fd57b4f32d937ec726c18d3e83
https://github.com/qemu/qemu/commit/5eecc1ba0e6745fd57b4f32d937ec726c18d3e83
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/vfio/pci-quirks.c
Log Message:
-----------
hw/vfio/pci-quirks: Resolve redundant property getters
The QOM API already provides getters for uint64 and uint32 values, so reuse
them.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301225220.239065-2-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9a9147383efe92a4bea8e412b81abbaae745b42e
https://github.com/qemu/qemu/commit/9a9147383efe92a4bea8e412b81abbaae745b42e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv/sifive_u: Resolve redundant property accessors
The QOM API already provides accessors for uint32 values, so reuse them.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220301225220.239065-3-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 967044a488557c100f4735d27a60a1abd56c491d
https://github.com/qemu/qemu/commit/967044a488557c100f4735d27a60a1abd56c491d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7ac2f050ef435befe8841a18674cab6738959075
https://github.com/qemu/qemu/commit/7ac2f050ef435befe8841a18674cab6738959075
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix typo of mimpid cpu option
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3d483e5169859be5255aa377e5a2c13fd19dc3d5
https://github.com/qemu/qemu/commit/3d483e5169859be5255aa377e5a2c13fd19dc3d5
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix csr number based privilege checking
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bac4e6f1a24f9aad401e91ce99f2716a0418267c
https://github.com/qemu/qemu/commit/bac4e6f1a24f9aad401e91ce99f2716a0418267c
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3656586a502ddaab0dcb8f8d8dfe8ed2ddfb6d19
https://github.com/qemu/qemu/commit/3656586a502ddaab0dcb8f8d8dfe8ed2ddfb6d19
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.
In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM or hstatus.VTVM).
We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 69cbdd570ac53b2effa3ee7e1429cd6ae3a7321a
https://github.com/qemu/qemu/commit/69cbdd570ac53b2effa3ee7e1429cd6ae3a7321a
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Fix interrupt parent for dynamic platform devices
When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.
In case of multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.
Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
platform FDT entries")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f197cc2cc9981f578a70b3e3ec59fd47e071fc65
https://github.com/qemu/qemu/commit/f197cc2cc9981f578a70b3e3ec59fd47e071fc65
Author: Hongren (Zenithal) Zheng <i@zenithal.me>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add zicsr/zifencei to isa_string
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 14249b8689f5c3b12222752e8d9ca4062dee59f1
https://github.com/qemu/qemu/commit/14249b8689f5c3b12222752e8d9ca4062dee59f1
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/uboot_image.h
Log Message:
-----------
hw/core: Sync uboot_image.h from U-Boot v2022.01
Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7c7b7c06ca44397e92c0e8333c9dc6a11c47cb6a
https://github.com/qemu/qemu/commit/7c7b7c06ca44397e92c0e8333c9dc6a11c47cb6a
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/core/loader.c
Log Message:
-----------
hw/core: loader: Set is_linux to true for VxWorks uImage
VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82e24ab052eb47e120cfd4b10d37b41ab219e73f
https://github.com/qemu/qemu/commit/82e24ab052eb47e120cfd4b10d37b41ab219e73f
Author: luzhipeng <luzhipeng@cestc.cn>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/commands-posix.c
M qga/commands-win32.c
M qga/qapi-schema.json
Log Message:
-----------
qga: add guest-get-diskstats command for Linux guests
Add a new 'guest-get-diskstats' command for report disk io statistics
for Linux guests. This can be useful for getting io flow or handling
IO fault, no need to enter guests.
Signed-off-by: luzhipeng <luzhipeng@cestc.cn>
Message-Id: <20220520021935.676-1-luzhipeng@cestc.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 4c2a939bd31aa4e8dde592907316d8978e652ffa
https://github.com/qemu/qemu/commit/4c2a939bd31aa4e8dde592907316d8978e652ffa
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/main.c
Log Message:
-----------
trivial: qga: Log version on start
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220523191644.823726-2-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 2b8024f1d21817093e889e4fc7848f06d774fb64
https://github.com/qemu/qemu/commit/2b8024f1d21817093e889e4fc7848f06d774fb64
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/docker/dockerfiles/fedora-win32-cross.docker
M tests/docker/dockerfiles/fedora-win64-cross.docker
Log Message:
-----------
tests: Bump Fedora image version for cross-compilation
There are 2 reason for the bump:
- Fedora 33 is not supported anymore
- Some changes in the guest agent required updates of
mingw-headers
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220525085953.940116-2-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: a8ade15b48082b7e8abe3f2666cf0fefe2ed867f
https://github.com/qemu/qemu/commit/a8ade15b48082b7e8abe3f2666cf0fefe2ed867f
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/commands-win32.c
Log Message:
-----------
qga-win32: Add support for NVME bus type
Bus type spaces (Indicates a storage spaces bus) is not
supported, so return it as unknown.
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220524154344.869638-2-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 2b37aba0008f90b17ff5f12b4a65970a096b33e3
https://github.com/qemu/qemu/commit/2b37aba0008f90b17ff5f12b4a65970a096b33e3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/elfload.c
M linux-user/linuxload.c
M linux-user/main.c
M linux-user/qemu.h
M semihosting/arm-compat-semi.c
Log Message:
-----------
linux-user: Clean up arg_start/arg_end confusion
We had two sets of variables: arg_start/arg_end, and
arg_strings/env_strings. In linuxload.c, we set the
first pair to the bounds of the argv strings, but in
elfload.c, we set the first pair to the bounds of the
argv pointers and the second pair to the bounds of
the argv strings.
Remove arg_start/arg_end, replacing them with the standard
argc/argv/envc/envp values. Retain arg_strings/env_strings
with the meaning we were using in elfload.c.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/714
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220427025129.160184-1-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: edef46ae47068304a0a3254dfec3b72d60daf9f2
https://github.com/qemu/qemu/commit/edef46ae47068304a0a3254dfec3b72d60daf9f2
Author: Fabrice Fontaine <fontaine.fabrice@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/syscall.c: fix build without RLIMIT_RTTIME
RLIMIT_RTTIME is not provided by uclibc-ng or by musl prior to version
1.2.0 and
https://github.com/bminor/musl/commit/2507e7f5312e79620f6337935d0a6c9045ccba09
resulting in the following build failure since
https://git.qemu.org/?p=qemu.git;a=commit;h=244fd08323088db73590ff2317dfe86f810b51d7:
../linux-user/syscall.c: In function 'target_to_host_resource':
../linux-user/syscall.c:1057:16: error: 'RLIMIT_RTTIME' undeclared (first use
in this function); did you mean 'RLIMIT_NOFILE'?
1057 | return RLIMIT_RTTIME;
| ^~~~~~~~~~~~~
| RLIMIT_NOFILE
Fixes:
-
http://autobuild.buildroot.org/results/22d3b584b704613d030e1ea9e6b709b713e4cc26
Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220523105239.1499162-1-fontaine.fabrice@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 1c94cc584b58d3aa1c5aad20dfe30e96df32d4c0
https://github.com/qemu/qemu/commit/1c94cc584b58d3aa1c5aad20dfe30e96df32d4c0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Remove pointless non-const CPUArchState cast
fill_thread_info() takes a pointer to const.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220509205728.51912-2-philippe.mathieu.daude@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 5a7338423856edd5622a72e13594de312cd54df8
https://github.com/qemu/qemu/commit/5a7338423856edd5622a72e13594de312cd54df8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/strace.c
M linux-user/strace.h
M linux-user/syscall.c
M linux-user/uname.c
M linux-user/uname.h
M linux-user/user-internals.h
Log Message:
-----------
linux-user: Have do_syscall() use CPUArchState* instead of void*
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220509205728.51912-3-philippe.mathieu.daude@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 8286bccee51e3475b5bd7ebb913bb689bc268cfc
https://github.com/qemu/qemu/commit/8286bccee51e3475b5bd7ebb913bb689bc268cfc
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/syscall.c
M linux-user/uname.c
M linux-user/user-internals.h
Log Message:
-----------
linux-user: Remove pointless CPU{ARCH}State casts
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220509205728.51912-4-philippe.mathieu.daude@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 1190a27db64d3c24ef4a0a16273878abd4b42efe
https://github.com/qemu/qemu/commit/1190a27db64d3c24ef4a0a16273878abd4b42efe
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/s390x/signal.c
Log Message:
-----------
linux-user/s390x: Fix unwinding from signal handlers
Commit 31330e6cecfd ("linux-user/s390x: Implement setup_sigtramp")
removed an unused field from rt_sigframe, disturbing offsets of other
fields and breaking unwinding from signal handlers (e.g. libgcc's
s390_fallback_frame() relies on this struct having a specific layout).
Restore the field and add a comment.
Reported-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Fixes: 31330e6cecfd ("linux-user/s390x: Implement setup_sigtramp")
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220503225157.1696774-2-iii@linux.ibm.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 2ea1fce427f3458edb5d41154f8f18b238dc22dd
https://github.com/qemu/qemu/commit/2ea1fce427f3458edb5d41154f8f18b238dc22dd
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/tcg/s390x/signals-s390x.c
Log Message:
-----------
tests/tcg/s390x: Test unwinding from signal handlers
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20220503225157.1696774-3-iii@linux.ibm.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 4752cfcff4c683255c59e38c47bf697074eb5737
https://github.com/qemu/qemu/commit/4752cfcff4c683255c59e38c47bf697074eb5737
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/include/host/s390/host-signal.h
Log Message:
-----------
linux-user/host/s390: Treat EX and EXRL as writes
clang-built s390x branch-relative-long test fails on clang-built s390x
QEMU due to the following sequence of events:
- The test zeroes out a code page, clang generates exrl+xc for this.
- do_helper_xc() is called. Clang generates exrl+xc there as well.
- Since there already exists a TB for the code in question, its page is
read-only and SIGSEGV is raised.
- host_signal_handler() calls host_signal_write() and the latter does
not recognize exrl as a write. Therefore page_unprotect() is not
called and the signal is forwarded to the test.
Fix by treating EXRL (and EX, just in case) as writes. There may be
false positives, but they will lead only to an extra page_unprotect()
call.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504114819.1729737-1-iii@linux.ibm.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 9569eaa3f76f4da55be240c2cc77d7254883f52e
https://github.com/qemu/qemu/commit/9569eaa3f76f4da55be240c2cc77d7254883f52e
Author: Liu Yiding <liuyd.fnst@fujitsu.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/tools/virtiofsd.rst
Log Message:
-----------
docs: Correct the default thread-pool-size
Refer to 26ec190964 virtiofsd: Do not use a thread pool by default
Signed-off-by: Liu Yiding <liuyd.fnst@fujitsu.com>
Acked-by: Vivek Goyal <vgoyal@redhat.com>
Message-id: 20220413042054.1484640-1-liuyd.fnst@fujitsu.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 7ec3fa4d4697570ddcc7d31e846fb614910ff357
https://github.com/qemu/qemu/commit/7ec3fa4d4697570ddcc7d31e846fb614910ff357
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: add minibmc section in aspeed document
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 58020c697f256f913cc59e76be89891232737114
https://github.com/qemu/qemu/commit/58020c697f256f913cc59e76be89891232737114
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add fby35 machine type
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace
i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB.
Reference images can be found in Facebook OpenBMC Github Release assets
as "fby35.mtd". [3]
You can boot the reference images as follows (fby35 uses dual-flash):
qemu-system-arm -machine fby35-bmc \
-drive file=fby35.mtd,format=raw,if=mtd \
-drive file=fby35.mtd,format=raw,if=mtd \
-nographic
[1]
https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts
[2]
https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh
[3] https://github.com/facebook/openbmc/releases
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220503225925.1798324-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 570d79ed70d8257dae851acaf33457db7f766e5e
https://github.com/qemu/qemu/commit/570d79ed70d8257dae851acaf33457db7f766e5e
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: Add fby35 board
Add fby35 to the list of Aspeed boards.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220506193354.990532-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fe283637da72718e23317e6b127ad24644291a6a
https://github.com/qemu/qemu/commit/fe283637da72718e23317e6b127ad24644291a6a
Author: Iris Chen <irischenlj@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/block/m25p80.c
M tests/qtest/aspeed_gpio-test.c
M tests/qtest/aspeed_smc-test.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
hw: m25p80: allow write_enable latch get/set
The write_enable latch property is not currently exposed.
This commit makes it a modifiable property.
Signed-off-by: Iris Chen <irischenlj@fb.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220513055022.951759-1-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6ed411e7e7727d66a847485e202d008633d2a9ac
https://github.com/qemu/qemu/commit/6ed411e7e7727d66a847485e202d008633d2a9ac
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be
useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com>
Cc: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516055620.2380197-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a9eb173515ec406e76e46211992ce7663f703bc4
https://github.com/qemu/qemu/commit/a9eb173515ec406e76e46211992ce7663f703bc4
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030
from UART6 to UART13. The addresses and interrupt numbers for these two
later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a398bb077eead505d27af4f3145e4e5c98581482
https://github.com/qemu/qemu/commit/a398bb077eead505d27af4f3145e4e5c98581482
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Add uarts_num SoC attribute
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 23d5f4fc2611536d6dd6eb7a4e7b97463e5b4a2e
https://github.com/qemu/qemu/commit/23d5f4fc2611536d6dd6eb7a4e7b97463e5b4a2e
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw: aspeed: Ensure AST1030 respects uart-default
The AST1030 machine initialization was not respecting the Aspeed SoC
property "uart-default", which specifies which UART should be connected to
the first serial device, it was just always connecting UART5. This doesn't
change any behavior, because the default value for "uart-default" is UART5,
but it makes it possible to override this in new machine definitions using
the AST1030.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-4-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0a65f0e3230245a6187fbcd537531d243d8c817b
https://github.com/qemu/qemu/commit/0a65f0e3230245a6187fbcd537531d243d8c817b
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Introduce common UART init function
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-5-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a1d2bd3fdeed2cf3e736bfc2a0579a5f53222144
https://github.com/qemu/qemu/commit/a1d2bd3fdeed2cf3e736bfc2a0579a5f53222144
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_soc.c
Log Message:
-----------
hw: aspeed: Init all UART's with serial devices
Background:
AspeedMachineClass.uart_default specifies the serial console UART, which
usually corresponds to the "stdout-path" in the device tree.
The default value is UART5, since most boards use UART5 for this:
amc->uart_default = ASPEED_DEV_UART5;
Users can override AspeedMachineClass.uart_default in their board's machine
class init to specify something besides UART5. For example, for fuji-bmc:
amc->uart_default = ASPEED_DEV_UART1;
We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
users can use. None of the other UART's are initialized, and the only way
to override this attribute is by creating a specialized board definition,
requiring QEMU source code changes and rebuilding.
The result of this is that if you want to get serial console output on a
board that uses UART3, you need to add a board definition. This was
encountered by Zev in OpenBMC. [1]
Changes:
This commit initializes all of the UART's present on each Aspeed chip with
serial devices and allows the QEMU user to connect as many or few as they
like to serial devices. For example, you can still run QEMU and just connect
stdout to the machine's default UART, without specifying any additional
serial devices:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
However, if you don't want to add a special machine definition, you can now
manually configure UART1 to connect to stdout and get serial console output,
even if the machine's default is UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
In the example above, the first "-serial null" argument is connected to
UART5, and "-serial mon:stdio" is connected to UART1.
Another example: you can get serial console output from Wedge100, which uses
UART3, by reusing the palmetto AST2400 machine and rewiring the serial
device arguments:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
There is a slight change in behavior introduced with this change: now, each
UART's memory-mapped IO region will have a serial device model connected to
it. Previously, all reads and writes to those regions would be ineffective
and return zero values, but now some values will be nonzero, even when the
user doesn't connect a serial device backend (like a socket, file, etc). For
example, the line status register might indicate that the transmit buffer is
empty now, whereas previously it might have always indicated it was full.
[1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
[2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
[3]
https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-6-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f27191d6c8d57a969f36b21d61b5220e723d407b
https://github.com/qemu/qemu/commit/f27191d6c8d57a969f36b21d61b5220e723d407b
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 59e68da005e79b9b729e3f7dea3e04d1b00a9cf5
https://github.com/qemu/qemu/commit/59e68da005e79b9b729e3f7dea3e04d1b00a9cf5
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8b4727544ca5c81a08b3c561a07dfb0c537ac0f3
https://github.com/qemu/qemu/commit/8b4727544ca5c81a08b3c561a07dfb0c537ac0f3
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 64b5d7a62cc6122435d799cf4ad2846a31632fb6
https://github.com/qemu/qemu/commit/64b5d7a62cc6122435d799cf4ad2846a31632fb6
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64
2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 70a8e1a810d376b6d0880fe2c40406d434bb1d38
https://github.com/qemu/qemu/commit/70a8e1a810d376b6d0880fe2c40406d434bb1d38
Author: Howard Chiu <howard_chiu@aspeedtech.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add i2c devices for AST2600 EVB
Add EEPROM and LM75 temperature sensor according to hardware schematic
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3a639bec8f3bbfb2e1260e5ddf932ae5a6238699
https://github.com/qemu/qemu/commit/3a639bec8f3bbfb2e1260e5ddf932ae5a6238699
Author: Yang Weijiang <weijiang.yang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Remove LBREn bit check when access Arch LBR MSRs
Live migration can happen when Arch LBR LBREn bit is cleared,
e.g., when migration happens after guest entered SMM mode.
In this case, we still need to migrate Arch LBR MSRs.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220517155024.33270-1-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1d325391bc6eff267462ad4eace11bc99aba6bbf
https://github.com/qemu/qemu/commit/1d325391bc6eff267462ad4eace11bc99aba6bbf
Author: Jaroslav Jindrak <dzejrou@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M backends/hostmem.c
Log Message:
-----------
hostmem: default the amount of prealloc-threads to smp-cpus
Prior to the introduction of the prealloc-threads property, the amount
of threads used to preallocate memory was derived from the value of
smp-cpus passed to qemu, the amount of physical cpus of the host
and a hardcoded maximum value. When the prealloc-threads property
was introduced, it included a default of 1 in backends/hostmem.c and
a default of smp-cpus using the sugar API for the property itself. The
latter default is not used when the property is not specified on qemu's
command line, so guests that were not adjusted for this change suddenly
started to use the default of 1 thread to preallocate memory, which
resulted in observable slowdowns in guest boots for guests with large
memory (e.g. when using libvirt <8.2.0 or managing guests manually).
This commit restores the original behavior for these cases while not
impacting guests started with the prealloc-threads property in any way.
Fixes: 220c1fd864e9d ("hostmem: introduce "prealloc-threads" property")
Signed-off-by: Jaroslav Jindrak <dzejrou@gmail.com>
Message-Id: <20220517123858.7933-1-dzejrou@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6bbbb50c439afb90ea9d4f885b036bc4987cc48c
https://github.com/qemu/qemu/commit/6bbbb50c439afb90ea9d4f885b036bc4987cc48c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M util/thread-pool.c
Log Message:
-----------
thread-pool: optimize scheduling of completion bottom half
The completion bottom half was scheduled within the pool->lock
critical section. That actually results in worse performance,
because the worker thread can run its own small critical section
and go to sleep before the bottom half starts running.
Note that this simple change does not produce an improvement without
changing the thread pool QemuSemaphore to a condition variable.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Message-Id: <20220514065012.1149539-2-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bfb415b16ccafb2b38b23fb2356f98e121bf6398
https://github.com/qemu/qemu/commit/bfb415b16ccafb2b38b23fb2356f98e121bf6398
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M util/thread-pool.c
Log Message:
-----------
thread-pool: replace semaphore with condition variable
Since commit f9fc8932b1 ("thread-posix: remove the posix semaphore
support", 2022-04-06) QemuSemaphore has its own mutex and condition
variable; this adds unnecessary overhead on I/O with small block sizes.
Check the QTAILQ directly instead of adding the indirection of a
semaphore's count. Using a semaphore has not been necessary since
qemu_cond_timedwait was introduced; the new code has to be careful about
spurious wakeups but it is simpler, for example thread_pool_cancel does
not have to worry about synchronizing the semaphore count with the number
of elements of pool->request_list.
Note that the return value of qemu_cond_timedwait (0 for timeout, 1 for
signal or spurious wakeup) is different from that of qemu_sem_timedwait
(-1 for timeout, 0 for success).
Reported-by: Lukáš Doktor <ldoktor@redhat.com>
Suggested-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Message-Id: <20220514065012.1149539-3-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 983e8174d0141eb74f0e9fdaf67f0d16b0537d1c
https://github.com/qemu/qemu/commit/983e8174d0141eb74f0e9fdaf67f0d16b0537d1c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M util/thread-pool.c
Log Message:
-----------
thread-pool: remove stopping variable
Just setting the max threads to 0 is enough to stop all workers.
Message-Id: <20220514065012.1149539-4-pbonzini@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6dda2de07c4f4978e8e2581bdd439f7923cd2663
https://github.com/qemu/qemu/commit/6dda2de07c4f4978e8e2581bdd439f7923cd2663
Author: Viktor Prutyanov <viktor.prutyanov@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M contrib/elf2dmp/qemu_elf.c
Log Message:
-----------
contrib/elf2dmp: add ELF dump header checking
Add ELF header checking to prevent processing input file which is not
QEMU x86_64 guest memory dump or even not ELF.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1013
Signed-off-by: Viktor Prutyanov <viktor.prutyanov@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220520084339.171684-1-viktor.prutyanov@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 439115265e1dcd7bb9e62a14cd750b3a8592f014
https://github.com/qemu/qemu/commit/439115265e1dcd7bb9e62a14cd750b3a8592f014
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/ac97.c
Log Message:
-----------
hw/audio/ac97: Coding style fixes to avoid checkpatch errors
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id:
<62862a057e9c9ec0bb45248b2b9a3a1babb346a6.1650706617.git.balaton@eik.bme.hu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f611fac6732cb2d7b8f06a820337954db606830a
https://github.com/qemu/qemu/commit/f611fac6732cb2d7b8f06a820337954db606830a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/ac97.c
Log Message:
-----------
hw/audio/ac97: Remove unimplemented reset functions
The warm_reset() and cold_reset() functions are not implemented and do
nothing so no point in calling them or keep around as dead code.
Therefore remove them for now.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id:
<cc6e99fd498a9ae358ebce787fc04ab6e8201879.1650706617.git.balaton@eik.bme.hu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cd09ba92cb198e4a4763aabf5167af57a233644e
https://github.com/qemu/qemu/commit/cd09ba92cb198e4a4763aabf5167af57a233644e
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/audio/ac97.c
Log Message:
-----------
hw/audio/ac97: Remove unneeded local variables
Several functions have a local variable that is just a copy of one of
the function parameters. This is unneeded complication so just get rid
of these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id:
<d959aa0b267eb139a994e41ca0b7ba87d9cef7a9.1650706617.git.balaton@eik.bme.hu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1872afd140646c994811375277ca55f2c020fdfb
https://github.com/qemu/qemu/commit/1872afd140646c994811375277ca55f2c020fdfb
Author: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host
Since KVM commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when
guest MPX disabled")
it is not possible to disable MPX on a "-cpu host" just by adding "-mpx"
there if the host CPU does indeed support MPX.
QEMU will fail to set MSR_IA32_VMX_TRUE_{EXIT,ENTRY}_CTLS MSRs in this case
and so trigger an assertion failure.
Instead, besides "-mpx" one has to explicitly add also
"-vmx-exit-clear-bndcfgs" and "-vmx-entry-load-bndcfgs" to QEMU command
line to make it work, which is a bit convoluted.
Make the MPX-related bits in FEAT_VMX_{EXIT,ENTRY}_CTLS dependent on MPX
being actually enabled so such workarounds are no longer necessary.
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Message-Id:
<51aa2125c76363204cc23c27165e778097c33f0b.1653323077.git.maciej.szmigiero@oracle.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: fbb0a3e9729a0a968d0e038a154ea4f46f554a6f
https://github.com/qemu/qemu/commit/fbb0a3e9729a0a968d0e038a154ea4f46f554a6f
Author: Lev Kujawski <lkujaw@member.fsf.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/ide/core.c
M hw/ide/macio.c
Log Message:
-----------
ide_ioport_read: Return lower octet of data register instead of 0xFF
Prior to this patch, the pre-GRUB Solaris x86 bootloader would fail to
load on QEMU with the following screen output:
SunOS Secondary Boot version 3.00
prom_panic: Could not mount filesystem.
Entering boot debugger:
[136419]: _
This occurs because the bootloader issues an ATA IDENTIFY DEVICE
command, and then reads the resulting 256 words of parameter
information using inb rather than the correct inw. As the previous
behavior of QEMU was to return 0xFF and not advance the drive's sector
buffer, DRQ would never be cleared and the bootloader would be blocked
from selecting a secondary ATA device, such as an optical drive.
Resolves:
* [Bug 1639394] Unable to boot Solaris 8/9 x86 under Fedora 24
Signed-off-by: Lev Kujawski <lkujaw@member.fsf.org>
Message-Id: <20220520235200.1138450-1-lkujaw@member.fsf.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: df91eb7d344109518640672f5d385760fd38a0ee
https://github.com/qemu/qemu/commit/df91eb7d344109518640672f5d385760fd38a0ee
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES
Previously, HV_CPUID_NESTED_FEATURES.EAX CPUID leaf was handled differently
as it was only used to encode the supported eVMCS version range. In fact,
there are also feature (e.g. Enlightened MSR-Bitmap) bits there. In
preparation to adding these features, move HV_CPUID_NESTED_FEATURES leaf
handling to hv_build_cpuid_leaf() and drop now-unneeded 'hyperv_nested'.
No functional change intended.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-2-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 79b8020e4255dcfe6cb07c454eec77197fbb20ae
https://github.com/qemu/qemu/commit/79b8020e4255dcfe6cb07c454eec77197fbb20ae
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/hyperv.txt
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv-proto.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Hyper-V Enlightened MSR bitmap feature
The newly introduced enlightenment allow L0 (KVM) and L1 (Hyper-V)
hypervisors to collaborate to avoid unnecessary updates to L2
MSR-Bitmap upon vmexits.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-3-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b6fda47852db97aa6e5509bad172e4647daf7df0
https://github.com/qemu/qemu/commit/b6fda47852db97aa6e5509bad172e4647daf7df0
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/hyperv.txt
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv-proto.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Hyper-V XMM fast hypercall input feature
Hyper-V specification allows to pass parameters for certain hypercalls
using XMM registers ("XMM Fast Hypercall Input"). When the feature is
in use, it allows for faster hypercalls processing as KVM can avoid
reading guest's memory.
KVM supports the feature since v5.14.
Rename HV_HYPERCALL_{PARAMS_XMM_AVAILABLE -> XMM_INPUT_AVAILABLE} to
comply with KVM.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-4-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3d9aa35a1881447f5653ab50d15ff0e9cf31c47b
https://github.com/qemu/qemu/commit/3d9aa35a1881447f5653ab50d15ff0e9cf31c47b
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/hyperv.txt
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv-proto.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls
KVM kind of supported "extended GVA ranges" (up to 4095 additional GFNs
per hypercall) since the implementation of Hyper-V PV TLB flush feature
(Linux-4.18) as regardless of the request, full TLB flush was always
performed. "Extended GVA ranges for TLB flush hypercalls" feature bit
wasn't exposed then. Now, as KVM gains support for fine-grained TLB
flush handling, exposing this feature starts making sense.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-5-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 078d43c83497b973e15b94c6a81e15d6974e293a
https://github.com/qemu/qemu/commit/078d43c83497b973e15b94c6a81e15d6974e293a
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/hyperv.txt
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv-proto.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Hyper-V Direct TLB flush hypercall
Hyper-V TLFS allows for L0 and L1 hypervisors to collaborate on L2's
TLB flush hypercalls handling. With the correct setup, L2's TLB flush
hypercalls can be handled by L0 directly, without the need to exit to
L1.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-6-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2b2f9998d8fd71bff25ea9f0357fb5cd59a59c26
https://github.com/qemu/qemu/commit/2b2f9998d8fd71bff25ea9f0357fb5cd59a59c26
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
R docs/hyperv.txt
A docs/system/i386/hyperv.rst
M docs/system/target-i386.rst
Log Message:
-----------
i386: docs: Convert hyperv.txt to rST
rSTify docs/hyperv.txt and link it from docs/system/target-i386.rst.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220525115949.1294004-7-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7fea1d0245463a9f98ce475fd49516524e262a95
https://github.com/qemu/qemu/commit/7fea1d0245463a9f98ce475fd49516524e262a95
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qapi/crypto.json
Log Message:
-----------
qapi: crypto-akcipher: Introduce akcipher types to qapi
Introduce akcipher types, also include RSA related types.
Signed-off-by: Lei He <helei.sig11@bytedance.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 6994a6965a19820aa6a7cdce06296fb77f9d60e3
https://github.com/qemu/qemu/commit/6994a6965a19820aa6a7cdce06296fb77f9d60e3
Author: zhenwei pi <pizhenwei@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A crypto/akcipher.c
A crypto/akcipherpriv.h
M crypto/meson.build
A include/crypto/akcipher.h
Log Message:
-----------
crypto: Introduce akcipher crypto class
Introduce new akcipher crypto class 'QCryptoAkCIpher', which supports
basic asymmetric operations: encrypt, decrypt, sign and verify.
Suggested by Daniel P. Berrangé, also add autoptr cleanup for the new
class. Thanks to Daniel!
Co-developed-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 2d86b2661f9f8d3e3c9c321af9b9fab57542fbae
https://github.com/qemu/qemu/commit/2d86b2661f9f8d3e3c9c321af9b9fab57542fbae
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A crypto/der.c
A crypto/der.h
M crypto/meson.build
M tests/unit/meson.build
A tests/unit/test-crypto-der.c
Log Message:
-----------
crypto: add ASN.1 DER decoder
Add an ANS.1 DER decoder which is used to parse asymmetric
cipher keys
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 480d4d93ff72df750e1a30b42b2af5d0e69e60a2
https://github.com/qemu/qemu/commit/480d4d93ff72df750e1a30b42b2af5d0e69e60a2
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A crypto/akcipher-nettle.c.inc
M crypto/akcipher.c
M crypto/meson.build
A crypto/rsakey-builtin.c.inc
A crypto/rsakey-nettle.c.inc
A crypto/rsakey.c
A crypto/rsakey.h
M meson.build
Log Message:
-----------
crypto: Implement RSA algorithm by hogweed
Implement RSA algorithm by hogweed from nettle. Thus QEMU supports
a 'real' RSA backend to handle request from guest side. It's
important to test RSA offload case without OS & hardware requirement.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: b8c30771f6f168088c34c6ebcf3e501c541a7f94
https://github.com/qemu/qemu/commit/b8c30771f6f168088c34c6ebcf3e501c541a7f94
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A crypto/akcipher-gcrypt.c.inc
M crypto/akcipher.c
Log Message:
-----------
crypto: Implement RSA algorithm by gcrypt
Added gcryt implementation of RSA algorithm, RSA algorithm
implemented by gcrypt has a higher priority than nettle because
it supports raw padding.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 0ed37ca377bb339f33650210ff444257d4a48410
https://github.com/qemu/qemu/commit/0ed37ca377bb339f33650210ff444257d4a48410
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M crypto/akcipher-nettle.c.inc
A tests/bench/benchmark-crypto-akcipher.c
M tests/bench/meson.build
A tests/bench/test_akcipher_keys.inc
M tests/unit/meson.build
A tests/unit/test-crypto-akcipher.c
Log Message:
-----------
test/crypto: Add test suite for crypto akcipher
Add unit test and benchmark test for crypto akcipher.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 1c636bbe73dff3a0fffebf153a0e1c9a32382d58
https://github.com/qemu/qemu/commit/1c636bbe73dff3a0fffebf153a0e1c9a32382d58
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/unit/test-crypto-akcipher.c
Log Message:
-----------
tests/crypto: Add test suite for RSA keys
As Daniel suggested, Add tests suite for rsakey, as a way to prove
that we can handle DER errors correctly.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 727c6112bf03936c7a83ba5210f0c53756ed22c8
https://github.com/qemu/qemu/commit/727c6112bf03936c7a83ba5210f0c53756ed22c8
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: allow setting stdout-path even on machines with a VGA
-machine graphics=off is the usual way to tell the firmware or the OS that the
user wants a serial console. The pseries machine however does not support
this, and never adds the stdout-path node to the device tree if a VGA device
is provided. This is in addition to the other magic behavior of VGA devices,
which is to add a keyboard and mouse to the default USB bus.
Split spapr->has_graphics in two variables so that the two behaviors can be
separated: the USB devices remains the same, but the stdout-path is added
even with "-device VGA -machine graphics=off".
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220507054826.124936-1-pbonzini@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9c79708217e3ddcd7b92550bbb13ddeeb037bf9f
https://github.com/qemu/qemu/commit/9c79708217e3ddcd7b92550bbb13ddeeb037bf9f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Remove unused BINARY_DEVICE_TREE_FILE
Commit 28290f37e20cda27574f15be9e9499493e3d0fe8 'PPC: E500: Generate
device tree on reset' improved device tree generation and made
BINARY_DEVICE_TREE_FILE obsolete.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220505161805.11116-8-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0963bb22a5ecf21cfec49b246efd1590d3ca9ae2
https://github.com/qemu/qemu/commit/0963bb22a5ecf21cfec49b246efd1590d3ca9ae2
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Use address from elf parser for kernel address
tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on.
QEMU loads the kernel at 0x400000 by default which works most of
the time as Linux kernels are relocatable, 64bit and compiled with "-pie"
(position independent code). This works for a little endian zImage too.
However a big endian zImage is compiled without -pie, is 32bit, linked to
0x4000000 so current QEMU ends up loading it at
0x4400000 but keeps spapr->kernel_addr unchanged so booting fails.
This uses the kernel address returned from load_elf().
If the default kernel_addr is used, there is no change in behavior (as
translate_kernel_address() takes care of this), which is:
LE/BE vmlinux and LE zImage boot, BE zImage does not.
If the VM created with "-machine kernel-addr=0,x-vof=on", then QEMU
prints a warning and BE zImage boots.
Note #1: SLOF (x-vof=off) still cannot boot a big endian zImage as
SLOF enables MSR_SF for everything loaded by QEMU and this leads to early
crash of 32bit zImage.
Note #2: BE/LE vmlinux images set MSR_SF in early boot so these just work;
a LE zImage restores MSR_SF after every CI call and we are lucky enough
not to crash before the first CI call.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220504065536.3534488-1-aik@ozlabs.ru>
[danielhb: use PRIx64 instead of lx in warn_report]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 352ab623fe0960dcd12fb652e4a897a50118d923
https://github.com/qemu/qemu/commit/352ab623fe0960dcd12fb652e4a897a50118d923
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
spapr/docs: Add a few words about x-vof
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20220506055124.3822112-1-aik@ozlabs.ru>
[danielhb: added linebreaks before and after table]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 81bd071f046206ca396e29627a7ba63a21414382
https://github.com/qemu/qemu/commit/81bd071f046206ca396e29627a7ba63a21414382
Author: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hmp-commands-info.hx
M monitor/misc.c
Log Message:
-----------
mos6522: fix linking error when CONFIG_MOS6522 is not set
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
Make devices configuration available in hmp-commands*.hx and check for
CONFIG_MOS6522.
Fixes: 409e9f7131e5 (mos6522: add "info via" HMP command for debugging)
Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Cc: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220510235439.54775-1-muriloo@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6006da81b0c93b1c6574e7667b955deaf6f56fb9
https://github.com/qemu/qemu/commit/6006da81b0c93b1c6574e7667b955deaf6f56fb9
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Fix tlbie
Commit 74c4912f097bab98 changed check_tlb_flush() to use
tlb_flush_all_cpus_synced() instead of calling tlb_flush() on each
CPU. However, as side effect of this, a CPU executing a ptesync
after a tlbie will have its TLB flushed only after exiting its
current Translation Block (TB).
This causes memory accesses to invalid pages to succeed, if they
happen to be on the same TB as the ptesync.
To fix this, use tlb_flush_all_cpus() instead, that immediately
flushes the TLB of the CPU executing the ptesync instruction.
Fixes: 74c4912f097bab98 ("target/ppc: Fix synchronization of mttcg with
broadcast TLB flushes")
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220503163904.22575-1-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8c641c680a36e9046d7679609b9c0ebdb1669cb1
https://github.com/qemu/qemu/commit/8c641c680a36e9046d7679609b9c0ebdb1669cb1
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
According to Power ISA, the FI bit in FPSCR is non-sticky.
This means that if an instruction is said to modify the FI bit, then
it should be set or cleared depending on the result of the
instruction. Otherwise, it should be kept as was before.
However, the following inconsistency was found when comparing results
from the hardware (tested on both a Power 9 processor and in
Power 10 Mambo):
(FI bit is set before the execution of the instruction)
Hardware: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> SET
QEMU: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> CLEARED
As the FI bit is non-sticky, and xscmpeqdp does not list it as a field
that is changed by the instruction, it should not be changed after its
execution.
This is happening to multiple instructions in the vsx implementations.
If the ISA does not list the FI bit as altered for a particular
instruction, then it should be kept as it was before the instruction.
QEMU is not following this behavior. Affected instructions include:
- xv* (all vsx-vector instructions);
- xscmp*, xsmax*, xsmin*;
- xstdivdp and similars;
(to identify the affected instructions, just search in the ISA for
the instructions that does not list FI in "Special Registers Altered")
Most instructions use the function do_float_check_status() to commit
changes in the inexact flag. So the fix is to add a parameter to it
that will control if the bit FI should be changed or not.
All users of do_float_check_status() are then modified to provide this
argument, controlling if that specific instruction changes bit FI or
not.
Some macro helpers are responsible for both instructions that change
and instructions that aren't suposed to change FI. This seems to always
overlap with the sfprf flag. So, reuse this flag for this purpose when
applicable.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517161522.36132-2-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4cfc7d170e3a541b71a0e0fe7b3f9fb8b4aa1051
https://github.com/qemu/qemu/commit/4cfc7d170e3a541b71a0e0fe7b3f9fb8b4aa1051
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exception is set
XX <- 1
...
FI is set to 1
...
"""
However, when tested on a Power 9 hardware, some instructions that
trigger an OX don't set the FI bit:
xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> CLEARED
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> CLEARED
(just a few examples. Other instructions are also affected)
The root cause for this seems to be that only instructions that list
the bit FI in the "Special Registers Altered" should modify it.
QEMU is, today, not working like the hardware:
xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> SET
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET
(all tests assume FI is cleared beforehand)
Fix this by making float_overflow_excp() return float_flag_inexact
if it should update the inexact flags.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20220517161522.36132-3-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 99e1c742db19b985c2be02dffb198ea18906a57f
https://github.com/qemu/qemu/commit/99e1c742db19b985c2be02dffb198ea18906a57f
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20220517161522.36132-4-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b9a6c1eac053c3b21275c8ae63c9f42e33c4be30
https://github.com/qemu/qemu/commit/b9a6c1eac053c3b21275c8ae63c9f42e33c4be30
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Don't overwrite PC registers when writing TCTXT registers
When writing a register from the TCTXT memory region (4th page within
the IC BAR), we were overwriting the Presentation Controller (PC)
register at the same offset. It looks like a silly cut and paste
error.
We were somehow lucky: the TCTXT registers being touched are
TCTXT_ENx/_SET/_RESET to enable physical threads and the PC registers
at the same offset are either not used by our model or the update was
harmless.
Found through code inspection.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220523151859.72283-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c50ac948a56877f90cc0218f2737db0945473106
https://github.com/qemu/qemu/commit/c50ac948a56877f90cc0218f2737db0945473106
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
Log Message:
-----------
target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c9b05672a7519bcdd8915ed9de9cc5c70fde9c1d
https://github.com/qemu/qemu/commit/c9b05672a7519bcdd8915ed9de9cc5c70fde9c1d
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
Log Message:
-----------
target/ppc: use TCG_CALL_NO_RWG in vector helpers without env
Helpers of vector instructions without cpu_env as an argument do not
access globals.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c718e9d3ebb2ee23b654c56bd10801601d0d4f8b
https://github.com/qemu/qemu/commit/c718e9d3ebb2ee23b654c56bd10801601d0d4f8b
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
Log Message:
-----------
target/ppc: use TCG_CALL_NO_RWG in BCD helpers
Helpers of BCD instructions only access the VSRs supplied by the
TCGv_ptr arguments, no globals are accessed.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0a7b47a3fe2706f97357390373003ec138e2a95a
https://github.com/qemu/qemu/commit/0a7b47a3fe2706f97357390373003ec138e2a95a
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
Log Message:
-----------
target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env
Helpers of VSX instructions without cpu_env as an argument do not access
globals.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0f9f973ddb06dcf372900d588eb84bebd3555279
https://github.com/qemu/qemu/commit/0f9f973ddb06dcf372900d588eb84bebd3555279
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper
fsel doesn't change FPSCR and CR1 is handled by gen_set_cr1_from_fpscr,
so helper_fsel doesn't need the env argument and can be declared with
TCG_CALL_NO_RWG_SE. We also take this opportunity to move the insn to
decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 788fe7d9651a0ad4e5f326422b666d0b29c4bd2e
https://github.com/qemu/qemu/commit/788fe7d9651a0ad4e5f326422b666d0b29c4bd2e
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: declare xscvspdpn helper with call flags
Move xscvspdpn to decodetree, declare helper_xscvspdpn with
TCG_CALL_NO_RWG_SE and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 344aa063c38b35712b3ed52ea10f7246921eaf29
https://github.com/qemu/qemu/commit/344aa063c38b35712b3ed52ea10f7246921eaf29
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: declare xvxsigsp helper with call flags
Move xvxsigsp to decodetree, declare helper_xvxsigsp with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3e42bd20a751a4a977496a3228e4c49e1c24caf1
https://github.com/qemu/qemu/commit/3e42bd20a751a4a977496a3228e4c49e1c24caf1
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: declare xxextractuw and xxinsertw helpers with call flags
Move xxextractuw and xxinsertw to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-9-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 57358cc9a6cd3cdacf17a2ad2f4d3a8f18da0709
https://github.com/qemu/qemu/commit/57358cc9a6cd3cdacf17a2ad2f4d3a8f18da0709
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: introduce do_va_helper
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-10-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 98eac4d5d2bafa2e31c475357c0421addf44ac20
https://github.com/qemu/qemu/commit/98eac4d5d2bafa2e31c475357c0421addf44ac20
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: declare vmsum[um]bm helpers with call flags
Move vmsumubm and vmsummbm to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-11-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 68287bfcbc2c6ae08e5c52385b3adf38676d23d3
https://github.com/qemu/qemu/commit/68287bfcbc2c6ae08e5c52385b3adf38676d23d3
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
target/ppc: declare vmsumuh[ms] helper with call flags
Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-12-matheus.ferst@eldorado.org.br>
[danielhb: added #undef VMSUMUHM to fix ppc64 build]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f95492a18413bf2dde8ca42eb369fc6d3cc02450
https://github.com/qemu/qemu/commit/f95492a18413bf2dde8ca42eb369fc6d3cc02450
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: declare vmsumsh[ms] helper with call flags
Move vmsumshm and vmsumshs to decodetree, declare vmsumshm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-13-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 40b5465035416dcdbbc25435c2f51ad8bec8521b
https://github.com/qemu/qemu/commit/40b5465035416dcdbbc25435c2f51ad8bec8521b
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Fix eieio memory ordering semantics
The generated eieio memory ordering semantics do not match the
instruction definition in the architecture. Add a big comment to
explain this strange instruction and correct the memory ordering
behaviour.
Signed-off: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a9a5128e4065133fe1e64b3caa83c1046ff63de2
https://github.com/qemu/qemu/commit/a9a5128e4065133fe1e64b3caa83c1046ff63de2
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: ST_ST memory ordering is not provided with eieio
eieio does not provide ordering between stores to CI memory and stores
to cacheable memory so it can't be used as a general ST_ST barrier.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-of-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220519135908.21282-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4202ab65872f36524b37fe12c298b097a3997211
https://github.com/qemu/qemu/commit/4202ab65872f36524b37fe12c298b097a3997211
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Optimize memory ordering generation with lwsync
lwsync orders more than just LD_LD, importantly it matches x86 and
s390 default memory ordering.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-4-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e6b6d58ff3cbaa47a5fe0d08d820b8201e87827d
https://github.com/qemu/qemu/commit/e6b6d58ff3cbaa47a5fe0d08d820b8201e87827d
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/machine.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Implement lwsync with weaker memory ordering
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 21740d5d853fe22b9be8878228c4f77bde04fcc5
https://github.com/qemu/qemu/commit/21740d5d853fe22b9be8878228c4f77bde04fcc5
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implement xxm[tf]acc and xxsetaccz
Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero
The PowerISA 3.1 mentions that for the current version of the
architecture, "the hardware implementation provides the effect of ACC[i]
and VSRs 4*i to 4*i + 3 logically containing the same data" and "The
Accumulators introduce no new logical state at this time" (page 501).
For now it seems unnecessary to create new structures, so this patch
just uses ACC[i] as VSRs 4*i to 4*i+3 and therefore move to and from
accumulators are no-ops.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0d3a610eb1b5cdbc79684d64bd4ce70546de0ad2
https://github.com/qemu/qemu/commit/0d3a610eb1b5cdbc79684d64bd4ce70546de0ad2
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented xvi*ger* instructions
Implement the following PowerISA v3.1 instructions:
xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update)
xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update)
Positive multiply, Positive accumulate
xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
with Saturate Positive multiply, Positive accumulate
xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update)
xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
Positive multiply, Positive accumulate
xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation
xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7e38d4928efcf8fd7728a8964bc0abc937740642
https://github.com/qemu/qemu/commit/7e38d4928efcf8fd7728a8964bc0abc937740642
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/insn64.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented pmxvi*ger* instructions
Implement the following PowerISA v3.1 instructions:
pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update)
pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) Positive multiply, Positive accumulate
pmxvi8ger4: Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update)
pmxvi8ger4pp: Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update) Positive multiply, Positive accumulate
pmxvi8ger4spp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) with Saturate Positive multiply, Positive accumulate
pmxvi16ger2: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update)
pmxvi16ger2pp: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvi16ger2s: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation
pmxvi16ger2spp: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5ad95fd6341dc665d316c828d6a8b55a02ea584c
https://github.com/qemu/qemu/commit/5ad95fd6341dc665d316c828d6a8b55a02ea584c
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented xvf*ger*
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ea83f1c28ed41fafeeaf221049386cc9b104131f
https://github.com/qemu/qemu/commit/ea83f1c28ed41fafeeaf221049386cc9b104131f
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented xvf16ger*
Implement the following PowerISA v3.1 instructions:
xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Negative accumulate
xvf16ger2np: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Positive accumulate
xvf16ger2pn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Negative accumulate
xvf16ger2pp: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-6-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c95ed55ed4b737cfac2aaa60e97a13a31db8e7c5
https://github.com/qemu/qemu/commit/c95ed55ed4b737cfac2aaa60e97a13a31db8e7c5
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/insn64.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented pmxvf*ger*
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
pmxvf16ger2np: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Positive accumulate
pmxvf16ger2pn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Negative accumulate
pmxvf16ger2pp: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvf32ger: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update)
pmxvf32gernn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf32gernp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf32gerpn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf32gerpp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
pmxvf64ger: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update)
pmxvf64gernn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf64gernp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf64gerpn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf64gerpp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e515144a718419c022eeae4a18f5cadc2e7c4cc7
https://github.com/qemu/qemu/commit/e515144a718419c022eeae4a18f5cadc2e7c4cc7
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/insn64.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented [pm]xvbf16ger2*
Implement the following PowerISA v3.1 instructions:
xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Positive accumulate
xvbf16ger2pn: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Negative accumulate
xvbf16ger2pp: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Positive accumulate
pmxvbf16ger2: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
pmxvbf16ger2nn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Negative accumulate
pmxvbf16ger2np: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Positive accumulate
pmxvbf16ger2pn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Negative accumulate
pmxvbf16ger2pp: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-8-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 85b4ba91f87847e4f5e429a1b672fdf4b0824cf6
https://github.com/qemu/qemu/commit/85b4ba91f87847e4f5e429a1b672fdf4b0824cf6
Author: Joel Stanley <joel@jms.id.au>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user: Add PowerPC ISA 3.1 and MMA to hwcap
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7576de60e6c0fcd62f94aab899f7b362c8f0998f
https://github.com/qemu/qemu/commit/7576de60e6c0fcd62f94aab899f7b362c8f0998f
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
New SeaBIOS-hppa version 6
Staring with SEABIOS_HPPA_VERSION 6 the serial ports are now emulated as
on physical hardware, with LASI UART being serial port #0 and DINO UART
as serial port #1. On older versions those ports were swapped.
This SeaBIOS-hppa fix is needed to allow fixing the qemu serial
pass-through from host to guest.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 6f94c3a70992d98999a0df70816e16d1dc2c1463
https://github.com/qemu/qemu/commit/6f94c3a70992d98999a0df70816e16d1dc2c1463
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/hppa/hppa_hardware.h
Log Message:
-----------
hppa: Sync contents of hppa_hardware.h header file with SeaBIOS-hppa
The hppa_hardware.h header file holds many constants for addresses and
offsets which are needed while building the firmware (SeaBIOS-hppa) and
while setting up the virtual machine in QEMU.
That's why this header file needs to be in sync between both source code
repositories. This patch adds a comment mentioning this dependency at
the top of this file and restores some DINO relevant offsets.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 8f79a66ad5bf2fa6a02899edf479b9322b498238
https://github.com/qemu/qemu/commit/8f79a66ad5bf2fa6a02899edf479b9322b498238
Author: Helge Deller <deller@gmx.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
Log Message:
-----------
hppa: Fix serial port assignments and pass-through
This fixes the serial ports in the emulation to behave as on original
hardware.
On the real hardware, the LASI UART is serial port #0 and the DINO UART
is serial port #1. This is fixed in SeaBIOS-hppa firmware v6, which is
why at least this firmware version is required.
The serial port addresses in hppa/hppa_hardware.h have to be swapped,
and when creating the virtual serial ports the correct port addresses
are used.
This patch now for example allows to specify on the qemu command line:
-serial mon:stdio -serial /dev/ttyS4
to use the emulated ttyS0 in the guest for console output, and pass
ttyS4 from the host to ttyS1 in the guest.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 1345c7c6344a3de89ce19ba5bddd90cae4f2d95a
https://github.com/qemu/qemu/commit/1345c7c6344a3de89ce19ba5bddd90cae4f2d95a
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/qemu/cutils.h
M include/qemu/osdep.h
M qemu-io.c
M storage-daemon/qemu-storage-daemon.c
M tests/qtest/fuzz/fuzz.c
M util/cutils.c
M util/oslib-posix.c
M util/oslib-win32.c
Log Message:
-----------
include: move qemu_*_exec_dir() to cutils
The function is required by get_relocated_path() (already in cutils),
and used by qemu-ga and may be generally useful.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-2-marcandre.lureau@redhat.com>
Commit: a7a2c580d36fbfe24628c562bffa531808c9855a
https://github.com/qemu/qemu/commit/a7a2c580d36fbfe24628c562bffa531808c9855a
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M util/oslib-win32.c
Log Message:
-----------
util/win32: simplify qemu_get_local_state_dir()
SHGetFolderPath() is a deprecated API:
https://docs.microsoft.com/en-us/windows/win32/api/shlobj_core/nf-shlobj_core-shgetfolderpatha
It is a wrapper for SHGetKnownFolderPath() and CSIDL_COMMON_PATH is
mapped to FOLDERID_ProgramData:
https://docs.microsoft.com/en-us/windows/win32/shell/csidl
g_get_system_data_dirs() is a suitable replacement, as it will have
FOLDERID_ProgramData in the returned list. However, it follows the XDG
Base Directory Specification, if `XDG_DATA_DIRS` is defined, it will be
returned instead.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20220525144140.591926-3-marcandre.lureau@redhat.com>
Commit: 64cb74b1c8a185010322a46f9a3ef36bd07a1b16
https://github.com/qemu/qemu/commit/64cb74b1c8a185010322a46f9a3ef36bd07a1b16
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/libqmp.c
M tests/qtest/libqmp.h
Log Message:
-----------
tests: make libqmp buildable for win32
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220525144140.591926-4-marcandre.lureau@redhat.com>
Commit: 111613e5beef16a770b4b0a18b48d0f9442dcfa4
https://github.com/qemu/qemu/commit/111613e5beef16a770b4b0a18b48d0f9442dcfa4
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga: flatten safe_open_or_create()
There is a bit too much nesting in the function, this can be simplified
a bit to improve readability.
This also helps with the following error handling changes.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-5-marcandre.lureau@redhat.com>
Commit: e7b109a4d691c7397b44c94e2c9820cc1b3a55b0
https://github.com/qemu/qemu/commit/e7b109a4d691c7397b44c94e2c9820cc1b3a55b0
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A qga/cutils.c
A qga/cutils.h
M qga/meson.build
Log Message:
-----------
qga: add qga_open_cloexec() helper
QGA calls qemu_open_old() in various places. Calling qemu_open() instead
isn't a great alternative, as it has special "/dev/fdset" handling and
depends on QEMU internal monitor data structures.
Instead, provide a simple helper for QGA needs, with Error* support. The
following patches will make use of it.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-6-marcandre.lureau@redhat.com>
Commit: 420230e4be90e4c1fc1d499847b077a752a62c5a
https://github.com/qemu/qemu/commit/420230e4be90e4c1fc1d499847b077a752a62c5a
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga: use qga_open_cloexec() for safe_open_or_create()
The function takes care of setting CLOEXEC.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-7-marcandre.lureau@redhat.com>
Commit: 7e19aeb241ea5bc92fbc53b221cf5aefea3f95b2
https://github.com/qemu/qemu/commit/7e19aeb241ea5bc92fbc53b221cf5aefea3f95b2
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/channel-posix.c
Log Message:
-----------
qga: throw an Error in ga_channel_open()
Allow for a single point of error reporting, and further refactoring.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-8-marcandre.lureau@redhat.com>
Commit: 5feec335249986a52e8397bc9c9c904b37e020f1
https://github.com/qemu/qemu/commit/5feec335249986a52e8397bc9c9c904b37e020f1
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/channel-posix.c
M qga/commands-posix.c
Log Message:
-----------
qga: replace qemu_open_old() with qga_open_cloexec()
qemu_open_old() uses qemu_open_internal() which handles special
"/dev/fdset/" path for monitor fd sets, set CLOEXEC, and uses Error
reporting (and some O_DIRECT special error casing).
The monitor fdset handling is unnecessary for qga, use
qga_open_cloexec() instead.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-9-marcandre.lureau@redhat.com>
Commit: ed1251d7e411ef24f16392d952bd5a0305d4e50f
https://github.com/qemu/qemu/commit/ed1251d7e411ef24f16392d952bd5a0305d4e50f
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/commands-posix.c
Log Message:
-----------
qga: make build_fs_mount_list() return a bool
Change build_fs_mount_list() to return bool, in accordance
with the guidance under = Rules = in include/qapi/error.h
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Suggested-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220525144140.591926-10-marcandre.lureau@redhat.com>
Commit: 1266e836b8d61faedd358f86109021ed0a86d372
https://github.com/qemu/qemu/commit/1266e836b8d61faedd358f86109021ed0a86d372
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/unit/test-qga.c
Log Message:
-----------
test/qga: use G_TEST_DIR to locate os-release test file
This a more accurate way to lookup the test data, and will allow to move
the test in a subproject.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-11-marcandre.lureau@redhat.com>
Commit: 6a585ef34c8b19828deec9cea9f14681a3a56d81
https://github.com/qemu/qemu/commit/6a585ef34c8b19828deec9cea9f14681a3a56d81
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/installer/qemu-ga.wxs
M qga/meson.build
Log Message:
-----------
qga/wixl: prefer variables over environment
No need to setup an environment or to check if the variable is undefined
manually.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-12-marcandre.lureau@redhat.com>
Commit: b2657b13d3b8353b2cdab92fcd1baefc7d7608bc
https://github.com/qemu/qemu/commit/b2657b13d3b8353b2cdab92fcd1baefc7d7608bc
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/installer/qemu-ga.wxs
Log Message:
-----------
qga/wixl: require Mingw_bin
No clear reason to make guesses here.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-13-marcandre.lureau@redhat.com>
Commit: 998b5e3d9728ff26cc95d52c322bac7b1d1ae132
https://github.com/qemu/qemu/commit/998b5e3d9728ff26cc95d52c322bac7b1d1ae132
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/installer/qemu-ga.wxs
Log Message:
-----------
qga/wixl: simplify some pre-processing
Sadly, wixl doesn't have 'elif'.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-14-marcandre.lureau@redhat.com>
Commit: 98212fcbab18342ba74ca4ecd032c67c2c499682
https://github.com/qemu/qemu/commit/98212fcbab18342ba74ca4ecd032c67c2c499682
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M meson.build
M qga/installer/qemu-ga.wxs
M qga/meson.build
Log Message:
-----------
qga/wixl: replace QEMU_GA_MSI_MINGW_BIN_PATH with glib bindir
Use more conventional variables to set the location of pre-built
DLL/bin.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-15-marcandre.lureau@redhat.com>
Commit: 11e42a4ccc5383397782096785fa40f644c7f451
https://github.com/qemu/qemu/commit/11e42a4ccc5383397782096785fa40f644c7f451
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/unit/test-qga.c
Log Message:
-----------
test/qga: use g_auto wherever sensible
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-Id: <20220525144140.591926-16-marcandre.lureau@redhat.com>
Commit: c388e9411931e374a03f6a50e1cb54af779839f7
https://github.com/qemu/qemu/commit/c388e9411931e374a03f6a50e1cb54af779839f7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/system/arm/emulation.rst
Log Message:
-----------
docs/system/arm: Add FEAT_HCX to list of emulated features
In commit 5814d587fe861fe9 we added support for emulating
FEAT_HCX (Support for the HCRX_EL2 register). However we
forgot to add it to the list in emulated.rst. Correct the
omission.
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220520084320.424166-1-peter.maydell@linaro.org
Commit: d522a2f524a2d4be75e6792802d14da78fc8101f
https://github.com/qemu/qemu/commit/d522a2f524a2d4be75e6792802d14da78fc8101f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Include missing "cpregs.h"
Fix when building HVF on macOS Aarch64:
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you
mean 'ARMCPUInfo'?
const ARMCPRegInfo *ri;
^~~~~~~~~~~~
ARMCPUInfo
target/arm/cpu-qom.h:38:3: note: 'ARMCPUInfo' declared here
} ARMCPUInfo;
^
target/arm/hvf/hvf.c:589:14: error: implicit declaration of function
'get_arm_cp_reginfo' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
^
target/arm/hvf/hvf.c:589:12: warning: incompatible integer to pointer
conversion assigning to 'const ARMCPUInfo *' (aka 'const struct ARMCPUInfo *')
from 'int' [-Wint-conversion]
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
target/arm/hvf/hvf.c:591:26: error: no member named 'type' in 'struct
ARMCPUInfo'
assert(!(ri->type & ARM_CP_NO_RAW));
~~ ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/include/assert.h:99:25:
note: expanded from macro 'assert'
(__builtin_expect(!(e), 0) ? __assert_rtn(__func__, __ASSERT_FILE_NAME,
__LINE__, #e) : (void)0)
^
target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier
'ARM_CP_NO_RAW'
assert(!(ri->type & ARM_CP_NO_RAW));
^
1 warning and 4 errors generated.
Fixes: cf7c6d1004 ("target/arm: Split out cpregs.h")
Reported-by: Duncan Bayne <duncan@bayne.id.au>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220525161926.34233-1-philmd@fungible.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1029
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d207a69770ee0d23c532f391efe823a4f7a8dfdc
https://github.com/qemu/qemu/commit/d207a69770ee0d23c532f391efe823a4f7a8dfdc
Author: Icenowy Zheng <uwu@icenowy.me>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/sd/allwinner-sdhost.c
Log Message:
-----------
hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
U-Boot queries the FIFO water level to reduce checking status register
when doing PIO SD card operation.
Report a FIFO water level of 1 when data is ready, to prevent the code
from trying to read 0 words from the FIFO each time.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Message-id: 20220520124200.2112699-1-uwu@icenowy.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e6249b111c36befdffd8f37b77310c2eb00503d
https://github.com/qemu/qemu/commit/9e6249b111c36befdffd8f37b77310c2eb00503d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate.h
Log Message:
-----------
target/arm: Introduce TRANS, TRANS_FEAT
Steal the idea for these leaf function expanders from PowerPC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8c57b8af5f46f384c80f0bba799563766e99b882
https://github.com/qemu/qemu/commit/8c57b8af5f46f384c80f0bba799563766e99b882
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_ool_zz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 145ac7f0e3fe3f75ef86c2bd14ab1c04e7acca62
https://github.com/qemu/qemu/commit/145ac7f0e3fe3f75ef86c2bd14ab1c04e7acca62
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8845ad7103b6bf45ab895933bc11cea0602ee752
https://github.com/qemu/qemu/commit/8845ad7103b6bf45ab895933bc11cea0602ee752
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_ool_zzz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f04689340ebe83144cb2f4466994d9e0d29223ed
https://github.com/qemu/qemu/commit/f04689340ebe83144cb2f4466994d9e0d29223ed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_ool_arg_zzz
Use gen_gvec_ool_arg_zzz instead of gen_gvec_ool_zzz
when the arguments come from arg_rrr_esz.
Replaces do_zzw_ool and do_zzz_data_ool.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 685792ce2ae13de11833e9306d4ed2c03ea28569
https://github.com/qemu/qemu/commit/685792ce2ae13de11833e9306d4ed2c03ea28569
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
Convert SVE translation functions using
gen_gvec_ool_arg_zzz to TRANS_FEAT.
Remove trivial wrappers do_aese, do_sm4.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b431440b856a2999809b352be972fd24fd6df6c8
https://github.com/qemu/qemu/commit/b431440b856a2999809b352be972fd24fd6df6c8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
Convert SVE translation functions using do_sve2_zzz_ool
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0ad853946cca1cbb9609d24c1facfd77f03d3c09
https://github.com/qemu/qemu/commit/0ad853946cca1cbb9609d24c1facfd77f03d3c09
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_ool_zzzz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 15f985812037e105e873c8979bc4a7eb82edcacd
https://github.com/qemu/qemu/commit/15f985812037e105e873c8979bc4a7eb82edcacd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
Convert SVE translation functions directly using
gen_gvec_ool_zzzz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 690f936b68e20834956f80185f9ec4e03d068067
https://github.com/qemu/qemu/commit/690f936b68e20834956f80185f9ec4e03d068067
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_ool_arg_zzzz
Use gen_gvec_ool_arg_zzzz instead of gen_gvec_ool_zzzz
when the arguments come from arg_rrrr_esz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 952fd087e040e3b6d51dcc2825f608c1e9dc2676
https://github.com/qemu/qemu/commit/952fd087e040e3b6d51dcc2825f608c1e9dc2676
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
Convert SVE translation functions using do_sve2_zzzz_ool
to use TRANS_FEAT and gen_gvec_ool_arg_zzzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d73d4559502ca56f7d12c9796a092b0a23d01393
https://github.com/qemu/qemu/commit/d73d4559502ca56f7d12c9796a092b0a23d01393
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
Convert SVE translation functions directly using
gen_gvec_ool_arg_zzzz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a0b104977509743c9b9dafc35c56ba9d06eece2
https://github.com/qemu/qemu/commit/4a0b104977509743c9b9dafc35c56ba9d06eece2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
Rename the function to match gen_gvec_ool_arg_zzzz,
and move to be adjacent.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-14-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 889d819f2a761e2589fdcdc0a324ef0a00fc77ee
https://github.com/qemu/qemu/commit/889d819f2a761e2589fdcdc0a324ef0a00fc77ee
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
Convert SVE translation functions directly using
gen_gvec_ool_arg_zzxz to TRANS_FEAT. Also include
BFDOT_zzxz, which was using gen_gvec_ool_zzzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2e2a788fa324f4b390321e904688abdfa6be90a2
https://github.com/qemu/qemu/commit/2e2a788fa324f4b390321e904688abdfa6be90a2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzz_data
Convert SVE translation functions using do_sve2_zzz_data
to use TRANS_FEAT and gen_gvec_ool_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-16-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5707c32286b2dc5ea48501879bd3e417c5bf04de
https://github.com/qemu/qemu/commit/5707c32286b2dc5ea48501879bd3e417c5bf04de
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
Convert SVE translation functions using do_sve2_zzzz_data
to use TRANS_FEAT and gen_gvec_ool_{zzzz,zzxz}.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-17-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a9f95a24fd957645f094cab094ee4b4ad9ed4b1b
https://github.com/qemu/qemu/commit/a9f95a24fd957645f094cab094ee4b4ad9ed4b1b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzw_data
Convert SVE translation functions using do_sve2_zzw_data
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-18-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d50f00d18837291181109287aeffc36dbdfe58f1
https://github.com/qemu/qemu/commit/d50f00d18837291181109287aeffc36dbdfe58f1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for USDOT_zzzz
This is the last direct user of tcg_gen_gvec_4_ool.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-19-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5bfc15c01af931fab7ca042e06a446d6a16e7df0
https://github.com/qemu/qemu/commit/5bfc15c01af931fab7ca042e06a446d6a16e7df0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_ool_zzp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-20-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d5d2439f0c91cf9e47af3cec05bcec0df729521f
https://github.com/qemu/qemu/commit/d5d2439f0c91cf9e47af3cec05bcec0df729521f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_ool_arg_zpz
Use gen_gvec_ool_arg_zpz instead of gen_gvec_ool_zzp
when the arguments come from arg_rpr_esz.
Replaces do_zpz_ool.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-21-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4e5a4170688dec973b6a5cb2ebfcf81b4a6f727d
https://github.com/qemu/qemu/commit/4e5a4170688dec973b6a5cb2ebfcf81b4a6f727d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
Convert SVE translation functions directly using
gen_gvec_ool_arg_zpz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-22-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc1b7a38f4acbbd7cc4a83fa54184f9e8d8725c6
https://github.com/qemu/qemu/commit/fc1b7a38f4acbbd7cc4a83fa54184f9e8d8725c6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zpz_data
Convert SVE translation functions using do_sve2_zpz_data
to use TRANS_FEAT and gen_gvec_ool_arg_zpz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-23-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 04348981fdcba76693ad3013e3c76cee360499c5
https://github.com/qemu/qemu/commit/04348981fdcba76693ad3013e3c76cee360499c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
Rename the function to match gen_gvec_ool_arg_zpz,
and move to be adjacent.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-24-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f15f2078f252374dcb4585daa9d5313cf8d41d42
https://github.com/qemu/qemu/commit/f15f2078f252374dcb4585daa9d5313cf8d41d42
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
Convert some SVE translation functions using
gen_gvec_ool_arg_zpzi to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-25-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 038c5f2ad9347ac47ebd55e038a4594615bae92e
https://github.com/qemu/qemu/commit/038c5f2ad9347ac47ebd55e038a4594615bae92e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_ool_zzzp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-26-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c76dfeffb179e147293653994f54fd7ef5e0e03c
https://github.com/qemu/qemu/commit/c76dfeffb179e147293653994f54fd7ef5e0e03c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_ool_arg_zpzz
Use gen_gvec_ool_arg_zpzz instead of gen_gvec_ool_zzzp
when the arguments come from arg_rprr_esz.
Replaces do_zpzz_ool.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-27-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc9adb73738291958192f1b479a8b135ddd1ebd4
https://github.com/qemu/qemu/commit/fc9adb73738291958192f1b479a8b135ddd1ebd4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
Convert SVE translation functions directly using
gen_gvec_ool_arg_zpzz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-28-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cb582c99253738fff31a9c2eda1982e955b4bc46
https://github.com/qemu/qemu/commit/cb582c99253738fff31a9c2eda1982e955b4bc46
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
Convert SVE translation functions using do_sve2_zpzz_ool
to use TRANS_FEAT and gen_gvec_ool_arg_zpzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-29-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 76f2dc0bc448211123e93174c781cb7fc0eae89a
https://github.com/qemu/qemu/commit/76f2dc0bc448211123e93174c781cb7fc0eae89a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Merge gen_gvec_fn_zz into do_mov_z
There is only one caller for gen_gvec_fn_zz; inline it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-30-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83263a4832acaa2874853dbe610244ef0e6b0d00
https://github.com/qemu/qemu/commit/83263a4832acaa2874853dbe610244ef0e6b0d00
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into gen_gvec_fn_zzz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-31-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cee3fe4cea48a476975363ee89e04e0bf4576919
https://github.com/qemu/qemu/commit/cee3fe4cea48a476975363ee89e04e0bf4576919
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
Rename the function to match gen_gvec_fn_zzz,
and move to be adjacent.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-32-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5cb4c8e7d255ac506a8f6c5410d4667e86dd1f90
https://github.com/qemu/qemu/commit/5cb4c8e7d255ac506a8f6c5410d4667e86dd1f90
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: More use of gen_gvec_fn_arg_zzz
Two uses of gen_gvec_fn_zzz can pass on arg_rrr_esz instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-33-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 971d2136cec9ed4a78af60147fd5e1bbcec07f18
https://github.com/qemu/qemu/commit/971d2136cec9ed4a78af60147fd5e1bbcec07f18
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
Convert SVE translation functions directly using
gen_gvec_fn_arg_zzz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-34-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 67b48a33181ad454e59ad1aee397695aa3320562
https://github.com/qemu/qemu/commit/67b48a33181ad454e59ad1aee397695aa3320562
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
Convert SVE translation functions using do_sve2_fn_zzz
to use TRANS_FEAT and gen_gvec_fn_arg_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-35-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e52300d2719a5a11348ddf3a8ca185779c40cd51
https://github.com/qemu/qemu/commit/e52300d2719a5a11348ddf3a8ca185779c40cd51
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for RAX1
The decode for RAX1 sets esz to MO_8, because that's what
we use by default for "no esz present". We changed that
to MO_64 during translation because it is more logical for
the operation. However, the esz argument to gen_gvec_rax1
is unused and forces MO_64 within that function, so there
is no need to do it here as well.
Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-36-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 742e7f4a06ddfbdf913b37d8fb2d1e0290cdc54c
https://github.com/qemu/qemu/commit/742e7f4a06ddfbdf913b37d8fb2d1e0290cdc54c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_fn_arg_zzzz
Merge gen_gvec_fn_zzzz with the sve access check and the
dereference of arg_rrrr_esz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-37-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 20057dca8f2172b731fa89cb333f984b4c214b11
https://github.com/qemu/qemu/commit/20057dca8f2172b731fa89cb333f984b4c214b11
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
Convert SVE translation functions using do_sve2_zzzz_fn
to use TRANS_FEAT and gen_gvec_fn_arg_zzzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-38-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 30ff3702944bc47075de6a64d6086ec5a20bbfd1
https://github.com/qemu/qemu/commit/30ff3702944bc47075de6a64d6086ec5a20bbfd1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_fn_zzi
We have two places that perform this particular operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-39-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4e138bc861a8e3fa1c7749dad0b9f6711eaf255e
https://github.com/qemu/qemu/commit/4e138bc861a8e3fa1c7749dad0b9f6711eaf255e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_zz_dbm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-40-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9ff1c87f49f2b9ec51dc1d1da60bb28382f27488
https://github.com/qemu/qemu/commit/9ff1c87f49f2b9ec51dc1d1da60bb28382f27488
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Hoist sve access check through do_sel_z
The check is already done in gen_gvec_ool_zzzp,
which is called by do_sel_z; remove from callers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-41-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: df321641c14874c9915449cfb97b141da96703e1
https://github.com/qemu/qemu/commit/df321641c14874c9915449cfb97b141da96703e1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_fn_arg_zzi
We have two places that perform this particular operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-42-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f5bd785a027c10f7cb834a927908db3e76a7952c
https://github.com/qemu/qemu/commit/f5bd785a027c10f7cb834a927908db3e76a7952c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_fn2i
Convert SVE translation functions using do_sve2_fn2i
to use TRANS_FEAT and gen_gvec_fn_arg_zzi.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-43-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d9bb094c36dbf14a2b97ab988a8cbe356b3247e
https://github.com/qemu/qemu/commit/3d9bb094c36dbf14a2b97ab988a8cbe356b3247e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_vpz_ool
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-44-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d542a1c5b84f25b95b8b347ecac9ef98dbb95478
https://github.com/qemu/qemu/commit/d542a1c5b84f25b95b8b347ecac9ef98dbb95478
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_shift_imm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-45-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 867f6622756a85e9d4b30fa285bc4a3654c4230e
https://github.com/qemu/qemu/commit/867f6622756a85e9d4b30fa285bc4a3654c4230e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce do_shift_zpzi
Share code between the various shifts using arg_rpri_esz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-46-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5f1c313186313de7b382ded1f298a08860cbe262
https://github.com/qemu/qemu/commit/5f1c313186313de7b382ded1f298a08860cbe262
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_shift_zpzi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-47-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 58b19ec8900a3ac572e34c72bedc0f69254a5dfc
https://github.com/qemu/qemu/commit/58b19ec8900a3ac572e34c72bedc0f69254a5dfc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_zpzzz_ool
Remove the DO_ZPZZZ macro, as it had just the two uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-48-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 312d9fda79d5d664051093a694bc5c7b155bed6f
https://github.com/qemu/qemu/commit/312d9fda79d5d664051093a694bc5c7b155bed6f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move sve check into do_index
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-49-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7233fded41344dad3cea5eb38c8d0d191e12dbba
https://github.com/qemu/qemu/commit/7233fded41344dad3cea5eb38c8d0d191e12dbba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_index
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-50-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fe9e5e4157c476045b282d8e306accfcebe7b773
https://github.com/qemu/qemu/commit/fe9e5e4157c476045b282d8e306accfcebe7b773
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_adr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-51-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ea24eddf945bd2d50f272c2860188de12312dd2b
https://github.com/qemu/qemu/commit/ea24eddf945bd2d50f272c2860188de12312dd2b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_predset
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-52-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ecfbceec3a7790a2f0a3e95f2a1a3e848bbade9c
https://github.com/qemu/qemu/commit/ecfbceec3a7790a2f0a3e95f2a1a3e848bbade9c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for RDFFR, WRFFR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-53-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 450548793b493b9145aa1aabdb77b23caa48ceda
https://github.com/qemu/qemu/commit/450548793b493b9145aa1aabdb77b23caa48ceda
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_pfirst_pnext
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-54-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2f1d4bd2ab5547dd8ff78524787d6536e5aa9a7a
https://github.com/qemu/qemu/commit/2f1d4bd2ab5547dd8ff78524787d6536e5aa9a7a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_EXT
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-55-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 06126f0c2a7354e900edc183ab105e236b69b919
https://github.com/qemu/qemu/commit/06126f0c2a7354e900edc183ab105e236b69b919
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_perm_pred3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-56-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ce854768e811c95a543edf6a6fad8042b43bc76c
https://github.com/qemu/qemu/commit/ce854768e811c95a543edf6a6fad8042b43bc76c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_perm_pred2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-57-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b0fdd6fea26b0f5c4e6a401e7989a65763d7b7f5
https://github.com/qemu/qemu/commit/b0fdd6fea26b0f5c4e6a401e7989a65763d7b7f5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move sve zip high_ofs into simd_data
This is in line with how we treat uzp, and will
eliminate the special case code during translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-58-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 01fcab9a44eb5a5773b7b59572ccc7133456c968
https://github.com/qemu/qemu/commit/01fcab9a44eb5a5773b7b59572ccc7133456c968
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-59-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3c28788fbe48c00e25238bc7d265421acfd6a20a
https://github.com/qemu/qemu/commit/3c28788fbe48c00e25238bc7d265421acfd6a20a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_zip, do_zip_q
Convert SVE translation functions using do_zip*
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-60-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 770cbaa8608c0e167357545ab72a611ce843d864
https://github.com/qemu/qemu/commit/770cbaa8608c0e167357545ab72a611ce843d864
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_clast_vector
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-61-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 19ba2de1aae888c5a981fc4c1e28f005bcc2a773
https://github.com/qemu/qemu/commit/19ba2de1aae888c5a981fc4c1e28f005bcc2a773
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_clast_fp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-62-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2a540862af2007bb121d9ca0f30d7d00391ea938
https://github.com/qemu/qemu/commit/2a540862af2007bb121d9ca0f30d7d00391ea938
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_clast_general
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-63-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b49e6a6f83b74fc680d456a08aa99a1526a9643e
https://github.com/qemu/qemu/commit/b49e6a6f83b74fc680d456a08aa99a1526a9643e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_last_fp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-64-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7db106fe6f464f4eb4a473231a7eecd632141f7d
https://github.com/qemu/qemu/commit/7db106fe6f464f4eb4a473231a7eecd632141f7d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_last_general
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-65-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f0e6d372a517b91e3de6e56c673b7bef0e888821
https://github.com/qemu/qemu/commit/f0e6d372a517b91e3de6e56c673b7bef0e888821
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for SPLICE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-66-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: da59da73424ebe885455fa09a05c790c4183468e
https://github.com/qemu/qemu/commit/da59da73424ebe885455fa09a05c790c4183468e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_ppzz_flags
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-67-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c53e0d438086362cf17408ba5256c338c508949d
https://github.com/qemu/qemu/commit/c53e0d438086362cf17408ba5256c338c508949d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-68-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 07dd20cb896b583b770dd97c5d3b29da37701145
https://github.com/qemu/qemu/commit/07dd20cb896b583b770dd97c5d3b29da37701145
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_ppzi_flags
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-69-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 01b0104aae6d7eda794ce7c8fe68d398675faa49
https://github.com/qemu/qemu/commit/01b0104aae6d7eda794ce7c8fe68d398675faa49
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_brk2, do_brk3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-70-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d0f65af6ca6b58b205964bfde0cb6137b140d4fa
https://github.com/qemu/qemu/commit/d0f65af6ca6b58b205964bfde0cb6137b140d4fa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for MUL_zzi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-71-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: de4a48599d7b81582832d8aa4904c6de019480a2
https://github.com/qemu/qemu/commit/de4a48599d7b81582832d8aa4904c6de019480a2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Reject dup_i w/ shifted byte early
Remove the unparsed extraction in trans_DUP_i,
which is intended to reject an 8-bit shift of
an 8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b4deff96085fe9a47b452f717af4f76c21144013
https://github.com/qemu/qemu/commit/b4deff96085fe9a47b452f717af4f76c21144013
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Reject add/sub w/ shifted byte early
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
and do_zzi_sat which are intended to reject an 8-bit shift of an
8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9594ed55b46210a863994563b00b80a4378476a6
https://github.com/qemu/qemu/commit/9594ed55b46210a863994563b00b80a4378476a6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Reject copy w/ shifted byte early
Remove the unparsed extractions in trans_CPY_{m,z}_i which are intended
to reject an 8-bit shift of an 8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-74-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 51ea303f5b2d383dff7f1fbc1851355932374408
https://github.com/qemu/qemu/commit/51ea303f5b2d383dff7f1fbc1851355932374408
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for ADD_zzi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-75-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f7f00587ee6cf00bcf9ff6de220b2aac6dd982f4
https://github.com/qemu/qemu/commit/f7f00587ee6cf00bcf9ff6de220b2aac6dd982f4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_zzi_sat
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-76-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1145ebf25f832d94ebbe3c07638c5182891fe395
https://github.com/qemu/qemu/commit/1145ebf25f832d94ebbe3c07638c5182891fe395
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_zzi_ool
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-77-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1a301305fa5422877ca13688537615d3ed75aa63
https://github.com/qemu/qemu/commit/1a301305fa5422877ca13688537615d3ed75aa63
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
Use these for the several varieties of floating-point
multiply-add instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-78-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1a3fff4dfdfa09118edab5496db19c0cdda1edc6
https://github.com/qemu/qemu/commit/1a3fff4dfdfa09118edab5496db19c0cdda1edc6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FMMLA
Being able to specify the feature predicate in TRANS_FEAT
makes it easier to split trans_FMMLA by element size,
which also happens to simplify the decode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-79-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a2fd9f71324f26194241fcdceca2a52efeec87e
https://github.com/qemu/qemu/commit/4a2fd9f71324f26194241fcdceca2a52efeec87e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move sve check into gen_gvec_fn_ppp
Combined with the check already present in gen_mov_p,
we can simplify some special cases in trans_AND_pppp
and trans_BIC_pppp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-80-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 03eb316406fb64977cb8d6a7fa475316f2b8b786
https://github.com/qemu/qemu/commit/03eb316406fb64977cb8d6a7fa475316f2b8b786
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement NOT (prediates) alias
This alias is defined on EOR (prediates). While the
same operation could be performed with NAND or NOR,
only bother with the official alias.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-81-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 880d749f08ddb4999aaf33e2c3acc30fc2a83578
https://github.com/qemu/qemu/commit/880d749f08ddb4999aaf33e2c3acc30fc2a83578
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for SEL_zpzz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-82-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 143e7e82cd9b6099f51cf4990fa3d9445bb83ce5
https://github.com/qemu/qemu/commit/143e7e82cd9b6099f51cf4990fa3d9445bb83ce5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for MOVPRFX
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-83-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b61fa19a21d5c11d1e36c6c274db6c9115d47072
https://github.com/qemu/qemu/commit/b61fa19a21d5c11d1e36c6c274db6c9115d47072
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FMLA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-84-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fac7a9d205b883830debb6e165781c74ef64887b
https://github.com/qemu/qemu/commit/fac7a9d205b883830debb6e165781c74ef64887b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for BFMLA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-85-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0c0e1b487db216946ec34f3de00702f9d3363ab5
https://github.com/qemu/qemu/commit/0c0e1b487db216946ec34f3de00702f9d3363ab5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
Rename the function to match gen_gvec_ool_arg_zzz,
and move to be adjacent. Split out gen_gvec_fpst_zzz
as a helper while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-86-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e93ddaf384f90c403c03f40f5f042220a8a29395
https://github.com/qemu/qemu/commit/e93ddaf384f90c403c03f40f5f042220a8a29395
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for DO_FP3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5e10dd43dcb94532de9da92163295fc2ea31fafb
https://github.com/qemu/qemu/commit/5e10dd43dcb94532de9da92163295fc2ea31fafb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FMUL_zzx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-88-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eddad2d37aae5f51150c042d25e9a87c33888451
https://github.com/qemu/qemu/commit/eddad2d37aae5f51150c042d25e9a87c33888451
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FTMAD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-89-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e702ec19af3555b5cf22070233b7ee9b6ed95cfe
https://github.com/qemu/qemu/commit/e702ec19af3555b5cf22070233b7ee9b6ed95cfe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into do_reduce
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-90-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 95262d73e141604ba9e13d7c21ebc4ac26c6e712
https://github.com/qemu/qemu/commit/95262d73e141604ba9e13d7c21ebc4ac26c6e712
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_reduce
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-91-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1523d7d445e1bbc30f1b184081a8d1a3a9200432
https://github.com/qemu/qemu/commit/1523d7d445e1bbc30f1b184081a8d1a3a9200432
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
Rename do_zz_fp to gen_gvec_fpst_arg_zz, and move up.
Split out gen_gvec_fpst_zz as a helper while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-92-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f5270696fe2ac7741879d701539558f59eee8efd
https://github.com/qemu/qemu/commit/f5270696fe2ac7741879d701539558f59eee8efd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Expand frint_fns for MO_8
Simplify indexing of this array. This will allow folding
of the illegal esz == 0 into the normal fn == NULL check.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-93-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 289557bebfc8c7fdaf342449fe6409d3e7848ed7
https://github.com/qemu/qemu/commit/289557bebfc8c7fdaf342449fe6409d3e7848ed7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
Rename the function to match other expansion function and
move to be adjacent. Split out gen_gvec_fpst_zzp as a
helper while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-94-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 835522f9f52533fa2f90c9c2030b408ac832ea5c
https://github.com/qemu/qemu/commit/835522f9f52533fa2f90c9c2030b408ac832ea5c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into do_frint_mode
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-95-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e823106aa4e750af6c9e707e7e5a09648446b7e4
https://github.com/qemu/qemu/commit/e823106aa4e750af6c9e707e7e5a09648446b7e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_frint_mode
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-96-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 13a4143777242d253c35dcac9bd8b306d5f6997e
https://github.com/qemu/qemu/commit/13a4143777242d253c35dcac9bd8b306d5f6997e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FLOGB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-97-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c5262e75e97169419b8118208c02ee7bc09aad1d
https://github.com/qemu/qemu/commit/c5262e75e97169419b8118208c02ee7bc09aad1d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_ppz_fp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-98-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f2b8a014fa3b1ffc69af1d4d7721e81ca842b11b
https://github.com/qemu/qemu/commit/f2b8a014fa3b1ffc69af1d4d7721e81ca842b11b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz
Rename the function to match other expansion functions and
move to be adjacent. Split out gen_gvec_fpst_zzzp as a
helper while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-99-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1cc6b1b9b7326c1d1efe7b7f8b25556ea2c60660
https://github.com/qemu/qemu/commit/1cc6b1b9b7326c1d1efe7b7f8b25556ea2c60660
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-100-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 07aaa02645532935838429c4efcb8a65e1204494
https://github.com/qemu/qemu/commit/07aaa02645532935838429c4efcb8a65e1204494
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FCADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-101-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 40b112157dbf864a72da7ee55214dc236d39f3dd
https://github.com/qemu/qemu/commit/40b112157dbf864a72da7ee55214dc236d39f3dd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Introduce gen_gvec_fpst_zzzzp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-102-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 74623d97c681e77637ab6573b529fb6c4c8bce9d
https://github.com/qemu/qemu/commit/74623d97c681e77637ab6573b529fb6c4c8bce9d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-103-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: de6016351a200a8ed1d2e2def4f2f97b131eedeb
https://github.com/qemu/qemu/commit/de6016351a200a8ed1d2e2def4f2f97b131eedeb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Move null function and sve check into do_fp_imm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-104-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 046316167b7a0b9a728c27ddaafbda9bf317b1c3
https://github.com/qemu/qemu/commit/046316167b7a0b9a728c27ddaafbda9bf317b1c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for DO_FP_IMM
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-105-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: afdab3f7d2e3a0461fb3f91ccf44693ed2097461
https://github.com/qemu/qemu/commit/afdab3f7d2e3a0461fb3f91ccf44693ed2097461
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for DO_FPCMP
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-106-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5a216a65371a1e9e17e9031def5b0b6c15c34dbc
https://github.com/qemu/qemu/commit/5a216a65371a1e9e17e9031def5b0b6c15c34dbc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Remove assert in trans_FCMLA_zzxz
Since 636ddeb15c0, we do not require rd == ra.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-107-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9410adc81851cda278ce493cd6bb18cef6a5b0fc
https://github.com/qemu/qemu/commit/9410adc81851cda278ce493cd6bb18cef6a5b0fc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for FCMLA_zzxz
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-108-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c5b18fafb44b8c983030868640b1e3a0564435d
https://github.com/qemu/qemu/commit/2c5b18fafb44b8c983030868640b1e3a0564435d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_narrow_extract
Rename from do_sve2_narrow_extract and hoist the sve2
check into the TRANS_FEAT macro.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-109-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2487bfeebee5131cdb96a4875670b9ca24f9a58f
https://github.com/qemu/qemu/commit/2487bfeebee5131cdb96a4875670b9ca24f9a58f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_shll_tb
Rename from do_sve2_shll_tb and hoist the sve2
check into the TRANS_FEAT macro.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-110-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e239ef18091615dfda5d9e5158e35ac320e476da
https://github.com/qemu/qemu/commit/e239ef18091615dfda5d9e5158e35ac320e476da
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_shr_narrow
Rename from do_sve2_shr_narrow and hoist the sve2
check into the TRANS_FEAT macro.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-111-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60fc9ff2966e403f826f18305727bb398fe4930d
https://github.com/qemu/qemu/commit/60fc9ff2966e403f826f18305727bb398fe4930d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_FMLAL_zzzw
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-112-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0c8ad2382aabbd759dff72be7281e649e32f24fb
https://github.com/qemu/qemu/commit/0c8ad2382aabbd759dff72be7281e649e32f24fb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use TRANS_FEAT for do_FMLAL_zzxw
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-113-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8f77a092ccd0a0cf2f8030222f68b45ac20a9a30
https://github.com/qemu/qemu/commit/8f77a092ccd0a0cf2f8030222f68b45ac20a9a30
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Add sve feature check for remaining trans_* functions
For all remaining trans_* functions that do not already
have a check, add one now.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-114-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f8df1f36be2b2b6be2ea8c74faa5306fd714699a
https://github.com/qemu/qemu/commit/f8df1f36be2b2b6be2ea8c74faa5306fd714699a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Remove aa64_sve check from before disas_sve
We now have individual checks on all insns within disas_sve.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-115-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6f700b78673d125575b2122ca6f85068dedb8cc4
https://github.com/qemu/qemu/commit/6f700b78673d125575b2122ca6f85068dedb8cc4
Author: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself as the maintainer for Hyper-V VMBus
This way there is some contact point for incoming patches,
and somebody to review and pick up them.
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Commit: 26080682eed5320e4700a090e74001fdbda5a72a
https://github.com/qemu/qemu/commit/26080682eed5320e4700a090e74001fdbda5a72a
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/hyperv/vmbus.c
M include/hw/hyperv/vmbus.h
Log Message:
-----------
hw/hyperv/vmbus: Remove unused vmbus_load/save_req()
vmbus_save_req() and vmbus_load_req() are not used.
Remove them to avoid maintaining dead code.
This essentially reverts commit 4dd8a7064b8a6527f99a62be11
("vmbus: add infrastructure to save/load vmbus requests").
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211106134155.582312-2-philmd@redhat.com>
[MSS: Remove also corresponding variables, which are now unused]
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Commit: 77890278323e1b48f39e7a48952bf2c1204a37bc
https://github.com/qemu/qemu/commit/77890278323e1b48f39e7a48952bf2c1204a37bc
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
Log Message:
-----------
.gitlab-ci.d/container-cross: Fix RISC-V container dependencies / stages
The "riscv64-debian-cross-container" job does not depend on any other
container job from the first stage, so we can move it to the first
stage, too.
The "riscv64-debian-test-cross-container" job needs the debian11
container, so we should add a proper "needs:" statement here.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220524093141.91012-1-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220527153603.887929-2-alex.bennee@linaro.org>
Commit: bd170739400bb46eae90a9d15357af77930b7d0e
https://github.com/qemu/qemu/commit/bd170739400bb46eae90a9d15357af77930b7d0e
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/crossbuilds.yml
Log Message:
-----------
.gitlab-ci.d/crossbuilds: Fix the dependency of the cross-i386-tci job
The cross-i386-tci job uses the fedora-i386-cross image, so we should make sure
that the corresponding job that builds it (the i386-fedora-cross-container job)
has finished before we start the TCI job.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524092600.89997-1-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-3-alex.bennee@linaro.org>
Commit: 9c010d3615e40655445c8d4646d84450f413f8e3
https://github.com/qemu/qemu/commit/9c010d3615e40655445c8d4646d84450f413f8e3
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/buildtest-template.yml
Log Message:
-----------
gitlab-ci: add meson JUnit test result into report
This allows the gitlab UI to show the test results in different ways,
see doc:
https://docs.gitlab.com/ee/ci/unit_test_reports.html#how-it-works
Previous we only reports avocado test results (.avocado_test_job_template),
with this change, the qemu/meson tests are also covered.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220525173411.612224-1-marcandre.lureau@redhat.com>
[AJB: expand the commit description]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-4-alex.bennee@linaro.org>
Commit: da38f4775ad9b3b68fe8c8edad902305f4eac863
https://github.com/qemu/qemu/commit/da38f4775ad9b3b68fe8c8edad902305f4eac863
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson.build: fix summary display of test compilers
The recent refactoring of configure.sh dropped a number of variables
we relied on for printing out information. Make it simpler.
Fixes: eebf199c09 (tests/tcg: invoke Makefile.target directly from QEMU's
makefile)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220527153603.887929-5-alex.bennee@linaro.org>
Commit: 98b12ba6bc7b930063c1f9ba9d452d306ce5ed6b
https://github.com/qemu/qemu/commit/98b12ba6bc7b930063c1f9ba9d452d306ce5ed6b
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/lcitool/refresh
Log Message:
-----------
tests/lcitool: fix up indentation to correct style
3 space indentation snuck into the initial commit. Clean it up before
we let it get established. I've also:
- removed unused os import
- added double lines between functions
- added some comments and grouped and sorted the generation stanzas
My lint tool is also recommending using f-strings but that requires
python 3.6.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-6-alex.bennee@linaro.org>
Commit: 96bceef25ed4246df0411db6274083b49c414f2d
https://github.com/qemu/qemu/commit/96bceef25ed4246df0411db6274083b49c414f2d
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M tests/docker/Makefile.include
M tests/docker/dockerfiles/debian-armhf-cross.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-armhf-cross with lcitool
Use lcitool to update debian-armhf-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-7-alex.bennee@linaro.org>
Commit: ec745ac41b0e0a2a6c644be07841071262cf33b6
https://github.com/qemu/qemu/commit/ec745ac41b0e0a2a6c644be07841071262cf33b6
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M tests/docker/Makefile.include
M tests/docker/dockerfiles/debian-armel-cross.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-armel-cross with lcitool
Use lcitool to update debian-armel-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-8-alex.bennee@linaro.org>
Commit: a2f21d79159aea4c8781fa31d09225fc4c51956c
https://github.com/qemu/qemu/commit/a2f21d79159aea4c8781fa31d09225fc4c51956c
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M tests/docker/Makefile.include
M tests/docker/dockerfiles/debian-mipsel-cross.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-mipsel-cross with lcitool
Use lcitool to update debian-mipsel-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-9-alex.bennee@linaro.org>
Commit: ca23b2869f7ffe56d24d303e343d5d82543f0b3f
https://github.com/qemu/qemu/commit/ca23b2869f7ffe56d24d303e343d5d82543f0b3f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M tests/docker/Makefile.include
M tests/docker/dockerfiles/debian-mips64el-cross.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-mips64el-cross with lcitool
Use lcitool to update debian-mips64el-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-10-alex.bennee@linaro.org>
Commit: caa6428937d9976eb6fd874350842a51b9f5859d
https://github.com/qemu/qemu/commit/caa6428937d9976eb6fd874350842a51b9f5859d
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M tests/docker/Makefile.include
M tests/docker/dockerfiles/debian-ppc64el-cross.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-ppc64el-cross with lcitool
Use lcitool to update debian-ppc64el-cross to a Debian 11 based system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-11-alex.bennee@linaro.org>
Commit: e1f6ec9130657bc2d76f98ef27ab4851cceeb9e8
https://github.com/qemu/qemu/commit/e1f6ec9130657bc2d76f98ef27ab4851cceeb9e8
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/containers.yml
M tests/docker/dockerfiles/debian-amd64.docker
M tests/lcitool/refresh
Log Message:
-----------
tests/docker: update debian-amd64 with lcitool
The one minor wrinkle we need to account for is the netmap support
still requires building from source. We also include cscope and GNU
global as they are used in one of the builds.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Luigi Rizzo <rizzo@iet.unipi.it>
Cc: Giuseppe Lettieri <g.lettieri@iet.unipi.it>
Cc: Vincenzo Maffione <v.maffione@gmail.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-12-alex.bennee@linaro.org>
Commit: 4674441b85fb1f8dea53eedebf598648f8216742
https://github.com/qemu/qemu/commit/4674441b85fb1f8dea53eedebf598648f8216742
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/optionrom/Makefile
Log Message:
-----------
configure: do not define or use the CPP variable
Just hardcode $(CC) -E, it should be enough.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-2-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-13-alex.bennee@linaro.org>
Commit: 09cda84ca0fd52f2104c70b66495ef480852098c
https://github.com/qemu/qemu/commit/09cda84ca0fd52f2104c70b66495ef480852098c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M Makefile
Log Message:
-----------
build: clean up ninja invocation
Fix an incorrect "@@:" and move "-d keepdepfile" to the NINJAFLAGS variable.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-3-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-14-alex.bennee@linaro.org>
Commit: 1ecfb4f31a8fd3cedaa81e1371b3caa62c856e8a
https://github.com/qemu/qemu/commit/1ecfb4f31a8fd3cedaa81e1371b3caa62c856e8a
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M Makefile
M scripts/mtest2make.py
Log Message:
-----------
build: add a more generic way to specify make->ninja dependencies
Let any make target specify ninja goals that needs to be built for it
(though selecting the goals is _not_ recursive on depending targets)
instead of having a custom mechanism only for "make check" and "make
bench".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-4-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-15-alex.bennee@linaro.org>
Commit: 691956c0d0e3da6a943775d18716e5b4fa811e36
https://github.com/qemu/qemu/commit/691956c0d0e3da6a943775d18716e5b4fa811e36
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
build: do a full build before running TCG tests
TCG tests need both QEMU and firmware to be built, so do "ninja all" before
trying to run them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-5-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-16-alex.bennee@linaro.org>
Commit: 1d44a2d46f8436da23cd00010f914eb61fcc2ef6
https://github.com/qemu/qemu/commit/1d44a2d46f8436da23cd00010f914eb61fcc2ef6
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/meson.build
Log Message:
-----------
configure, meson: move symlinking of ROMs to meson
This is useful because pc-bios/meson.build already has a list of all ROM
files, and thus does not need to use wildcards. The problems with
wildcards are mentioned above the definition of the LINKS variable,
but then the recommendation is disattended.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-6-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-17-alex.bennee@linaro.org>
Commit: c5042e7de886496f8f701175f081dce2591edfb2
https://github.com/qemu/qemu/commit/c5042e7de886496f8f701175f081dce2591edfb2
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/tcg/configure.sh
Log Message:
-----------
tests/tcg: correct target CPU for sparc32
We do not want v8plus for pure sparc32, as the difference with the V8 ABI
are only meaningful on 64-bit CPUs suh as ultrasparc; supersparc is the
best CPU to use for 32-bit.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-7-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-18-alex.bennee@linaro.org>
Commit: 2ae0e4433b9f03a11db2d12e88e7044b986877aa
https://github.com/qemu/qemu/commit/2ae0e4433b9f03a11db2d12e88e7044b986877aa
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M tests/Makefile.include
R tests/tcg/configure.sh
Log Message:
-----------
tests/tcg: merge configure.sh back into main configure script
tests/tcg/configure.sh has a complicated story.
In the beginning its code ran as part of the creation of config-target.mak
files, and that is where it placed the information on the target compiler.
However, probing for the buildability of TCG tests required multiple
inclusions of config-target.mak in the _main_ Makefile (not in
Makefile.target, which took care of building the QEMU executables in
the pre-Meson era), which polluted the namespace.
Thus, it was moved to a separate directory. It created small config-*.mak
files in $(BUILD_DIR)/tests/tcg. Those were also included multiple
times, but at least they were small and manageable; this was also an
important step in disentangling the TCG tests from Makefile.target.
Since then, Meson has allowed the configure script to go on a diet.
A few compilation tests survive (mostly for sanitizers) but these days
it mostly takes care of command line parsing, looking for tools, and
setting up the environment for Meson to do its stuff.
It's time to extend configure with the capability to build for more
than just one target: not just tests, but also firmware. As a first
step, integrate all the logic to find cross compilers in the configure
script, and move tests/tcg/configure.sh back there (though as a
separate loop, not integrated in the one that generates target
configurations for Meson).
tests/tcg is actually very close to being buildable as a standalone
project, so I actually expect the compiler tests to move back to
tests/tcg, as a "configure" script of sorts which would run at Make
time after the docker images are built. The GCC tree has a similar idea
of doing only bare-bones tree-wide configuration and leaving the rest
for Make time.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-8-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-19-alex.bennee@linaro.org>
Commit: 6bd6bf7edc0370d6df17975101204a33feae8eae
https://github.com/qemu/qemu/commit/6bd6bf7edc0370d6df17975101204a33feae8eae
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: add missing cross compiler fallbacks
The arm compiler can be used for armeb, and the sparc64 compiler
can be used for sparc.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-9-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-20-alex.bennee@linaro.org>
Commit: f113ce2ba683d78830166be3c4ef6f45cee9b320
https://github.com/qemu/qemu/commit/f113ce2ba683d78830166be3c4ef6f45cee9b320
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: handle host compiler in probe_target_compiler
In preparation for handling more binaries than just cc, handle
the case of "probe_target_compiler $cpu" directly in the function,
setting the target_* variables based on the ones that are used to
build QEMU. The clang check also needs to be moved after this
fallback.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517092616.1272238-10-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-21-alex.bennee@linaro.org>
Commit: f2aec0b6fda6ace5a10fd6c7cb50e240031a3989
https://github.com/qemu/qemu/commit/f2aec0b6fda6ace5a10fd6c7cb50e240031a3989
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: introduce --cross-prefix-*=
Also in preparation for handling more binaries from the cross binutils,
support an option --cross-prefix-ARCH. All cross_cc_* defaults are
replaced with cross_prefix_*; the cross_cc_* fallbacks are extended
to the cross-compilation prefix, but the compiler fallbacks remain
as well. This way, for example, --cross-cc-arm=arm-linux-gnueabihf-clang
also applies to armeb binaries.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-11-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-22-alex.bennee@linaro.org>
Commit: 9057464c5c5a947b3ad6795eab5ef8f699fccaba
https://github.com/qemu/qemu/commit/9057464c5c5a947b3ad6795eab5ef8f699fccaba
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: include more binutils in tests/tcg makefile
Firmware builds require paths to all the binutils; it is not enough to
use only cc, or even as/ld as in the case of tests/tcg/tricore.
Adjust the cross-compiler configurator to detect also ar, nm, objcopy,
ranlib and strip.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-12-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-23-alex.bennee@linaro.org>
Commit: 99d8b64fc301f451c3a9975f244d4d3742e239e4
https://github.com/qemu/qemu/commit/99d8b64fc301f451c3a9975f244d4d3742e239e4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: move symlink configuration earlier
Ensure that the pc-bios/optionrom and pc-bios/s390-ccw directory
exist at the time when we'll write out the compiler configuration
for them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-13-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-24-alex.bennee@linaro.org>
Commit: b818cb8e472e89b317fd0e7c00315b1d9fcdd00d
https://github.com/qemu/qemu/commit/b818cb8e472e89b317fd0e7c00315b1d9fcdd00d
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/netboot.mak
Log Message:
-----------
configure: enable cross-compilation of s390-ccw
While container-based cross compilers are not supported, this already makes
it possible to build s390-ccw on any machine that has s390x GCC and binutils
installed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-14-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-25-alex.bennee@linaro.org>
Commit: 38a1e45b4b73c474d2fa0124bee1bb32449d099b
https://github.com/qemu/qemu/commit/38a1e45b4b73c474d2fa0124bee1bb32449d099b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/optionrom/Makefile
Log Message:
-----------
configure: enable cross-compilation of optionrom
While container-based cross compilers are not supported, this already makes
it possible to build x86 optionroms on any machine that has an installation
of GCC and binutils for 32- or 64-bit x86.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-15-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-26-alex.bennee@linaro.org>
Commit: fcde237702cb3522607e0377721705c1832a4d1b
https://github.com/qemu/qemu/commit/fcde237702cb3522607e0377721705c1832a4d1b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
M pc-bios/vof/Makefile
Log Message:
-----------
configure: enable cross compilation of vof
While container-based cross compilers are not supported, this already
makes it possible to build vof on any machine that has an installation
of GCC and binutils for 32- or 64-bit PowerPC.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-16-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-27-alex.bennee@linaro.org>
Commit: 6fced171ec398727763d1b9075538f2f8642fd66
https://github.com/qemu/qemu/commit/6fced171ec398727763d1b9075538f2f8642fd66
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: remove unused variables from config-host.mak
The only compiler variable that is still needed is $(CC), for
contrib/plugins/Makefile. All firmware builds have their own
config-host.mak file.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220517092616.1272238-17-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220527153603.887929-28-alex.bennee@linaro.org>
Commit: 2f341aec42ed6a29a03cd2d8cac0dce219b309d8
https://github.com/qemu/qemu/commit/2f341aec42ed6a29a03cd2d8cac0dce219b309d8
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A .gitlab-ci.d/base.yml
M .gitlab-ci.d/qemu-project.yml
M docs/devel/ci-jobs.rst.inc
Log Message:
-----------
gitlab: introduce a common base job template
Currently job rules are spread across the various templates
and jobs, making it hard to understand exactly what runs in
what scenario. This leads to inconsistency in the rules and
increased maint burden.
The intent is that we introduce a common '.base_job_template'
which will have a general purpose 'rules:' block. No other
template or job should define 'rules:', but instead they must
rely on the inherited rules. To allow behaviour to be tweaked,
rules will be influenced by a number of variables with the
naming scheme 'QEMU_JOB_nnnn'.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220526110705.59952-2-berrange@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-29-alex.bennee@linaro.org>
Commit: 8505eac09c49a0103c9bc5fe2af6f81e3bddcaa6
https://github.com/qemu/qemu/commit/8505eac09c49a0103c9bc5fe2af6f81e3bddcaa6
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/base.yml
M .gitlab-ci.d/cirrus.yml
M docs/devel/ci-jobs.rst.inc
Log Message:
-----------
gitlab: convert Cirrus jobs to .base_job_template
This folds the Cirrus job rules into the base job
template, introducing two new variables
- QEMU_JOB_CIRRUS - identifies the job as making
use of Cirrus CI via cirrus-run
- QEMU_JOB_OPTIONAL - identifies the job as one
that is not run by default, primarily due to
resource constraints. It can be manually invoked
by users if they wish to validate that scenario.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220526110705.59952-3-berrange@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-30-alex.bennee@linaro.org>
Commit: dee526864913363d6000bc4fea75ff2588d1594a
https://github.com/qemu/qemu/commit/dee526864913363d6000bc4fea75ff2588d1594a
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/base.yml
M .gitlab-ci.d/static_checks.yml
M docs/devel/ci-jobs.rst.inc
Log Message:
-----------
gitlab: convert static checks to .base_job_template
This folds the static checks into using the base job
template rules, introducing one new variable
- QEMU_JOB_ONLY_FORKS - a job that should never run
on an upstream pipeline. The information it reports
is only applicable to contributors in a pre-submission
scenario, not time of merge.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220526110705.59952-4-berrange@redhat.com>
[AJB: fix typo]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-31-alex.bennee@linaro.org>
Commit: 02dfac821d03e11988a3c6deb68d17f7b2ccfffc
https://github.com/qemu/qemu/commit/02dfac821d03e11988a3c6deb68d17f7b2ccfffc
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/base.yml
M .gitlab-ci.d/buildtest-template.yml
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/container-cross.yml
M .gitlab-ci.d/container-template.yml
M .gitlab-ci.d/crossbuild-template.yml
M .gitlab-ci.d/windows.yml
M docs/devel/ci-jobs.rst.inc
Log Message:
-----------
gitlab: convert build/container jobs to .base_job_template
This converts the main build and container jobs to use the
base job rules, defining the following new variables
- QEMU_JOB_SKIPPED - jobs that are known to be currently
broken and should not be run. Can still be manually
launched if desired.
- QEMU_JOB_AVOCADO - jobs that run the Avocado integration
test harness.
- QEMU_JOB_PUBLISH - jobs that publish content after the
branch is merged upstream
As build-tools-and-docs runs on master we declare the requirement of
building amd64-debian-container optional as it should already exits
once we merge.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220526110705.59952-5-berrange@redhat.com>
[AJB: fix upstream typo, mention optional container req]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-32-alex.bennee@linaro.org>
Commit: 3725937af7eb812c770cc8e1aaea88e5d542feb7
https://github.com/qemu/qemu/commit/3725937af7eb812c770cc8e1aaea88e5d542feb7
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/base.yml
M docs/devel/ci-jobs.rst.inc
Log Message:
-----------
gitlab: don't run CI jobs in forks by default
To preserve CI shared runner credits we don't want to run
pipelines on every push.
This sets up the config so that pipelines are never created
for contributors by default. To override this the QEMU_CI
variable can be set to a non-zero value. If set to 1, the
pipeline will be created but all jobs will remain manually
started. The contributor can selectively run jobs that they
care about. If set to 2, the pipeline will be created and
all jobs will immediately start.
This behavior can be controlled using push variables
git push -o ci.variable=QEMU_CI=1
To make this more convenient define an alias
git config --local alias.push-ci "push -o ci.variable=QEMU_CI=1"
git config --local alias.push-ci-now "push -o ci.variable=QEMU_CI=2"
Which lets you run
git push-ci
to create the pipeline, or
git push-ci-now
to create and run the pipeline
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220526110705.59952-6-berrange@redhat.com>
[AJB: fix typo, replicate alias tips in ci.rst]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220527153603.887929-33-alex.bennee@linaro.org>
Commit: 75ec4bb1c84cc8602298d69e66c2e4ff4c92b361
https://github.com/qemu/qemu/commit/75ec4bb1c84cc8602298d69e66c2e4ff4c92b361
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/devel/ci-jobs.rst.inc
M docs/devel/ci.rst
M docs/devel/submitting-a-patch.rst
M docs/devel/testing.rst
Log Message:
-----------
docs/devel: clean-up the CI links in the docs
There where some broken links so fix those up with proper references
to the devel docs. I also did a little light copy-editing to reflect
the current state and broke up a paragraph to reduce the "wall of
text" effect.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220527153603.887929-34-alex.bennee@linaro.org>
Commit: 5b69520f20271a9185d6cbe43415139306731d7f
https://github.com/qemu/qemu/commit/5b69520f20271a9185d6cbe43415139306731d7f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/cpu.c
Log Message:
-----------
target/m68k: Clear mach in m68k_cpu_disas_set_info
Zero selects all cpu features in disas/m68k.c,
which is really what we want -- not limited to 68040.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220430170225.326447-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 7a54af1eeb7884462769a6d05921abb32296ff93
https://github.com/qemu/qemu/commit/7a54af1eeb7884462769a6d05921abb32296ff93
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Enable halt insn for 68060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220430170225.326447-3-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 79a3de047a962682cbeb8e28a602da32158d7441
https://github.com/qemu/qemu/commit/79a3de047a962682cbeb8e28a602da32158d7441
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
M target/m68k/op_helper.c
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Raise the TRAPn exception with the correct pc
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 5bb68425c4f65319c856ffeb9488dc253eaf9a54
https://github.com/qemu/qemu/commit/5bb68425c4f65319c856ffeb9488dc253eaf9a54
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Switch over exception type in m68k_interrupt_all
Replace an if ladder with a switch for clarity.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-3-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 25e83e73ebc8d744e7c7ecdd35d7abae04dae2c8
https://github.com/qemu/qemu/commit/25e83e73ebc8d744e7c7ecdd35d7abae04dae2c8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Fix coding style in m68k_interrupt_all
Add parenthesis around & vs &&.
Remove assignment to sr in function call argument -- note that
sr is unused after the call, so the assignment was never needed,
only the result of the & expression.
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-4-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 1707a91f985734367a34b05c78ac34e2ff890a69
https://github.com/qemu/qemu/commit/1707a91f985734367a34b05c78ac34e2ff890a69
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
Log Message:
-----------
linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-5-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 1ae93ce89282c2653386ad59c4aa21ec9d79245c
https://github.com/qemu/qemu/commit/1ae93ce89282c2653386ad59c4aa21ec9d79245c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Remove retaddr in m68k_interrupt_all
The only value this variable holds is now env->pc.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-6-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: b65807b8846c1fb8b916cfa1f6b3ec1ab8beb87e
https://github.com/qemu/qemu/commit/b65807b8846c1fb8b916cfa1f6b3ec1ab8beb87e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
M target/m68k/cpu.h
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Fix address argument for EXCP_CHK
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), CHK, CHK2 (and others)
are supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
Create a raise_exception_format2 function to centralize recording
of the trapping pc in mmu.ar, plus advancing to the next insn.
Update m68k_interrupt_all to pass mmu.ar to do_stack_frame.
Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the
kernel does in trap_c().
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-7-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: dbd0b2f54941a402e3a5631d0e256e327a2149c9
https://github.com/qemu/qemu/commit/dbd0b2f54941a402e3a5631d0e256e327a2149c9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
M target/m68k/helper.h
M target/m68k/op_helper.c
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Zero Div (and others)
is supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
While the N, Z and V flags are documented to be undefine on DIV0,
the C flag is documented as always cleared.
Update helper_div* to take the instruction length as an argument
and use raise_exception_format2. Hoist the reset of the C flag
above the division by zero check.
Update m68k_interrupt_all to pass mmu.ar to do_stack_frame.
Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the
kernel does in trap_c().
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-8-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 273ba0e1a390df6dc333820c4380dc17919a9fd0
https://github.com/qemu/qemu/commit/273ba0e1a390df6dc333820c4380dc17919a9fd0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
M target/m68k/op_helper.c
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Fix address argument for EXCP_TRACE
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to record the trapping
pc in env->mmu.ar. Update m68k_interrupt_all to pass the
value to do_stack_frame. Update cpu_loop to handle EXCP_TRACE.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-9-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: dc6ef826d76c3ea0540cd4fb745f1202f54cce35
https://github.com/qemu/qemu/commit/dc6ef826d76c3ea0540cd4fb745f1202f54cce35
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Fix stack frame for EXCP_ILLEGAL
According to the M68040 Users Manual, section 8.4.1, Four word
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-10-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: ba54636066bcd04907c2a7e0d8d1631f4a68ee56
https://github.com/qemu/qemu/commit/ba54636066bcd04907c2a7e0d8d1631f4a68ee56
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/m68k/cpu_loop.c
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/m68k/op_helper.c
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Implement TRAPcc
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-11-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 939f8c1654e4406873a2f6dc4e3ad837f25be3c9
https://github.com/qemu/qemu/commit/939f8c1654e4406873a2f6dc4e3ad837f25be3c9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Implement TPF in terms of TRAPcc
TPF stands for "trap false", and is a long-form nop for ColdFire.
Re-use the immediate consumption code from trapcc; the insn will
already expand to a nop because of the TCG_COND_NEVER test
within do_trapcc.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-12-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 6892bf922d113e220f5da86fb6d07da731e4dfa8
https://github.com/qemu/qemu/commit/6892bf922d113e220f5da86fb6d07da731e4dfa8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Implement TRAPV
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-13-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 5fff5bc1c8fb06e45e24553048a7c6b779d4dea9
https://github.com/qemu/qemu/commit/5fff5bc1c8fb06e45e24553048a7c6b779d4dea9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Implement FTRAPcc
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-14-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 21955ada078f64f8ff2ba6d30d6d73608413e35e
https://github.com/qemu/qemu/commit/21955ada078f64f8ff2ba6d30d6d73608413e35e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/tcg/m68k/Makefile.target
A tests/tcg/m68k/trap.c
Log Message:
-----------
tests/tcg/m68k: Add trap.c
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-15-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: d5ebc33c1eceff936fe029b0f49aa835a2dcff31
https://github.com/qemu/qemu/commit/d5ebc33c1eceff936fe029b0f49aa835a2dcff31
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/strace.c
Log Message:
-----------
linux-user/strace: Use is_error in print_syscall_err
Errors are not all negative numbers: use is_error.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-16-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 7aed7a4882fee0809b13c9d8092f4deaf1ca6c6f
https://github.com/qemu/qemu/commit/7aed7a4882fee0809b13c9d8092f4deaf1ca6c6f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M linux-user/strace.list
Log Message:
-----------
linux-user/strace: Adjust get_thread_area for m68k
Unlike i386, m68k get_thread_area has no arguments.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-17-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 356b83753530a4bc7cee7fd508d40d563e4ccc72
https://github.com/qemu/qemu/commit/356b83753530a4bc7cee7fd508d40d563e4ccc72
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/m68k/helper.h
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Mark helper_raise_exception as noreturn
Also mark raise_exception_ra and raise_exception, lest we
generate a warning about helper_raise_exception returning.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-18-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: ef9b9c3ec233892e44113c38bd91a4574cd013d4
https://github.com/qemu/qemu/commit/ef9b9c3ec233892e44113c38bd91a4574cd013d4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/tcg/tcg-op.h
Log Message:
-----------
tcg: Add tcg_gen_mov_ptr
Add an interface to perform moves between TCGv_ptr.
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7c54241164238988f48dd99cfacea6183ef758b3
https://github.com/qemu/qemu/commit/7c54241164238988f48dd99cfacea6183ef758b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
We wanted the VPSRAQ variant with the scalar vector shift operand,
not the variant with an immediate operand.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1022
Fixes: 47b331b2a8da ("tcg/i386: Implement avx512 scalar shift")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cdfb02a5f24480e94af9536541da636852106955
https://github.com/qemu/qemu/commit/cdfb02a5f24480e94af9536541da636852106955
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Fix illegal insn from out-of-range shli
The masking in tcg_out_shl was incorrect, producing an
illegal instruction, rather than merely unspecified results
for the out-of-range shift.
Tested-by: Joel Stanley <joel@jms.id.au>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1051
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 27aa990cd251fc1910957509a60f0d335f468bff
https://github.com/qemu/qemu/commit/27aa990cd251fc1910957509a60f0d335f468bff
Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/s390x/cpu_features_def.h.inc
M target/s390x/gen-features.c
M target/s390x/tcg/translate.c
Log Message:
-----------
s390: Typo fix FLOATING_POINT_SUPPPORT_ENH
One less P needed.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20220523115123.150340-1-dgilbert@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d21bd8c7add043d1c4e0a51115b16ba1bc3eab69
https://github.com/qemu/qemu/commit/d21bd8c7add043d1c4e0a51115b16ba1bc3eab69
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/s390x/s390-virtio-ccw.c
Log Message:
-----------
hw/s390x/s390-virtio-ccw: Improve the machine description string
The machine name already contains the words "ccw" and "virtio", so
using "VirtIO-ccw" in the description likely does not really help
the average user to get an idea what this machine type is about.
Thus let's switch to "Virtual s390x machine" now, since "virtual
machine" should be a familiar term, and "s390x" signals that this
is about 64-bit guests (unlike S390 which could mean that it is
31-bit only).
Also expand "v" to "version", since this makes it easier to use
this macro also with non-numeric machine names in downstream.
Message-Id: <20220506065026.513590-1-thuth@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c4b5ec29fb012256065e55df6b0500b4ef530327
https://github.com/qemu/qemu/commit/c4b5ec29fb012256065e55df6b0500b4ef530327
Author: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x: kvm: Honor storage keys during emulation
Storage key controlled protection is currently not honored when
emulating instructions.
If available, enable key protection for the MEM_OP ioctl, thereby
enabling it for the s390_cpu_virt_mem_* functions, when using kvm.
As a result, the emulation of the following instructions honors storage
keys:
* CLP
The Synch I/O CLP command would need special handling in order
to support storage keys, but is currently not supported.
* CHSC
Performing commands asynchronously would require special
handling, but commands are currently always synchronous.
* STSI
* TSCH
Must (and does) not change channel if terminated due to
protection.
* MSCH
Suppressed on protection, works because fetching instruction.
* SSCH
Suppressed on protection, works because fetching instruction.
* STSCH
* STCRW
Suppressed on protection, this works because no partial store is
possible, because the operand cannot span multiple pages.
* PCISTB
* MPCIFC
* STPCIFC
Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Message-Id: <20220506153956.2217601-3-scgl@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 41c27b432ae3d83c18d5b5dd8dde2245bbc0c583
https://github.com/qemu/qemu/commit/41c27b432ae3d83c18d5b5dd8dde2245bbc0c583
Author: Eric Farman <farman@linux.ibm.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update s390 vhost entries
Commit 7a523d96a0 ("virtio-ccw: move vhost_ccw_scsi to a separate file")
introduced a new file hw/s390x/vhost-scsi-ccw.c, which received a
couple comments [1][2] to update MAINTAINERS that were missed.
Fix that by making the vhost CCW entries a wildcard.
[1]
https://lore.kernel.org/r/d8d2bbd5021076bdba444d31a6da74f507baede3.camel@linux.ibm.com/
[2] https://lore.kernel.org/r/87k0c4gb9f.fsf@redhat.com/
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20220525145814.2750501-1-farman@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9ae7ae36bbcecc69edfe59994ba8d7ec4f0fa33d
https://github.com/qemu/qemu/commit/9ae7ae36bbcecc69edfe59994ba8d7ec4f0fa33d
Author: Gautam Agrawal <gautamnagrawal@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
A tests/tcg/multiarch/overflow.c
Log Message:
-----------
tests/tcg: Test overflow conditions
Add a test to check for overflow conditions in s390x.
This patch is based on the following patches :
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
Signed-off-by: Gautam Agrawal <gautamnagrawal@gmail.com>
Message-Id: <20220531183524.40948-1-gautamnagrawal@gmail.com>
[thuth: Move overflow.c to tests/tcg/multiarch/ to make it generic]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 6b669c52d1dc77acfd9bc715ca7202fddc00f072
https://github.com/qemu/qemu/commit/6b669c52d1dc77acfd9bc715ca7202fddc00f072
Author: Hailiang Zhang <zhanghailiang@xfusion.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Change my email address
The zhang.zhanghailiang@huawei.com email address has been
stopped. Change it to my new email address.
Signed-off-by: Hailiang Zhang <zhanghailiang@xfusion.com>
Message-Id: <20211214075424.6920-1-zhanghailiang@xfusion.com>
Acked-by: Gonglei <arei.gonglei@huawei.com>
Acked-by: Zhang Chen <chen.zhang@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 27ed9ad456ff208f822e71718bdd1c5749d63553
https://github.com/qemu/qemu/commit/27ed9ad456ff208f822e71718bdd1c5749d63553
Author: Wenchao Wang <wenchao.wang@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update maintainers for Guest x86 HAXM CPUs
Clean up the maintainer list.
Reviewed-by: Hang Yuan <hang.yuan@intel.com>
Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Message-Id:
<DM6PR11MB4090A58ACCA4AD8C752AEEA587199@DM6PR11MB4090.namprd11.prod.outlook.com>
[thuth: Note: Colin Xu's address bounces]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ae3b620c8b9780815815edbd8fd144fe144f5836
https://github.com/qemu/qemu/commit/ae3b620c8b9780815815edbd8fd144fe144f5836
Author: Miaoqian Lin <linmq006@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/npcm7xx_pwm-test.c
Log Message:
-----------
qtest/npcm7xx_pwm-test: Fix memory leak in mft_qom_set
g_strdup_printf() allocated memory for path, we should free it with
g_free() when no longer needed.
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-Id: <20220531080921.4704-1-linmq006@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 28efe145abd1357ea56fce4f02f5a9ecfc64ed7b
https://github.com/qemu/qemu/commit/28efe145abd1357ea56fce4f02f5a9ecfc64ed7b
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/qtest/vhost-user-test.c
Log Message:
-----------
tests/qtest: use g_autofree for test_server_create_chr
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220524154056.2896913-12-alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 10af77b635e4257226d65aabbfa3b77cb91e475e
https://github.com/qemu/qemu/commit/10af77b635e4257226d65aabbfa3b77cb91e475e
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M qemu-options.hx
M softmmu/vl.c
Log Message:
-----------
ui: Remove deprecated parameters of the "-display sdl" option
Dropping these deprecated parameters simplifies further refactoring
(e.g. QAPIfication is easier without underscores in the name).
Message-Id: <20220519155625.1414365-2-thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 339d913ecffe7c76e20344e5a6b8b753e19f17a4
https://github.com/qemu/qemu/commit/339d913ecffe7c76e20344e5a6b8b753e19f17a4
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/sysemu/sysemu.h
M qapi/ui.json
M softmmu/globals.c
M softmmu/vl.c
M ui/sdl2.c
Log Message:
-----------
ui: Switch "-display sdl" to use the QAPI parser
The "-display sdl" option still uses a hand-crafted parser for its
parameters since we didn't want to drag an interface we considered
somewhat flawed into the QAPI schema. Since the flaws are gone now,
it's time to QAPIfy.
This introduces the new "DisplaySDL" QAPI struct that is used to hold
the parameters that are unique to the SDL display. The only specific
parameter is currently "grab-mod" that is used to specify the required
modifier keys to escape from the mouse grabbing mode.
Message-Id: <20220519155625.1414365-3-thuth@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8341fb187027e6f064590283234a43122582ccf5
https://github.com/qemu/qemu/commit/8341fb187027e6f064590283234a43122582ccf5
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M qemu-options.hx
M softmmu/vl.c
Log Message:
-----------
ui: Remove deprecated options "-sdl" and "-curses"
We have "-sdl" and "-curses", but no "-gtk" and no "-cocoa" ...
these old-style options are rather confusing than helpful nowadays.
Now that the deprecation period is over, let's remove them, so we
get a cleaner interface (where "-display" is the only way to select
the user interface).
Message-Id: <20220519155625.1414365-4-thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 992ed07024c10c0be08df302e3a6967dea3bc211
https://github.com/qemu/qemu/commit/992ed07024c10c0be08df302e3a6967dea3bc211
Author: Dmitry Tikhov <ddtikhov@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ns.c
Log Message:
-----------
hw/nvme: fix narrowing conversion
Since nlbas is of type int, it does not work with large namespace size
values, e.g., 9 TB size of file backing namespace and 8 byte metadata
with 4096 bytes lbasz gives negative nlbas value, which is later
promoted to negative int64_t type value and results in negative
ns->moff which breaks namespace
Signed-off-by: Dmitry Tikhov <ddtikhov@gmail.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: 55ecfadd581236a5fd390752b4ed7a6cba35f656
https://github.com/qemu/qemu/commit/55ecfadd581236a5fd390752b4ed7a6cba35f656
Author: Dmitry Tikhov <d.tihov@yadro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: add missing return statement
Since there is no return after nvme_dsm_cb invocation, metadata
associated with non-zero block range is currently zeroed. Also this
behaviour leads to segfault since we schedule iocb->bh two times.
First when entering nvme_dsm_cb with iocb->idx == iocb->nr and
second because of missing return on call stack unwinding by calling
blk_aio_pwrite_zeroes and subsequent nvme_dsm_cb callback.
Fixes: d7d1474fd85d ("hw/nvme: reimplement dsm to allow cancellation")
Signed-off-by: Dmitry Tikhov <d.tihov@yadro.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: c0c1285f6a72a0897cdb22c50df8898d96b3d9e5
https://github.com/qemu/qemu/commit/c0c1285f6a72a0897cdb22c50df8898d96b3d9e5
Author: Dmitry Tikhov <d.tihov@yadro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: fix copy cmd for pi enabled namespaces
Current implementation have problem in the read part of copy command.
Because there is no metadata mangling before nvme_dif_check invocation,
reftag error could be thrown for blocks of namespace that have not been
previously written to.
Signed-off-by: Dmitry Tikhov <d.tihov@yadro.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: d772a01e75d892afe5afd7874339f4b4064e3fda
https://github.com/qemu/qemu/commit/d772a01e75d892afe5afd7874339f4b4064e3fda
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: fix smart aen
Pass the right constant to nvme_smart_event(). The NVME_AER* values hold
the bit position in the SMART byte, not the shifted value that we expect
it to be in nvme_smart_event().
Fixes: c62720f137df ("hw/block/nvme: trigger async event during injecting smart
warning")
Acked-by: zhenwei pi <pizhenwei@bytedance.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: add090394bad8ae962ebb8bfa059328b9cf12d03
https://github.com/qemu/qemu/commit/add090394bad8ae962ebb8bfa059328b9cf12d03
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/nvme.h
M hw/nvme/subsys.c
Log Message:
-----------
hw/nvme: enforce common serial per subsystem
The Identify Controller Serial Number (SN) is the serial number for the
NVM subsystem and must be the same across all controller in the NVM
subsystem.
Enforce this.
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: d08f0217bd4b3cc2d8a243f08b4f7b1412b662fe
https://github.com/qemu/qemu/commit/d08f0217bd4b3cc2d8a243f08b4f7b1412b662fe
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/about/deprecated.rst
M hw/core/machine.c
M hw/nvme/ns.c
Log Message:
-----------
hw/nvme: do not auto-generate eui64
We cannot provide auto-generated unique or persistent namespace
identifiers (EUI64, NGUID, UUID) easily. Since 6.1, namespaces have been
assigned a generated EUI64 of the form "52:54:00:<namespace counter>".
This is will be unique within a QEMU instance, but not globally.
Revert that this is assigned automatically and immediately deprecate the
compatibility parameter. Users can opt-in to this with the
`eui64-default=on` device parameter or set it explicitly with
`eui64=UINT64`.
Cc: libvir-list@redhat.com
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: dd41a0cf73fea6e1f23521fe9c4fde26d6d6d59a
https://github.com/qemu/qemu/commit/dd41a0cf73fea6e1f23521fe9c4fde26d6d6d59a
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ns.c
Log Message:
-----------
hw/nvme: do not auto-generate uuid
Do not default to generate an UUID for namespaces if it is not
explicitly specified.
This is a technically a breaking change in behavior. However, since the
UUID changes on every VM launch, it is not spec compliant and is of
little use since the UUID cannot be used reliably anyway and the
behavior prior to this patch must be considered buggy.
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: ead6423808540bb7c3dbf290ff0dc4e0cea8f27f
https://github.com/qemu/qemu/commit/ead6423808540bb7c3dbf290ff0dc4e0cea8f27f
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: do not report null uuid
Do not report the "null uuid" (all zeros) in the namespace
identification descriptors.
Reported-by: Luis Chamberlain <mcgrof@kernel.org>
Reported-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: 2025514278cb31f277f79712c4b20b16b0a09077
https://github.com/qemu/qemu/commit/2025514278cb31f277f79712c4b20b16b0a09077
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: bump firmware revision
The Linux kernel quirks the QEMU NVMe controller pretty heavily because
of the namespace identifier mess. Since this is now fixed, bump the
firmware revision number to allow the quirk to be disabled for this
revision.
As of now, bump the firmware revision number to be equal to the QEMU
release version number.
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: 7518b08d9cd50168193ef1b47b8549ffee15c28d
https://github.com/qemu/qemu/commit/7518b08d9cd50168193ef1b47b8549ffee15c28d
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
hw/nvme: deprecate the use-intel-id compatibility parameter
Since version 5.2 commit 6eb7a071292a ("hw/block/nvme: change controller
pci id"), the emulated NVMe controller has defaulted to a non-Intel PCI
identifier.
Deprecate the compatibility parameter so we can get rid of it once and
for all.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: 2c8ed5bdfe797ce19824e5bbc64a13b048e3298d
https://github.com/qemu/qemu/commit/2c8ed5bdfe797ce19824e5bbc64a13b048e3298d
Author: Dmitry Tikhov <d.tihov@yadro.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/nvme/dif.c
Log Message:
-----------
hw/nvme: add new command abort case
NVMe command set specification for end-to-end data protection formatted
namespace states:
o If the Reference Tag Check bit of the PRCHK field is set to ‘1’ and
the namespace is formatted for Type 3 protection, then the
controller:
▪ should not compare the protection Information Reference Tag
field to the computed reference tag; and
▪ may ignore the ILBRT and EILBRT fields. If a command is
aborted as a result of the Reference Tag Check bit of the
PRCHK field being set to ‘1’, then that command should be
aborted with a status code of Invalid Protection Information,
but may be aborted with a status code of Invalid Field in
Command.
Currently qemu compares reftag in the nvme_dif_prchk function whenever
Reference Tag Check bit is set in the command. For type 3 namespaces
however, caller of nvme_dif_prchk - nvme_dif_check does not increment
reftag for each subsequent logical block. That way commands incorporating
more than one logical block for type 3 formatted namespaces with reftag
check bit set, always fail with End-to-end Reference Tag Check Error.
Comply with spec by handling case of set Reference Tag Check
bit in the type 3 formatted namespace.
Fixes: 146f720c5563 ("hw/block/nvme: end-to-end data protection")
Signed-off-by: Dmitry Tikhov <d.tihov@yadro.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Commit: c69e9e2e0bc25fece1855b585728b75a8a2d7101
https://github.com/qemu/qemu/commit/c69e9e2e0bc25fece1855b585728b75a8a2d7101
Author: Stephen Michael Jothen <sjothen@gmail.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386/tcg: Fix masking of real-mode addresses with A20 bit
The correct A20 masking is done if paging is enabled (protected mode) but it
seems to have been forgotten in real mode. For example from the AMD64 APM Vol. 2
section 1.2.4:
> If the sum of the segment base and effective address carries over into bit 20,
> that bit can be optionally truncated to mimic the 20-bit address wrapping of
> the
> 8086 processor by using the A20M# input signal to mask the A20 address bit.
Most BIOSes will enable the A20 line on boot, but I found by disabling the A20
line
afterwards, the correct wrapping wasn't taking place.
`handle_mmu_fault' in target/i386/tcg/sysemu/excp_helper.c seems to be the
culprit.
In real mode, it fills the TLB with the raw unmasked address. However, for the
protected mode, the `mmu_translate' function does the correct A20 masking.
The fix then should be to just apply the A20 mask in the first branch of the if
statement.
Signed-off-by: Stephen Michael Jothen <sjothen@gmail.com>
Message-Id: <Yo5MUMSz80jXtvt9@air-old.local>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8a732fbe341a4f953e4258ef73c7cfc006ea0a2e
https://github.com/qemu/qemu/commit/8a732fbe341a4f953e4258ef73c7cfc006ea0a2e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
Log Message:
-----------
build: add a "make modules" target
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a269ea116874f98b1bff47739399846b588beb5f
https://github.com/qemu/qemu/commit/a269ea116874f98b1bff47739399846b588beb5f
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Fix wrong count setting
The previous patch used wrong count setting with index value, which got wrong
value from CPUID(EAX=12,ECX=0):EAX. So the SGX1 instruction can't be exposed
to VM and the SGX decice can't work in VM.
Fixes: d19d6ffa0710 ("target/i386: introduce helper to access supported CPUID")
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220530131834.1222801-1-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c1042fe666552af091f0ee769b125d6db64e12b9
https://github.com/qemu/qemu/commit/c1042fe666552af091f0ee769b125d6db64e12b9
Author: Jose R. Ziviani <jziviani@suse.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M hw/display/qxl.c
M hw/display/vhost-user-gpu-pci.c
M hw/display/vhost-user-gpu.c
M hw/display/vhost-user-vga.c
M hw/display/virtio-gpu-base.c
M hw/display/virtio-gpu-gl.c
M hw/display/virtio-gpu-pci-gl.c
M hw/display/virtio-gpu-pci.c
M hw/display/virtio-gpu.c
M hw/display/virtio-vga-gl.c
M hw/display/virtio-vga.c
M hw/s390x/virtio-ccw-gpu.c
M hw/usb/ccid-card-emulated.c
M hw/usb/ccid-card-passthru.c
M hw/usb/host-libusb.c
M hw/usb/redirect.c
M include/qemu/module.h
M scripts/modinfo-generate.py
Log Message:
-----------
modules: introduces module_kconfig directive
module_kconfig is a new directive that should be used with module_obj
whenever that module depends on the Kconfig to be enabled.
When the module is enabled in Kconfig we are sure that its dependencies
will be enabled as well, thus the module will be loaded without any
problem.
The correct way to use module_kconfig is by passing the Kconfig option
to module_kconfig (or the *config-devices.mak without CONFIG_).
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
Signed-off-by: Dario Faggioli <dfaggioli@suse.com>
Message-Id: <165369002370.5857.12150544416563557322.stgit@work>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8ca2eca85abafd977e10e813c1de1b2720478327
https://github.com/qemu/qemu/commit/8ca2eca85abafd977e10e813c1de1b2720478327
Author: Jose R. Ziviani <jziviani@suse.de>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M meson.build
M scripts/modinfo-generate.py
Log Message:
-----------
modules: generates per-target modinfo
This patch changes the way modinfo is generated and built. Instead of
one modinfo.c it generates one modinfo-<target>-softmmu.c per target. It
aims a fine-tune control of modules by configuring Kconfig.
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
Signed-off-by: Dario Faggioli <dfaggioli@suse.com>
Message-Id: <165369003038.5857.13084289285185196779.stgit@work>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3874c47f920684de8aff056f97a06cb6be0ad776
https://github.com/qemu/qemu/commit/3874c47f920684de8aff056f97a06cb6be0ad776
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M replay/replay.c
Log Message:
-----------
replay: fix event queue flush for qemu shutdown
This patch fixes event queue flush in the case of emulator
shutdown. replay_finish_events should be called when replay_mode
is not cleared.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165364836758.688121.7959245442743676491.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 66ca1a3ed4951b0dbd99ac190c2c311cad439d01
https://github.com/qemu/qemu/commit/66ca1a3ed4951b0dbd99ac190c2c311cad439d01
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M include/sysemu/cpu-timers.h
M softmmu/icount.c
M stubs/icount.c
M util/async.c
Log Message:
-----------
replay: notify vCPU when BH is scheduled
vCPU execution should be suspended when new BH is scheduled.
This is needed to avoid guest timeouts caused by the long cycles
of the execution. In replay mode execution may hang when
vCPU sleeps and block event comes to the queue.
This patch adds notification which wakes up vCPU or interrupts
execution of guest code.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
--
v2: changed first_cpu to current_cpu (suggested by Richard Henderson)
v4: moved vCPU notification to aio_bh_enqueue (suggested by Paolo Bonzini)
Message-Id: <165364837317.688121.17680519919871405281.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f3b5335344efd7df93669ddf6d0f51cad7dd8efb
https://github.com/qemu/qemu/commit/f3b5335344efd7df93669ddf6d0f51cad7dd8efb
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M accel/tcg/tcg-accel-ops-icount.c
M docs/replay.txt
M include/sysemu/replay.h
M replay/replay-events.c
M replay/replay-internal.h
M replay/replay-snapshot.c
M replay/replay.c
M softmmu/icount.c
Log Message:
-----------
replay: rewrite async event handling
This patch decouples checkpoints and async events.
It was a tricky part of replay implementation. Now it becomes
much simpler and easier to maintain.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165364837856.688121.8785039478408995979.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8dc6c84c25e68e7852219b6c993749c503b835e8
https://github.com/qemu/qemu/commit/8dc6c84c25e68e7852219b6c993749c503b835e8
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M replay/replay-events.c
M replay/replay-internal.h
M replay/replay-snapshot.c
M replay/replay.c
Log Message:
-----------
replay: simplify async event processing
This patch joins replay event id and async event id into single byte in the log.
It makes processing a bit faster and log a bit smaller.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
--
v2: minor enum fixes (suggested by Richard Henderson)
Message-Id: <165364838393.688121.8191379555130516329.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: afbdd0ed5c5cf89fd34605d742cd2365fda70129
https://github.com/qemu/qemu/commit/afbdd0ed5c5cf89fd34605d742cd2365fda70129
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/devel/index-tcg.rst
A docs/devel/replay.rst
R docs/devel/replay.txt
Log Message:
-----------
docs: convert docs/devel/replay page to rst
This patch converts prior .txt replay devel documentation to .rst.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165364839013.688121.11935249420738873044.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ff0c1bf606d9c50a57aaead04456bd8b6f36b3c4
https://github.com/qemu/qemu/commit/ff0c1bf606d9c50a57aaead04456bd8b6f36b3c4
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M docs/devel/replay.rst
R docs/replay.txt
M docs/system/index.rst
A docs/system/replay.rst
Log Message:
-----------
docs: move replay docs to docs/system/replay.rst
This patch adds replay description page, converting prior
text from docs/replay.txt.
The text was also updated and some sections were moved
to devel part of the docs.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165364839601.688121.5131456980322853233.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6fb13889d61f41e532eacee5a923150dee1a72e3
https://github.com/qemu/qemu/commit/6fb13889d61f41e532eacee5a923150dee1a72e3
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/avocado/replay_linux.py
Log Message:
-----------
tests/avocado: update replay_linux test
This patch updates replay_linux test to make it compatible with
new LinuxTest class.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <165364840253.688121.10404266209986316381.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a184c8c7b2dfbd655ecaa39dfa0a58bc4f5faa46
https://github.com/qemu/qemu/commit/a184c8c7b2dfbd655ecaa39dfa0a58bc4f5faa46
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/avocado/replay_linux.py
Log Message:
-----------
tests/avocado: add replay Linux tests for virtio machine
This patch adds two tests for replaying Linux boot process
on x86_64 virtio platform.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <165364840811.688121.11931681195199516354.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cc754761961bc9afc89641912f2b0099cc910e45
https://github.com/qemu/qemu/commit/cc754761961bc9afc89641912f2b0099cc910e45
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/avocado/replay_linux.py
Log Message:
-----------
tests/avocado: add replay Linux test for Aarch64 machines
This patch adds two tests for replaying Linux boot process
on Aarch64 platform.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <165364841373.688121.8868079200312201658.stgit@pasha-ThinkPad-X280>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7825ebc755777bcc65cb7dcb620939df32594901
https://github.com/qemu/qemu/commit/7825ebc755777bcc65cb7dcb620939df32594901
Author: Dario Faggioli <dfaggioli@suse.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests/Makefile.include: Fix 'make check-help' output
Since commit 3d2f73ef75e ("build: use "meson test" as the test harness"),
check-report.tap is no more, and we have check-report.junit.xml.
Update the output of 'make check-help', which was still listing
'check-report.tap', accordingly.
Fixes: 3d2f73ef75e
Signed-off-by: Dario Faggioli <dfaggioli@suse.com>
Message-Id: <165366545439.6869.11633009118019728798.stgit@work>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 348d71ff62a13bec56860ab4a1d8cd98c85c2105
https://github.com/qemu/qemu/commit/348d71ff62a13bec56860ab4a1d8cd98c85c2105
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
x86: cpu: make sure number of addressable IDs for processor cores meets the
spec
Accourding Intel's CPUID[EAX=04H] resulting bits 31 - 26 in EAX
should be:
"
**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
is the number of unique
Core_IDs reserved for addressing different processor cores in a physical
package. Core ID is a subset of
bits of the initial APIC ID.
"
ensure that values stored in EAX[31-26] always meets this condition.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220524151020.2541698-2-imammedo@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ca777cf77b08b63d2a92fce535ab6e037faebeb6
https://github.com/qemu/qemu/commit/ca777cf77b08b63d2a92fce535ab6e037faebeb6
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
x86: cpu: fixup number of addressable IDs for logical processors sharing cache
When QEMU is started with '-cpu host,host-cache-info=on', it will
passthrough host's number of logical processors sharing cache and
number of processor cores in the physical package. QEMU already
fixes up the later to correctly reflect number of configured cores
for VM, however number of logical processors sharing cache is still
comes from host CPU, which confuses guest started with:
-machine q35,accel=kvm \
-cpu host,host-cache-info=on,l3-cache=off \
-smp 20,sockets=2,dies=1,cores=10,threads=1 \
-numa node,nodeid=0,memdev=ram-node0 \
-numa node,nodeid=1,memdev=ram-node1 \
-numa cpu,socket-id=0,node-id=0 \
-numa cpu,socket-id=1,node-id=1
on 2 socket Xeon 4210R host with 10 cores per socket
with CPUID[04H]:
...
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
...
that doesn't match number of logical processors VM was
configured with and as result RHEL 9.0 guest complains:
sched: CPU #10's llc-sibling CPU #0 is not on the same node! [node: 1 != 0].
Ignoring dependency.
WARNING: CPU: 10 PID: 0 at arch/x86/kernel/smpboot.c:421
topology_sane.isra.0+0x67/0x80
...
Call Trace:
set_cpu_sibling_map+0x176/0x590
start_secondary+0x5b/0x150
secondary_startup_64_no_verify+0xc2/0xcb
Fix it by capping max number of logical processors to vcpus/socket
as it was configured, which fixes the issue.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2088311
Message-Id: <20220524151020.2541698-3-imammedo@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1a70a7d64b55025083e5f0626d031f8f25cd41c4
https://github.com/qemu/qemu/commit/1a70a7d64b55025083e5f0626d031f8f25cd41c4
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M python/qemu/qmp/util.py
M python/setup.cfg
Log Message:
-----------
python: update for mypy 0.950
typeshed (included in mypy) recently updated to improve the typing for
WriteTransport objects. I was working around this, but now there's a
version where I shouldn't work around it.
Unfortunately this creates some minor ugliness if I want to support both
pre- and post-0.950 versions. For now, for my sanity, just disable the
unused-ignores warning.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-2-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 862c01a1f963450f6e98c7b9ed49b0a5ba5a98fa
https://github.com/qemu/qemu/commit/862c01a1f963450f6e98c7b9ed49b0a5ba5a98fa
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests: add "TESTS_PYTHON" variable to Makefile
This is a convenience feature: $(PYTHON) points to the Python executable
we were instructed to use by the configure script. We use that Python to
create a virtual environment with the "check-venv" target in
tests/Makefile.include.
$(TESTS_PYTHON) points to the Python executable belonging to the virtual
environment tied to the build. This Python executable is a symlink to
the binary used to create the venv, which will be the version provided
at configure time.
Using $(TESTS_PYTHON) therefore uses the $(PYTHON) executable, but with
paths modified to use packages installed to the venv.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-3-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ac554aae24078fac3146eb38368c1adfbdc166ce
https://github.com/qemu/qemu/commit/ac554aae24078fac3146eb38368c1adfbdc166ce
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests: use python3 as the python executable name
Use "python3" instead of "python" as per PEP0394:
https://peps.python.org/pep-0394/
This should always be defined (in a venv, at least!), matching the
preferred python shebang of "#!/usr/bin/env python3".
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-4-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 414a84980e0fba3d1d4330b412884e674ffb96e8
https://github.com/qemu/qemu/commit/414a84980e0fba3d1d4330b412884e674ffb96e8
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests: silence pip upgrade warnings during venv creation
Turn off the nag warning coaxing us to upgrade pip. It's not really that
interesting to see in CI logs, and as long as nothing is broken --
nothing is broken.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-5-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 53cbfafff92357d0944b4c67e41296ed57724a7a
https://github.com/qemu/qemu/commit/53cbfafff92357d0944b4c67e41296ed57724a7a
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests: add quiet-venv-pip macro
Factor out the "test venv pip" macro; rewrite the "check-venv" rule to
be a little more compact. Replace the "PIP" pseudo-command output with
"VENVPIP" to make it 1% more clear that we are talking about using pip
to install something into a venv.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-6-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5e1d3abde4032fd2324bf3aff5730f223105dd23
https://github.com/qemu/qemu/commit/5e1d3abde4032fd2324bf3aff5730f223105dd23
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/Makefile.include
M tests/avocado/avocado_qemu/__init__.py
M tests/avocado/virtio_check_params.py
M tests/avocado/virtio_version.py
M tests/requirements.txt
Log Message:
-----------
tests: install "qemu" namespace package into venv
This patch adds the "qemu" namespace package to the $build/tests/venv
directory. It does so in "editable" mode, which means that changes to
the source python directory will actively be reflected by the venv.
This patch also then removes any sys.path hacking from the avocado test
scripts directly. By doing this, the environment of where to find these
packages is managed entirely by the virtual environment and not by the
scripts themselves.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-7-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e143e113a064d645990b21fa65a0be3f962fa082
https://github.com/qemu/qemu/commit/e143e113a064d645990b21fa65a0be3f962fa082
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/vm/Makefile.include
M tests/vm/basevm.py
Log Message:
-----------
tests: use tests/venv to run basevm.py-based scripts
This patch co-opts the virtual environment being used by avocado tests
to also run the basevm.py tests. This is being done in preparation for
for the qemu.qmp package being removed from qemu.git.
As part of the change, remove any sys.path() hacks and treat "qemu" as a
normal third-party import.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-8-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4a74a6efeedaf6f24a080ef3c243480d322dbed7
https://github.com/qemu/qemu/commit/4a74a6efeedaf6f24a080ef3c243480d322dbed7
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M tests/docker/dockerfiles/debian10.docker
Log Message:
-----------
tests: add python3-venv to debian10.docker
This is needed to be able to add a venv-building step to 'make check';
the clang-user job in particular needs this to be able to run
check-unit.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-9-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8650c7cdc2461ed98e85b31b02e37d454bd4d7d2
https://github.com/qemu/qemu/commit/8650c7cdc2461ed98e85b31b02e37d454bd4d7d2
Author: John Snow <jsnow@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M scripts/device-crash-test
Log Message:
-----------
tests: run 'device-crash-test' from tests/venv
Remove the sys.path hacking from device-crash-test, and add in a little
user-friendly message for anyone who was used to running this script
directly from the source tree.
Modify the GitLab job recipes to create the tests/venv first, then run
device-crash-test from that venv.
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220526000921.1581503-10-jsnow@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c6924b41bc796ce3b60b7524bdc13a8b77edfa05
https://github.com/qemu/qemu/commit/c6924b41bc796ce3b60b7524bdc13a8b77edfa05
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M scripts/meson-buildoptions.sh
Log Message:
-----------
regenerate meson-buildoptions.sh
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7b8d0cee7cf488b6e894b1fcaf7ca61ad8688288
https://github.com/qemu/qemu/commit/7b8d0cee7cf488b6e894b1fcaf7ca61ad8688288
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M configure
Log Message:
-----------
configure: remove reference to removed option
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b25ccc73d77e1b64f74046d1c3fbc0fb7327d87e
https://github.com/qemu/qemu/commit/b25ccc73d77e1b64f74046d1c3fbc0fb7327d87e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-06-06 (Mon, 06 Jun 2022)
Changed paths:
M qga/meson.build
Log Message:
-----------
meson: qga: do not use deprecated meson.build_root()
The function will return the build root of the parent project if called from a
subproject; that is irrelevant for QEMU's usage but rarely desirable, and
therefore the function was deprecated and replaced by two functions
project_build_root() and global_build_root(). Replace it with the former.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5cd091e924c0645031f559510f9be52abb962e4c
https://github.com/qemu/qemu/commit/5cd091e924c0645031f559510f9be52abb962e4c
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M .gitlab-ci.d/base.yml
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/custom-runners/ubuntu-20.04-aarch32.yml
M .gitlab-ci.d/custom-runners/ubuntu-20.04-aarch64.yml
M .gitlab-ci.d/custom-runners/ubuntu-20.04-s390x.yml
M .gitlab-ci.d/edk2.yml
M .gitlab-ci.d/opensbi.yml
M .gitmodules
M Kconfig.host
M MAINTAINERS
M Makefile
M accel/accel-common.c
M accel/hvf/hvf-accel-ops.c
M accel/kvm/kvm-all.c
M accel/stubs/tcg-stub.c
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops-mttcg.c
M accel/tcg/tcg-accel-ops-rr.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
M backends/cryptodev-builtin.c
M backends/cryptodev-vhost-user.c
M backends/cryptodev.c
M block/backup.c
M block/block-backend.c
M block/block-copy.c
M block/copy-before-write.c
M block/dirty-bitmap.c
M block/export/export.c
M block/export/meson.build
A block/export/vduse-blk.c
A block/export/vduse-blk.h
M block/export/vhost-user-blk-server.c
A block/export/virtio-blk-handler.c
A block/export/virtio-blk-handler.h
M block/gluster.c
M block/io.c
M block/io_uring.c
M block/linux-aio.c
M block/mirror.c
M block/monitor/bitmap-qmp-cmds.c
M block/nbd.c
M block/rbd.c
M block/trace-events
M bsd-user/bsd-file.h
A bsd-user/bsd-proc.h
M bsd-user/freebsd/os-syscall.c
M bsd-user/syscall_defs.h
M common-user/meson.build
A configs/devices/loongarch64-softmmu/default.mak
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64_be-linux-user.mak
M configs/targets/arm-linux-user.mak
M configs/targets/armeb-linux-user.mak
A configs/targets/loongarch64-linux-user.mak
A configs/targets/loongarch64-softmmu.mak
M configs/targets/riscv32-linux-user.mak
M configs/targets/riscv64-linux-user.mak
M configure
M contrib/vhost-user-blk/meson.build
M contrib/vhost-user-blk/vhost-user-blk.c
M disas.c
R disas/arm-a64.cc
R disas/libvixl/LICENCE
R disas/libvixl/README
R disas/libvixl/meson.build
R disas/libvixl/vixl/a64/assembler-a64.h
R disas/libvixl/vixl/a64/constants-a64.h
R disas/libvixl/vixl/a64/cpu-a64.h
R disas/libvixl/vixl/a64/decoder-a64.cc
R disas/libvixl/vixl/a64/decoder-a64.h
R disas/libvixl/vixl/a64/disasm-a64.cc
R disas/libvixl/vixl/a64/disasm-a64.h
R disas/libvixl/vixl/a64/instructions-a64.cc
R disas/libvixl/vixl/a64/instructions-a64.h
R disas/libvixl/vixl/code-buffer.h
R disas/libvixl/vixl/compiler-intrinsics.cc
R disas/libvixl/vixl/compiler-intrinsics.h
R disas/libvixl/vixl/globals.h
R disas/libvixl/vixl/invalset.h
R disas/libvixl/vixl/platform.h
R disas/libvixl/vixl/utils.cc
R disas/libvixl/vixl/utils.h
M disas/meson.build
M docs/about/deprecated.rst
M docs/conf.py
M docs/devel/submitting-a-patch.rst
M docs/interop/vhost-user.rst
A docs/specs/fw_cfg.rst
R docs/specs/fw_cfg.txt
M docs/specs/index.rst
M docs/specs/vmgenid.txt
M docs/system/arm/cpu-features.rst
M docs/system/arm/emulation.rst
M docs/system/device-emulation.rst
A docs/system/devices/canokey.rst
M docs/system/devices/cxl.rst
M docs/system/devices/nvme.rst
M docs/system/devices/usb.rst
A docs/system/loongarch/loongson3.rst
M docs/tools/qemu-storage-daemon.rst
M ebpf/ebpf_rss.c
A gdb-xml/loongarch-base64.xml
A gdb-xml/loongarch-fpu64.xml
M gdbstub.c
M hmp-commands-info.hx
M hmp-commands.hx
M hw/9pfs/9p-xattr-user.c
M hw/9pfs/9p.c
M hw/Kconfig
M hw/acpi/acpi_interface.c
M hw/acpi/cxl.c
M hw/acpi/erst.c
M hw/acpi/ghes.c
M hw/acpi/ipmi-stub.c
M hw/acpi/ipmi.c
M hw/acpi/meson.build
M hw/acpi/nvdimm.c
M hw/acpi/pcihp.c
M hw/acpi/piix4.c
M hw/acpi/viot.c
M hw/arm/Kconfig
M hw/arm/armv7m.c
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/arm/boot.c
M hw/arm/pxa2xx.c
M hw/arm/virt.c
M hw/arm/xlnx-zynqmp.c
M hw/audio/cs4231a.c
M hw/block/fdc-isa.c
M hw/block/fdc-sysbus.c
M hw/block/m25p80.c
M hw/block/vhost-user-blk.c
M hw/block/virtio-blk.c
M hw/block/xen-block.c
M hw/char/parallel.c
M hw/char/serial-isa.c
M hw/core/generic-loader.c
M hw/core/loader.c
M hw/core/qdev.c
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-host-stubs.c
M hw/cxl/cxl-host.c
M hw/display/artist.c
M hw/display/sii9022.c
M hw/display/ssd0303.c
M hw/display/virtio-gpu-base.c
M hw/display/virtio-gpu.c
M hw/display/virtio-vga.c
M hw/display/xenfb.c
M hw/display/xlnx_dp.c
M hw/hppa/machine.c
M hw/i2c/aspeed_i2c.c
M hw/i2c/core.c
M hw/i2c/pmbus_device.c
M hw/i2c/smbus_ich9.c
M hw/i2c/smbus_slave.c
M hw/i2c/trace-events
M hw/i386/acpi-build.c
M hw/i386/microvm-dt.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M hw/i386/xen/xen-hvm.c
M hw/i386/xen/xen_platform.c
M hw/ide/atapi.c
M hw/ide/core.c
M hw/ide/piix.c
M hw/input/lasips2.c
M hw/input/pckbd.c
M hw/input/pl050.c
M hw/input/ps2.c
M hw/intc/Kconfig
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/arm_gicv3_redist.c
A hw/intc/loongarch_extioi.c
A hw/intc/loongarch_ipi.c
A hw/intc/loongarch_pch_msi.c
A hw/intc/loongarch_pch_pic.c
M hw/intc/meson.build
M hw/intc/openpic.c
M hw/intc/pnv_xive.c
M hw/intc/pnv_xive2.c
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/intc/sifive_plic.c
M hw/intc/trace-events
M hw/ipmi/isa_ipmi_bt.c
M hw/ipmi/isa_ipmi_kcs.c
M hw/ipmi/smbus_ipmi.c
M hw/isa/isa-bus.c
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
M hw/isa/piix4.c
A hw/loongarch/Kconfig
A hw/loongarch/loongson3.c
A hw/loongarch/meson.build
M hw/m68k/bootinfo.h
M hw/m68k/virt.c
M hw/meson.build
M hw/mips/boston.c
M hw/mips/jazz.c
M hw/mips/malta.c
M hw/misc/applesmc.c
M hw/misc/aspeed_hace.c
A hw/misc/aspeed_peci.c
M hw/misc/aspeed_scu.c
M hw/misc/meson.build
M hw/misc/pvpanic-isa.c
M hw/misc/trace-events
M hw/net/e1000.c
M hw/net/fsl_etsec/etsec.c
M hw/net/fsl_etsec/etsec.h
M hw/net/imx_fec.c
M hw/nvme/ctrl.c
M hw/nvme/ns.c
M hw/nvme/nvme.h
M hw/nvme/subsys.c
M hw/nvme/trace-events
M hw/nvram/eeprom_at24c.c
A hw/pci-bridge/cxl_downstream.c
A hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/meson.build
M hw/pci-bridge/pci_expander_bridge.c
A hw/pci-bridge/pci_expander_bridge_stubs.c
M hw/pci-host/i440fx.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/pci-host/q35.c
M hw/pci/msi.c
M hw/pci/msix.c
M hw/pci/pci.c
M hw/pci/pcie_aer.c
M hw/pci/shpc.c
M hw/ppc/pnv.c
M hw/ppc/ppc440_uc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtas_ddw.c
M hw/remote/Kconfig
A hw/remote/iommu.c
M hw/remote/machine.c
M hw/remote/meson.build
M hw/remote/trace-events
A hw/remote/vfio-user-obj.c
M hw/riscv/boot.c
M hw/riscv/virt.c
M hw/rtc/Kconfig
A hw/rtc/ls7a_rtc.c
M hw/rtc/mc146818rtc.c
M hw/rtc/meson.build
M hw/s390x/virtio-ccw.c
M hw/scsi/mfi.h
M hw/scsi/scsi-disk.c
M hw/scsi/scsi-generic.c
M hw/scsi/spapr_vscsi.c
M hw/sensor/Kconfig
M hw/sensor/lsm303dlhc_mag.c
A hw/sensor/max31785.c
M hw/sensor/meson.build
M hw/sparc64/sun4u.c
M hw/sparc64/sun4u_iommu.c
M hw/ssi/aspeed_smc.c
M hw/timer/sse-timer.c
M hw/tpm/tpm_crb.c
M hw/tpm/tpm_tis_common.c
M hw/tpm/tpm_tis_isa.c
M hw/usb/Kconfig
A hw/usb/canokey.c
A hw/usb/canokey.h
M hw/usb/hcd-ehci.c
M hw/usb/meson.build
M hw/usb/redirect.c
M hw/usb/trace-events
M hw/vfio/common.c
M hw/vfio/display.c
M hw/vfio/trace-events
M hw/virtio/trace-events
M hw/virtio/vhost-backend.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
M hw/virtio/virtio-bus.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio-iommu.c
M hw/virtio/virtio-mmio.c
M hw/virtio/virtio-pci.c
M hw/watchdog/meson.build
A hw/watchdog/spapr_watchdog.c
M hw/watchdog/trace-events
M hw/xen/xen_pt_config_init.c
M include/block/aio-wait.h
M include/block/block-copy.h
M include/block/block-io.h
M include/block/block_int-io.h
M include/block/nvme.h
M include/disas/dis-asm.h
M include/exec/cpu-all.h
M include/exec/gdbstub.h
M include/exec/memory.h
M include/exec/poison.h
R include/exec/softmmu-semi.h
A include/hw/acpi/acpi_aml_interface.h
M include/hw/acpi/cxl.h
M include/hw/acpi/ipmi.h
A include/hw/acpi/piix4.h
M include/hw/arm/aspeed_soc.h
M include/hw/block/fdc.h
M include/hw/boards.h
M include/hw/cxl/cxl.h
A include/hw/cxl/cxl_host.h
M include/hw/display/xlnx_dp.h
M include/hw/i2c/aspeed_i2c.h
M include/hw/i2c/i2c.h
M include/hw/i386/pc.h
M include/hw/ide.h
M include/hw/input/i8042.h
M include/hw/input/lasips2.h
M include/hw/input/ps2.h
A include/hw/intc/loongarch_extioi.h
A include/hw/intc/loongarch_ipi.h
A include/hw/intc/loongarch_pch_msi.h
A include/hw/intc/loongarch_pch_pic.h
M include/hw/isa/isa.h
M include/hw/loader.h
A include/hw/loongarch/virt.h
A include/hw/misc/aspeed_peci.h
M include/hw/misc/pvpanic.h
A include/hw/pci-bridge/pci_expander_bridge.h
M include/hw/pci-host/i440fx.h
A include/hw/pci-host/ls7a.h
M include/hw/pci-host/pnv_phb3_regs.h
M include/hw/pci/msi.h
M include/hw/pci/msix.h
M include/hw/pci/pci.h
M include/hw/pci/pci_ids.h
M include/hw/ppc/pnv.h
M include/hw/ppc/spapr.h
M include/hw/qdev-core.h
M include/hw/registerfields.h
A include/hw/remote/iommu.h
M include/hw/remote/machine.h
A include/hw/remote/vfio-user-obj.h
M include/hw/rtc/mc146818rtc.h
M include/hw/southbridge/piix.h
M include/hw/virtio/vhost-backend.h
M include/hw/virtio/vhost.h
M include/hw/virtio/virtio-crypto.h
M include/hw/virtio/virtio-gpu.h
M include/hw/virtio/virtio-iommu.h
M include/hw/xen/xen.h
M include/hw/xen/xen_common.h
A include/io/channel-null.h
M include/monitor/hmp.h
A include/monitor/stats.h
M include/qemu/accel.h
M include/qemu/coroutine.h
M include/qemu/cutils.h
M include/qemu/hbitmap.h
M include/qemu/host-utils.h
M include/qemu/int128.h
M include/qemu/iova-tree.h
M include/qom/object.h
A include/semihosting/common-semi.h
M include/semihosting/console.h
A include/semihosting/guestfd.h
M include/semihosting/semihost.h
A include/semihosting/softmmu-uaccess.h
A include/semihosting/syscalls.h
M include/standard-headers/asm-m68k/bootinfo-virt.h
M include/sysemu/arch_init.h
M include/sysemu/block-backend-io.h
M include/sysemu/cryptodev.h
M include/ui/console.h
M include/ui/gtk.h
A io/channel-null.c
M io/channel-socket.c
M io/meson.build
M io/trace-events
A linux-headers/linux/vduse.h
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/signal.c
M linux-user/aarch64/target_prctl.h
M linux-user/arm/cpu_loop.c
M linux-user/elfload.c
A linux-user/loongarch64/cpu_loop.c
A linux-user/loongarch64/signal.c
A linux-user/loongarch64/sockbits.h
A linux-user/loongarch64/syscall_nr.h
A linux-user/loongarch64/target_cpu.h
A linux-user/loongarch64/target_elf.h
A linux-user/loongarch64/target_errno_defs.h
A linux-user/loongarch64/target_fcntl.h
A linux-user/loongarch64/target_prctl.h
A linux-user/loongarch64/target_resource.h
A linux-user/loongarch64/target_signal.h
A linux-user/loongarch64/target_structs.h
A linux-user/loongarch64/target_syscall.h
A linux-user/loongarch64/termbits.h
M linux-user/m68k/cpu_loop.c
M linux-user/main.c
M linux-user/mmap.c
M linux-user/riscv/cpu_loop.c
M linux-user/semihost.c
M linux-user/syscall.c
M linux-user/syscall_defs.h
M linux-user/user-internals.h
M linux-user/user-mmap.h
M meson.build
M meson_options.txt
M migration/block.c
A migration/channel-block.c
A migration/channel-block.h
M migration/channel.c
M migration/colo.c
M migration/meson.build
M migration/migration.c
M migration/multifd.c
R migration/qemu-file-channel.c
R migration/qemu-file-channel.h
M migration/qemu-file.c
M migration/qemu-file.h
M migration/ram.c
M migration/rdma.c
M migration/savevm.c
M migration/vmstate.c
M monitor/hmp-cmds.c
M monitor/qmp-cmds.c
M nbd/client-connection.c
M nbd/trace-events
M po/LINGUAS
A po/uk.po
M python/qemu/machine/machine.py
M qapi/block-core.json
M qapi/block-export.json
M qapi/block.json
M qapi/machine-target.json
M qapi/machine.json
M qapi/meson.build
M qapi/migration.json
M qapi/misc.json
M qapi/net.json
M qapi/qapi-schema.json
M qapi/qom.json
A qapi/stats.json
M qemu-options.hx
M scripts/clean-header-guards.pl
M scripts/clean-includes
M scripts/coverity-scan/COMPONENTS.md
M scripts/gensyscalls.sh
M scripts/meson-buildoptions.sh
M scripts/qemu-binfmt-conf.sh
M scripts/update-linux-headers.sh
M semihosting/arm-compat-semi.c
R semihosting/common-semi.h
M semihosting/config.c
M semihosting/console.c
A semihosting/guestfd.c
M semihosting/meson.build
A semihosting/syscalls.c
A semihosting/uaccess.c
M softmmu/physmem.c
M softmmu/qdev-monitor.c
M softmmu/vl.c
M storage-daemon/qemu-storage-daemon.c
M stubs/meson.build
M stubs/semihost.c
A stubs/vfio-user-obj.c
M stubs/xen-hw-stub.c
A subprojects/libvduse/include/atomic.h
A subprojects/libvduse/include/compiler.h
A subprojects/libvduse/libvduse.c
A subprojects/libvduse/libvduse.h
A subprojects/libvduse/linux-headers/linux
A subprojects/libvduse/meson.build
A subprojects/libvduse/standard-headers/linux
A subprojects/libvfio-user
M subprojects/libvhost-user/libvhost-user.c
M target/Kconfig
M target/arm/arch_dump.c
A target/arm/common-semi-target.h
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/debug_helper.c
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
A target/arm/helper-sme.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/kvm_arm.h
M target/arm/m_helper.c
M target/arm/machine.c
M target/arm/meson.build
M target/arm/mve_helper.c
M target/arm/op_helper.c
A target/arm/ptw.c
A target/arm/sme_helper.c
M target/arm/sve_helper.c
A target/arm/sve_ldst_internal.h
M target/arm/syndrome.h
M target/arm/tlb_helper.c
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-m-nocp.c
M target/arm/translate-mve.c
M target/arm/translate-sve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
M target/arm/vec_internal.h
M target/avr/cpu.c
M target/avr/cpu.h
M target/avr/helper.c
M target/i386/cpu-sysemu.c
M target/i386/hvf/vmcs.h
M target/i386/hvf/vmx.h
A target/loongarch/Kconfig
A target/loongarch/README
A target/loongarch/constant_timer.c
A target/loongarch/cpu-csr.h
A target/loongarch/cpu-param.h
A target/loongarch/cpu.c
A target/loongarch/cpu.h
A target/loongarch/csr_helper.c
A target/loongarch/disas.c
A target/loongarch/fpu_helper.c
A target/loongarch/gdbstub.c
A target/loongarch/helper.h
A target/loongarch/insn_trans/trans_arith.c.inc
A target/loongarch/insn_trans/trans_atomic.c.inc
A target/loongarch/insn_trans/trans_bit.c.inc
A target/loongarch/insn_trans/trans_branch.c.inc
A target/loongarch/insn_trans/trans_extra.c.inc
A target/loongarch/insn_trans/trans_farith.c.inc
A target/loongarch/insn_trans/trans_fcmp.c.inc
A target/loongarch/insn_trans/trans_fcnv.c.inc
A target/loongarch/insn_trans/trans_fmemory.c.inc
A target/loongarch/insn_trans/trans_fmov.c.inc
A target/loongarch/insn_trans/trans_memory.c.inc
A target/loongarch/insn_trans/trans_privileged.c.inc
A target/loongarch/insn_trans/trans_shift.c.inc
A target/loongarch/insns.decode
A target/loongarch/internals.h
A target/loongarch/iocsr_helper.c
A target/loongarch/machine.c
A target/loongarch/meson.build
A target/loongarch/op_helper.c
A target/loongarch/tlb_helper.c
A target/loongarch/translate.c
A target/loongarch/translate.h
M target/m68k/m68k-semi.c
M target/m68k/meson.build
M target/meson.build
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/tcg/exception.c
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/mips16e_translate.c.inc
M target/mips/tcg/msa_helper.c
M target/mips/tcg/msa_translate.c
M target/mips/tcg/nanomips_translate.c.inc
M target/mips/tcg/sysemu/cp0_helper.c
M target/mips/tcg/sysemu/mips-semi.c
M target/mips/tcg/sysemu/tlb_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/translate.c
M target/nios2/meson.build
M target/nios2/nios2-semi.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/dfp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/internal.h
M target/ppc/translate/fixedpoint-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
A target/riscv/common-semi-target.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/pmp.c
A target/riscv/pmu.c
A target/riscv/pmu.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
M target/s390x/ioinst.c
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
M tests/avocado/boot_linux_console.py
M tests/avocado/machine_aspeed.py
M tests/data/acpi/pc/DSDT
M tests/data/acpi/pc/DSDT.acpierst
M tests/data/acpi/pc/DSDT.acpihmat
M tests/data/acpi/pc/DSDT.bridge
M tests/data/acpi/pc/DSDT.cphp
M tests/data/acpi/pc/DSDT.dimmpxm
M tests/data/acpi/pc/DSDT.hpbridge
M tests/data/acpi/pc/DSDT.hpbrroot
M tests/data/acpi/pc/DSDT.ipmikcs
M tests/data/acpi/pc/DSDT.memhp
M tests/data/acpi/pc/DSDT.nohpet
M tests/data/acpi/pc/DSDT.numamem
M tests/data/acpi/pc/DSDT.roothp
M tests/data/acpi/q35/CEDT.cxl
M tests/data/acpi/q35/DSDT
M tests/data/acpi/q35/DSDT.acpierst
M tests/data/acpi/q35/DSDT.acpihmat
A tests/data/acpi/q35/DSDT.applesmc
M tests/data/acpi/q35/DSDT.bridge
M tests/data/acpi/q35/DSDT.cphp
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/DSDT.dimmpxm
M tests/data/acpi/q35/DSDT.ipmibt
A tests/data/acpi/q35/DSDT.ipmismbus
M tests/data/acpi/q35/DSDT.ivrs
M tests/data/acpi/q35/DSDT.memhp
M tests/data/acpi/q35/DSDT.mmio64
M tests/data/acpi/q35/DSDT.multi-bridge
M tests/data/acpi/q35/DSDT.nohpet
M tests/data/acpi/q35/DSDT.numamem
A tests/data/acpi/q35/DSDT.pvpanic-isa
M tests/data/acpi/q35/DSDT.tis.tpm12
M tests/data/acpi/q35/DSDT.tis.tpm2
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/DSDT.xapic
M tests/data/acpi/q35/VIOT.viot
M tests/docker/Makefile.include
M tests/docker/dockerfiles/centos8.docker
M tests/fp/meson.build
M tests/qemu-iotests/pylintrc
A tests/qemu-iotests/tests/copy-before-write
A tests/qemu-iotests/tests/copy-before-write.out
M tests/qtest/aspeed_smc-test.c
M tests/qtest/bios-tables-test.c
M tests/qtest/cxl-test.c
M tests/qtest/fuzz/generic_fuzz.c
M tests/qtest/migration-helpers.c
M tests/qtest/migration-test.c
M tests/qtest/npcm7xx_sdhci-test.c
M tests/qtest/virtio-9p-test.c
M tests/tcg/arm/Makefile.softmmu-target
M tests/tcg/i386/test-i386-fp-exceptions.c
M tests/tcg/i386/test-i386.c
A tests/tcg/loongarch64/Makefile.softmmu-target
A tests/tcg/loongarch64/system/boot.S
A tests/tcg/loongarch64/system/kernel.ld
A tests/tcg/loongarch64/system/regdef.h
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mffsce.c
A tests/tcg/riscv64/Makefile.softmmu-target
A tests/tcg/riscv64/issue1060.S
A tests/tcg/riscv64/semihost.ld
M tests/tcg/x86_64/system/boot.S
M tests/unit/meson.build
M tests/unit/test-cutils.c
A tests/unit/test-io-channel-null.c
M tests/unit/test-vmstate.c
M tests/vm/Makefile.include
M tools/virtiofsd/passthrough_ll.c
M ui/cocoa.m
M ui/console.c
M ui/gtk-egl.c
M ui/gtk-gl-area.c
M ui/gtk.c
M ui/input.c
M ui/trace-events
M util/aio-wait.c
M util/cacheflush.c
R util/cacheinfo.c
M util/cutils.c
M util/hbitmap.c
M util/host-utils.c
M util/iova-tree.c
M util/meson.build
A util/qemu-co-timeout.c
M util/qemu-timer.c
Log Message:
-----------
Merge https://github.com/qemu/qemu into tip
Commit: eadad54bf10547a9159f5e984b92d274b6101912
https://github.com/qemu/qemu/commit/eadad54bf10547a9159f5e984b92d274b6101912
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-07-15 (Fri, 15 Jul 2022)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/cirrus/freebsd-12.vars
M .gitlab-ci.d/cirrus/freebsd-13.vars
M .travis.yml
M MAINTAINERS
M Makefile
M accel/kvm/kvm-all.c
M accel/tcg/cputlb.c
M audio/meson.build
M block.c
M block/blklogwrites.c
M block/block-backend.c
M block/bochs.c
M block/cloop.c
M block/commit.c
M block/coroutines.h
M block/crypto.c
M block/dmg.c
M block/export/fuse.c
M block/io.c
M block/meson.build
M block/parallels-ext.c
M block/parallels.c
M block/qcow.c
M block/qcow2-bitmap.c
M block/qcow2-cache.c
M block/qcow2-cluster.c
M block/qcow2-refcount.c
M block/qcow2-snapshot.c
M block/qcow2.c
M block/qed.c
M block/vdi.c
M block/vhdx-log.c
M block/vhdx.c
M block/vmdk.c
M block/vpc.c
M block/vvfat.c
M configure
M crypto/block-luks.c
M crypto/block.c
M docs/about/build-platforms.rst
M docs/about/deprecated.rst
M docs/system/arm/aspeed.rst
M docs/system/arm/emulation.rst
M docs/system/arm/virt.rst
M hw/arm/allwinner-h3.c
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
A hw/arm/fby35.c
M hw/arm/meson.build
M hw/arm/virt.c
M hw/block/block.c
M hw/block/fdc.c
M hw/block/hd-geometry.c
M hw/block/m25p80.c
M hw/block/nand.c
M hw/block/onenand.c
M hw/block/pflash_cfi01.c
M hw/block/pflash_cfi02.c
M hw/gpio/aspeed_gpio.c
M hw/i2c/pmbus_device.c
M hw/ide/atapi.c
M hw/m68k/q800.c
M hw/misc/aspeed_sbc.c
M hw/misc/mac_via.c
M hw/misc/sifive_u_otp.c
M hw/nvram/eeprom_at24c.c
M hw/nvram/spapr_nvram.c
M hw/nvram/xlnx-bbram.c
M hw/nvram/xlnx-efuse.c
M hw/ppc/pnv_pnor.c
M hw/scsi/lsi53c895a.c
M hw/scsi/scsi-disk.c
M hw/scsi/trace-events
M hw/sd/sd.c
M hw/sensor/isl_pmbus_vr.c
M include/block/block-io.h
M include/block/block_int-io.h
M include/crypto/block.h
M include/hw/arm/aspeed_soc.h
M include/hw/arm/virt.h
M include/hw/i2c/pmbus_device.h
M include/hw/misc/aspeed_sbc.h
M include/hw/scsi/scsi.h
M include/hw/sensor/isl_pmbus_vr.h
M include/qemu/cutils.h
M include/scsi/constants.h
M include/semihosting/console.h
M include/sysemu/block-backend-io.h
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/signal.c
M linux-user/aarch64/target_cpu.h
M linux-user/aarch64/target_prctl.h
M linux-user/elfload.c
M linux-user/syscall.c
M meson.build
M meson_options.txt
M migration/block.c
M nbd/server.c
M pc-bios/keymaps/meson.build
M pc-bios/meson.build
M pc-bios/optionrom/Makefile
R pc-bios/optionrom/code16gcc.h
M pc-bios/s390-ccw.img
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/netboot.mak
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/virtio-blkdev.c
M pc-bios/s390-ccw/virtio-scsi.c
M pc-bios/s390-ccw/virtio-scsi.h
M pc-bios/s390-ccw/virtio.c
M pc-bios/s390-ccw/virtio.h
M pc-bios/s390-netboot.img
M pc-bios/vof/Makefile
M qemu-img.c
M qemu-io-cmds.c
M qga/commands-posix.c
M qga/commands-win32.c
M qga/main.c
M qga/qapi-schema.json
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
M scripts/oss-fuzz/build.sh
M scripts/qapi/common.py
A scripts/symlink-install-tree.py
M semihosting/console.c
M softmmu/datadir.c
M softmmu/vl.c
M storage-daemon/qemu-storage-daemon.c
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/debug_helper.c
M target/arm/helper-sme.h
M target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/meson.build
M target/arm/ptw.c
A target/arm/sme-fa64.decode
A target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-a64.c
M target/arm/translate-a64.h
A target/arm/translate-sme.c
M target/arm/translate-sve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
M target/i386/hvf/hvf.c
M target/i386/hvf/vmcs.h
M target/i386/hvf/x86_cpuid.c
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
M target/mips/tcg/meson.build
A target/mips/tcg/octeon.decode
A target/mips/tcg/octeon_translate.c
M target/mips/tcg/sysemu/mips-semi.c
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
M target/s390x/tcg/misc_helper.c
M target/s390x/tcg/translate.c
M tcg/region.c
M tests/avocado/avocado_qemu/__init__.py
M tests/avocado/machine_aspeed.py
M tests/qemu-iotests/108
M tests/qemu-iotests/223.out
M tests/qemu-iotests/307.out
M tests/qemu-iotests/mypy.ini
M tests/qemu-iotests/tests/copy-before-write
M tests/qtest/aspeed_gpio-test.c
M tests/qtest/aspeed_smc-test.c
M tests/qtest/fuzz-lsi53c895a-test.c
M tests/qtest/fuzz/fuzz.c
M tests/tcg/Makefile.target
M tests/tcg/aarch64/system/pauth-3.c
M tests/tcg/aarch64/system/semiconsole.c
M tests/tcg/aarch64/system/semiheap.c
M tests/tcg/multiarch/system/memory.c
M tests/unit/test-block-iothread.c
M tests/unit/test-crypto-block.c
M tests/vm/fedora
M tests/vm/freebsd
M tests/vm/netbsd
M tests/vm/openbsd
M ui/cocoa.m
M util/cutils.c
M util/meson.build
M util/module.c
Log Message:
-----------
Merge https://github.com/qemu/qemu into tip
Commit: 24f01d220f56eab3268538ef10655b4fb2453fdf
https://github.com/qemu/qemu/commit/24f01d220f56eab3268538ef10655b4fb2453fdf
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-07-18 (Mon, 18 Jul 2022)
Changed paths:
M MAINTAINERS
M accel/tcg/translate-all.c
M docs/system/devices/nvme.rst
M hw/adc/npcm7xx_adc.c
M hw/arm/bcm2835_peripherals.c
M hw/intc/armv7m_nvic.c
M hw/nvme/ctrl.c
M hw/nvme/ns.c
M hw/nvme/nvme.h
M hw/nvme/trace-events
M include/block/nvme.h
M include/hw/arm/bcm2835_peripherals.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tlb_helper.c
M target/arm/translate-a64.c
A tests/qtest/bcm2835-dma-test.c
M tests/qtest/meson.build
M tests/qtest/npcm7xx_adc-test.c
Log Message:
-----------
Merge https://github.com/qemu/qemu into tip
Commit: 6292097666ae873f85781ec7819f3f67099f190b
https://github.com/qemu/qemu/commit/6292097666ae873f85781ec7819f3f67099f190b
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-07-18 (Mon, 18 Jul 2022)
Changed paths:
M target/hexagon/gen_tcg.h
M tests/tcg/hexagon/mem_noshuf.c
Log Message:
-----------
Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load
Call the CHECK_NOSHUF macro multiple times: once in the
fGEN_TCG_PRED_LOAD() and again in fLOAD().
Before this commit, a packet with a store and a predicated
load with mem_noshuf that gets encoded like this:
{ P0 = cmp.eq(R17,#0x0)
memw(R18+#0x0) = R2
if (!P0.new) R3 = memw(R17+#0x4) }
... would end up generating a branch over both the load
and the store like so:
...
brcond_i32 loc17,$0x0,eq,$L1
mov_i32 loc18,store_addr_1
qemu_st_i32 store_val32_1,store_addr_1,leul,0
qemu_ld_i32 loc16,loc7,leul,0
set_label $L1
...
Test cases added to tests/tcg/hexagon/mem_noshuf.c
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220707210546.15985-2-tsimpson@quicinc.com>
Commit: eb9072602617cb49c489aaf058f72695c2eaedc2
https://github.com/qemu/qemu/commit/eb9072602617cb49c489aaf058f72695c2eaedc2
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-07-18 (Mon, 18 Jul 2022)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/mem_noshuf_exception.c
Log Message:
-----------
Hexagon (target/hexagon) fix bug in mem_noshuf load exception
The semantics of a mem_noshuf packet are that the store effectively
happens before the load. However, in cases where the load raises an
exception, we cannot simply execute the store first.
This change adds a probe to check that the load will not raise an
exception before executing the store.
If the load is predicated, this requires special handling. We check
the condition before performing the probe. Since, we need the EA to
perform the check, we move the GET_EA portion inside CHECK_NOSHUF_PRED.
Test case added in tests/tcg/hexagon/mem_noshuf_exception.c
Suggested-by: Alessandro Di Federico <ale@rev.ng>
Suggested-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220707210546.15985-3-tsimpson@quicinc.com>
Commit: 6d622335bc49435366241a45d9af36bce9e29ace
https://github.com/qemu/qemu/commit/6d622335bc49435366241a45d9af36bce9e29ace
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-19 (Tue, 19 Jul 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/core/machine.c
M hw/i386/acpi-build.c
M hw/i386/pc.c
M hw/nvme/subsys.c
M hw/scsi/vhost-user-scsi.c
M include/hw/boards.h
M migration/migration.c
M monitor/hmp-cmds.c
M qapi/migration.json
M qemu-options.hx
M softmmu/vl.c
M target/arm/cpu64.c
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/translate.c
M tests/qtest/migration-test.c
M tests/tcg/hexagon/Makefile.target
M tests/tcg/hexagon/mem_noshuf.c
A tests/tcg/hexagon/mem_noshuf_exception.c
Log Message:
-----------
Merge tag 'pull-hex-20220718' of https://github.com/quic/qemu into staging
Recall that the semantics of a Hexagon mem_noshuf packet are that the
store effectively happens before the load. There are two bug fixes
in this series.
# gpg: Signature made Mon 18 Jul 2022 19:22:44 BST
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20220718' of https://github.com/quic/qemu: (1480 commits)
Hexagon (target/hexagon) fix bug in mem_noshuf load exception
Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load
meson: qga: do not use deprecated meson.build_root()
configure: remove reference to removed option
regenerate meson-buildoptions.sh
tests: run 'device-crash-test' from tests/venv
tests: add python3-venv to debian10.docker
tests: use tests/venv to run basevm.py-based scripts
tests: install "qemu" namespace package into venv
tests: add quiet-venv-pip macro
tests: silence pip upgrade warnings during venv creation
tests: use python3 as the python executable name
tests: add "TESTS_PYTHON" variable to Makefile
python: update for mypy 0.950
x86: cpu: fixup number of addressable IDs for logical processors sharing cache
x86: cpu: make sure number of addressable IDs for processor cores meets the
spec
tests/Makefile.include: Fix 'make check-help' output
tests/avocado: add replay Linux test for Aarch64 machines
tests/avocado: add replay Linux tests for virtio machine
tests/avocado: update replay_linux test
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f9d9fff72eed...6d622335bc49
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 91e012: nbd: use a QemuMutex to synchronize yanking, recon...,
Peter Maydell <=