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[Qemu-commits] [qemu/qemu] f73eb9: pseries: allow setting stdout-path ev


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] f73eb9: pseries: allow setting stdout-path even on machine...
Date: Fri, 27 May 2022 08:19:20 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f73eb9484bf07812db21de985cb9c1e4ad3c82a9
      
https://github.com/qemu/qemu/commit/f73eb9484bf07812db21de985cb9c1e4ad3c82a9
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: allow setting stdout-path even on machines with a VGA

-machine graphics=off is the usual way to tell the firmware or the OS that the
user wants a serial console.  The pseries machine however does not support
this, and never adds the stdout-path node to the device tree if a VGA device
is provided.  This is in addition to the other magic behavior of VGA devices,
which is to add a keyboard and mouse to the default USB bus.

Split spapr->has_graphics in two variables so that the two behaviors can be
separated: the USB devices remains the same, but the stdout-path is added
even with "-device VGA -machine graphics=off".

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20220507054826.124936-1-pbonzini@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 1e665723e92cd3dae4d8943bf7bd1799a3b4a82a
      
https://github.com/qemu/qemu/commit/1e665723e92cd3dae4d8943bf7bd1799a3b4a82a
  Author: Bernhard Beschow <shentey@gmail.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  hw/ppc/e500: Remove unused BINARY_DEVICE_TREE_FILE

Commit 28290f37e20cda27574f15be9e9499493e3d0fe8 'PPC: E500: Generate
device tree on reset' improved device tree generation and made
BINARY_DEVICE_TREE_FILE obsolete.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220505161805.11116-8-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 5bb55f3e3b00679519a83ffe688eae0e68e305a7
      
https://github.com/qemu/qemu/commit/5bb55f3e3b00679519a83ffe688eae0e68e305a7
  Author: Alexey Kardashevskiy <aik@ozlabs.ru>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Use address from elf parser for kernel address

tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on.

QEMU loads the kernel at 0x400000 by default which works most of
the time as Linux kernels are relocatable, 64bit and compiled with "-pie"
(position independent code). This works for a little endian zImage too.

However a big endian zImage is compiled without -pie, is 32bit, linked to
0x4000000 so current QEMU ends up loading it at
0x4400000 but keeps spapr->kernel_addr unchanged so booting fails.

This uses the kernel address returned from load_elf().
If the default kernel_addr is used, there is no change in behavior (as
translate_kernel_address() takes care of this), which is:
LE/BE vmlinux and LE zImage boot, BE zImage does not.
If the VM created with "-machine kernel-addr=0,x-vof=on", then QEMU
prints a warning and BE zImage boots.

Note #1: SLOF (x-vof=off) still cannot boot a big endian zImage as
SLOF enables MSR_SF for everything loaded by QEMU and this leads to early
crash of 32bit zImage.

Note #2: BE/LE vmlinux images set MSR_SF in early boot so these just work;
a LE zImage restores MSR_SF after every CI call and we are lucky enough
not to crash before the first CI call.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220504065536.3534488-1-aik@ozlabs.ru>
[danielhb: use PRIx64 instead of lx in warn_report]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 162eec18c0aed28eda472bacf207b7b222894169
      
https://github.com/qemu/qemu/commit/162eec18c0aed28eda472bacf207b7b222894169
  Author: Alexey Kardashevskiy <aik@ozlabs.ru>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M docs/system/ppc/pseries.rst

  Log Message:
  -----------
  spapr/docs: Add a few words about x-vof

The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20220506055124.3822112-1-aik@ozlabs.ru>
[danielhb: added linebreaks before and after table]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c9f8004b6adf7020ba742d16b132e84ff6e57863
      
https://github.com/qemu/qemu/commit/c9f8004b6adf7020ba742d16b132e84ff6e57863
  Author: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M hmp-commands-info.hx
    M monitor/misc.c

  Log Message:
  -----------
  mos6522: fix linking error when CONFIG_MOS6522 is not set

When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:

/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158): 
undefined reference to `hmp_info_via'

Make devices configuration available in hmp-commands*.hx and check for
CONFIG_MOS6522.

Fixes: 409e9f7131e5 (mos6522: add "info via" HMP command for debugging)
Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Cc: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20220510235439.54775-1-muriloo@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 4ddc104689b186c4e4ed30be59a54463501761cf
      
https://github.com/qemu/qemu/commit/4ddc104689b186c4e4ed30be59a54463501761cf
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper_regs.c

  Log Message:
  -----------
  target/ppc: Fix tlbie

Commit 74c4912f097bab98 changed check_tlb_flush() to use
tlb_flush_all_cpus_synced() instead of calling tlb_flush() on each
CPU. However, as side effect of this, a CPU executing a ptesync
after a tlbie will have its TLB flushed only after exiting its
current Translation Block (TB).

This causes memory accesses to invalid pages to succeed, if they
happen to be on the same TB as the ptesync.

To fix this, use tlb_flush_all_cpus() instead, that immediately
flushes the TLB of the CPU executing the ptesync instruction.

Fixes: 74c4912f097bab98 ("target/ppc: Fix synchronization of mttcg with 
broadcast TLB flushes")
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220503163904.22575-1-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 3278677f6a5e048b17ea7623c107786448fdf6f4
      
https://github.com/qemu/qemu/commit/3278677f6a5e048b17ea7623c107786448fdf6f4
  Author: Víctor Colombo <victor.colombo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't

According to Power ISA, the FI bit in FPSCR is non-sticky.
This means that if an instruction is said to modify the FI bit, then
it should be set or cleared depending on the result of the
instruction. Otherwise, it should be kept as was before.

However, the following inconsistency was found when comparing results
from the hardware (tested on both a Power 9 processor and in
Power 10 Mambo):

(FI bit is set before the execution of the instruction)
Hardware: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> SET
QEMU: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> CLEARED

As the FI bit is non-sticky, and xscmpeqdp does not list it as a field
that is changed by the instruction, it should not be changed after its
execution.
This is happening to multiple instructions in the vsx implementations.

If the ISA does not list the FI bit as altered for a particular
instruction, then it should be kept as it was before the instruction.

QEMU is not following this behavior. Affected instructions include:
- xv* (all vsx-vector instructions);
- xscmp*, xsmax*, xsmin*;
- xstdivdp and similars;
(to identify the affected instructions, just search in the ISA for
 the instructions that does not list FI in "Special Registers Altered")

Most instructions use the function do_float_check_status() to commit
changes in the inexact flag. So the fix is to add a parameter to it
that will control if the bit FI should be changed or not.
All users of do_float_check_status() are then modified to provide this
argument, controlling if that specific instruction changes bit FI or
not.
Some macro helpers are responsible for both instructions that change
and instructions that aren't suposed to change FI. This seems to always
overlap with the sfprf flag. So, reuse this flag for this purpose when
applicable.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517161522.36132-2-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c582a1dbc8e44f5e976ce9c2ac4ce0bc38a33cae
      
https://github.com/qemu/qemu/commit/c582a1dbc8e44f5e976ce9c2ac4ce0bc38a33cae
  Author: Víctor Colombo <victor.colombo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: Fix FPSCR.FI changing in float_overflow_excp()

This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:

"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exception is set
XX <- 1
...
FI is set to 1
...
"""

However, when tested on a Power 9 hardware, some instructions that
trigger an OX don't set the FI bit:

xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> CLEARED
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> CLEARED
(just a few examples. Other instructions are also affected)

The root cause for this seems to be that only instructions that list
the bit FI in the "Special Registers Altered" should modify it.

QEMU is, today, not working like the hardware:

xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> SET
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET

(all tests assume FI is cleared beforehand)

Fix this by making float_overflow_excp() return float_flag_inexact
if it should update the inexact flags.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20220517161522.36132-3-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: dd657a35b429e9affa373a0e6162dd930854ba78
      
https://github.com/qemu/qemu/commit/dd657a35b429e9affa373a0e6162dd930854ba78
  Author: Víctor Colombo <victor.colombo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag

The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20220517161522.36132-4-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: d5aa9e79048bfc42616949391591fe7947574e5d
      
https://github.com/qemu/qemu/commit/d5aa9e79048bfc42616949391591fe7947574e5d
  Author: Frederic Barrat <fbarrat@linux.ibm.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M hw/intc/pnv_xive2.c

  Log Message:
  -----------
  pnv/xive2: Don't overwrite PC registers when writing TCTXT registers

When writing a register from the TCTXT memory region (4th page within
the IC BAR), we were overwriting the Presentation Controller (PC)
register at the same offset. It looks like a silly cut and paste
error.

We were somehow lucky: the TCTXT registers being touched are
TCTXT_ENx/_SET/_RESET to enable physical threads and the PC registers
at the same offset are either not used by our model or the update was
harmless.

Found through code inspection.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220523151859.72283-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 8f6086044b4de2907ee9660690b709b488b3d55b
      
https://github.com/qemu/qemu/commit/8f6086044b4de2907ee9660690b709b488b3d55b
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h

  Log Message:
  -----------
  target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 9aa898b8977abca0af6b2ed9ec0f7cfa20b9d7f5
      
https://github.com/qemu/qemu/commit/9aa898b8977abca0af6b2ed9ec0f7cfa20b9d7f5
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h

  Log Message:
  -----------
  target/ppc: use TCG_CALL_NO_RWG in vector helpers without env

Helpers of vector instructions without cpu_env as an argument do not
access globals.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 491bcaaa35a68157c0546c65fe6b91e65357b6c9
      
https://github.com/qemu/qemu/commit/491bcaaa35a68157c0546c65fe6b91e65357b6c9
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h

  Log Message:
  -----------
  target/ppc: use TCG_CALL_NO_RWG in BCD helpers

Helpers of BCD instructions only access the VSRs supplied by the
TCGv_ptr arguments, no globals are accessed.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: f2454bfe73d1ae9e7561fc3c29e0d2729381d27c
      
https://github.com/qemu/qemu/commit/f2454bfe73d1ae9e7561fc3c29e0d2729381d27c
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h

  Log Message:
  -----------
  target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env

Helpers of VSX instructions without cpu_env as an argument do not access
globals.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: eb69a84bb07be94179eb2275cd9d4bed12afc66f
      
https://github.com/qemu/qemu/commit/eb69a84bb07be94179eb2275cd9d4bed12afc66f
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/translate/fp-impl.c.inc
    M target/ppc/translate/fp-ops.c.inc

  Log Message:
  -----------
  target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper

fsel doesn't change FPSCR and CR1 is handled by gen_set_cr1_from_fpscr,
so helper_fsel doesn't need the env argument and can be declared with
TCG_CALL_NO_RWG_SE. We also take this opportunity to move the insn to
decodetree.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: cf862bee0e0d31de4809ac7bacb1d65ff7e8b9ce
      
https://github.com/qemu/qemu/commit/cf862bee0e0d31de4809ac7bacb1d65ff7e8b9ce
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/translate/vsx-impl.c.inc
    M target/ppc/translate/vsx-ops.c.inc

  Log Message:
  -----------
  target/ppc: declare xscvspdpn helper with call flags

Move xscvspdpn to decodetree, declare helper_xscvspdpn with
TCG_CALL_NO_RWG_SE and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c36ab970ac0ce257a6badb30f6a485a81c2289d2
      
https://github.com/qemu/qemu/commit/c36ab970ac0ce257a6badb30f6a485a81c2289d2
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/translate/vsx-impl.c.inc
    M target/ppc/translate/vsx-ops.c.inc

  Log Message:
  -----------
  target/ppc: declare xvxsigsp helper with call flags

Move xvxsigsp to decodetree, declare helper_xvxsigsp with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 8f5eeee3f1f1e7da4a1bf1ecb5527071fde1b2d5
      
https://github.com/qemu/qemu/commit/8f5eeee3f1f1e7da4a1bf1ecb5527071fde1b2d5
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/int_helper.c
    M target/ppc/translate/vsx-impl.c.inc
    M target/ppc/translate/vsx-ops.c.inc

  Log Message:
  -----------
  target/ppc: declare xxextractuw and xxinsertw helpers with call flags

Move xxextractuw and xxinsertw to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-9-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: ffc2a2818a6ae321830de2a8c93c78d437c64171
      
https://github.com/qemu/qemu/commit/ffc2a2818a6ae321830de2a8c93c78d437c64171
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/translate/vmx-impl.c.inc

  Log Message:
  -----------
  target/ppc: introduce do_va_helper

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-10-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: b2dc03a5c3a2bbfdf74121cd10d007803ea61e34
      
https://github.com/qemu/qemu/commit/b2dc03a5c3a2bbfdf74121cd10d007803ea61e34
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/int_helper.c
    M target/ppc/translate/vmx-impl.c.inc
    M target/ppc/translate/vmx-ops.c.inc

  Log Message:
  -----------
  target/ppc: declare vmsum[um]bm helpers with call flags

Move vmsumubm and vmsummbm to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-11-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 89a5a1aee2df29c311d11386923b750bf1ea6bc2
      
https://github.com/qemu/qemu/commit/89a5a1aee2df29c311d11386923b750bf1ea6bc2
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/int_helper.c
    M target/ppc/translate/vmx-impl.c.inc
    M target/ppc/translate/vmx-ops.c.inc
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  target/ppc: declare vmsumuh[ms] helper with call flags

Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-12-matheus.ferst@eldorado.org.br>
[danielhb: added #undef VMSUMUHM to fix ppc64 build]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 6f52f731a666d8aeaac5a10b208e9ca6773fb1a6
      
https://github.com/qemu/qemu/commit/6f52f731a666d8aeaac5a10b208e9ca6773fb1a6
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/int_helper.c
    M target/ppc/translate/vmx-impl.c.inc
    M target/ppc/translate/vmx-ops.c.inc

  Log Message:
  -----------
  target/ppc: declare vmsumsh[ms] helper with call flags

Move vmsumshm and vmsumshs to decodetree, declare vmsumshm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-13-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: fcb830af30adaef6219f6b712f24ec3e794cf2c8
      
https://github.com/qemu/qemu/commit/fcb830af30adaef6219f6b712f24ec3e794cf2c8
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Fix eieio memory ordering semantics

The generated eieio memory ordering semantics do not match the
instruction definition in the architecture. Add a big comment to
explain this strange instruction and correct the memory ordering
behaviour.

Signed-off: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 9d82353826422ed0e34ad76961fe0cae5f67e58e
      
https://github.com/qemu/qemu/commit/9d82353826422ed0e34ad76961fe0cae5f67e58e
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: ST_ST memory ordering is not provided with eieio

eieio does not provide ordering between stores to CI memory and stores
to cacheable memory so it can't be used as a general ST_ST barrier.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-of-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220519135908.21282-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: fc879703f74851e3e861894a0c4a6902877d0c2c
      
https://github.com/qemu/qemu/commit/fc879703f74851e3e861894a0c4a6902877d0c2c
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Optimize memory ordering generation with lwsync

lwsync orders more than just LD_LD, importantly it matches x86 and
s390 default memory ordering.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-4-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 03abfd90cfb02aa08f44bbb7141b0aaaf69042ef
      
https://github.com/qemu/qemu/commit/03abfd90cfb02aa08f44bbb7141b0aaaf69042ef
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/machine.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Implement lwsync with weaker memory ordering

This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: a702c5339eda791b969ed531ce99456df7ca8451
      
https://github.com/qemu/qemu/commit/a702c5339eda791b969ed531ce99456df7ca8451
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/insn32.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implement xxm[tf]acc and xxsetaccz

Implement the following PowerISA v3.1 instructions:
xxmfacc: VSX Move From Accumulator
xxmtacc: VSX Move To Accumulator
xxsetaccz: VSX Set Accumulator to Zero

The PowerISA 3.1 mentions that for the current version of the
architecture, "the hardware implementation provides the effect of ACC[i]
and VSRs 4*i to 4*i + 3 logically containing the same data" and "The
Accumulators introduce no new logical state at this time" (page 501).
For now it seems unnecessary to create new structures, so this patch
just uses ACC[i] as VSRs 4*i to 4*i+3 and therefore move to and from
accumulators are no-ops.

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 345531533f26df49e74f16dafc88408408173ece
      
https://github.com/qemu/qemu/commit/345531533f26df49e74f16dafc88408408173ece
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/int_helper.c
    M target/ppc/internal.h
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented xvi*ger* instructions

Implement the following PowerISA v3.1 instructions:
xvi4ger8:     VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp:   VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4:     VSX Vector 4-bit Signed Integer GER (rank-8 update)
xvi8ger4pp:   VSX Vector 4-bit Signed Integer GER (rank-8 update)
Positive multiply, Positive accumulate
xvi8ger4spp:  VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
with Saturate Positive multiply, Positive accumulate
xvi16ger2:    VSX Vector 16-bit Signed Integer GER (rank-2 update)
xvi16ger2pp:  VSX Vector 16-bit Signed Integer GER (rank-2 update)
Positive multiply, Positive accumulate
xvi16ger2s:   VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation
xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation Positive multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 6d525ca972085fb82fe2dec04fdf257318f9e5a5
      
https://github.com/qemu/qemu/commit/6d525ca972085fb82fe2dec04fdf257318f9e5a5
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/insn64.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented pmxvi*ger* instructions

Implement the following PowerISA v3.1 instructions:
pmxvi4ger8:     Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update)
pmxvi4ger8pp:   Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) Positive multiply, Positive accumulate
pmxvi8ger4:     Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update)
pmxvi8ger4pp:   Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update) Positive multiply, Positive accumulate
pmxvi8ger4spp:  Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) with Saturate Positive multiply, Positive accumulate
pmxvi16ger2:    Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update)
pmxvi16ger2pp:  Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvi16ger2s:   Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation
pmxvi16ger2spp: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation Positive multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c29018cc7395fdb7efd5e21c6f6c4d9cfbcf9a3c
      
https://github.com/qemu/qemu/commit/c29018cc7395fdb7efd5e21c6f6c4d9cfbcf9a3c
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented xvf*ger*

Implement the following PowerISA v3.1 instructions:
xvf32ger:   VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger:   VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 2d9cba74ef72232189ac5611968c1b9045a3e1a7
      
https://github.com/qemu/qemu/commit/2d9cba74ef72232189ac5611968c1b9045a3e1a7
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented xvf16ger*

Implement the following PowerISA v3.1 instructions:
xvf16ger2:   VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Negative accumulate
xvf16ger2np: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative
multiply, Positive accumulate
xvf16ger2pn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Negative accumulate
xvf16ger2pp: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive
multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-6-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 6f642338dc929a513ba5ba8f07a23894ba235bd0
      
https://github.com/qemu/qemu/commit/6f642338dc929a513ba5ba8f07a23894ba235bd0
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/insn64.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented pmxvf*ger*

Implement the following PowerISA v3.1 instructions:
pmxvf16ger2:   Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
pmxvf16ger2np: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Positive accumulate
pmxvf16ger2pn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Negative accumulate
pmxvf16ger2pp: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvf32ger:    Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update)
pmxvf32gernn:  Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf32gernp:  Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf32gerpn:  Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf32gerpp:  Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
pmxvf64ger:    Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update)
pmxvf64gernn:  Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf64gernp:  Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf64gerpn:  Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf64gerpp:  Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 5724e131ca6cd970555e66fb47b90b287ffa8ea0
      
https://github.com/qemu/qemu/commit/5724e131ca6cd970555e66fb47b90b287ffa8ea0
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/insn64.decode
    M target/ppc/translate/vsx-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implemented [pm]xvbf16ger2*

Implement the following PowerISA v3.1 instructions:
xvbf16ger2:   VSX Vector bfloat16 GER (rank-2 update)
xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Negative accumulate
xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
Positive accumulate
xvbf16ger2pn: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Negative accumulate
xvbf16ger2pp: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
Positive accumulate
pmxvbf16ger2:   Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
pmxvbf16ger2nn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Negative accumulate
pmxvbf16ger2np: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Negative multiply, Positive accumulate
pmxvbf16ger2pn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Negative accumulate
pmxvbf16ger2pp: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
Positive multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-8-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 96c343cc774b52b010e464a219d13f8e55e1003f
      
https://github.com/qemu/qemu/commit/96c343cc774b52b010e464a219d13f8e55e1003f
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Add PowerPC ISA 3.1 and MMA to hwcap

These are new hwcap bits added for power10.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 272be013d3d3a3218ea7800c579d0e144da679ca
      
https://github.com/qemu/qemu/commit/272be013d3d3a3218ea7800c579d0e144da679ca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M docs/system/ppc/pseries.rst
    M hmp-commands-info.hx
    M hw/intc/pnv_xive2.c
    M hw/ppc/e500.c
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr.h
    M linux-user/elfload.c
    M monitor/misc.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/helper_regs.c
    M target/ppc/insn32.decode
    M target/ppc/insn64.decode
    M target/ppc/int_helper.c
    M target/ppc/internal.h
    M target/ppc/machine.c
    M target/ppc/translate.c
    M target/ppc/translate/fp-impl.c.inc
    M target/ppc/translate/fp-ops.c.inc
    M target/ppc/translate/vmx-impl.c.inc
    M target/ppc/translate/vmx-ops.c.inc
    M target/ppc/translate/vsx-impl.c.inc
    M target/ppc/translate/vsx-ops.c.inc
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  Merge tag 'pull-ppc-20220526' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2022-05-26:

Most of the changes are enhancements/fixes made in TCG ppc emulation
code. Several bugs fixes were made across the board as well.

Changes include:

- tcg and target/ppc: VSX MMA implementation, fixes in helper
declarations to use call flags, memory ordering, tlbie and others
- pseries: fixed stdout-path setting with -machine graphics=off
- pseries: allow use of elf parser for kernel address
- other assorted fixes and improvements

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# gpg: Signature made Thu 26 May 2022 02:35:58 PM PDT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" 
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20220526' of https://gitlab.com/danielhb/qemu: (34 commits)
  linux-user: Add PowerPC ISA 3.1 and MMA to hwcap
  target/ppc: Implemented [pm]xvbf16ger2*
  target/ppc: Implemented pmxvf*ger*
  target/ppc: Implemented xvf16ger*
  target/ppc: Implemented xvf*ger*
  target/ppc: Implemented pmxvi*ger* instructions
  target/ppc: Implemented xvi*ger* instructions
  target/ppc: Implement xxm[tf]acc and xxsetaccz
  target/ppc: Implement lwsync with weaker memory ordering
  tcg/ppc: Optimize memory ordering generation with lwsync
  tcg/ppc: ST_ST memory ordering is not provided with eieio
  target/ppc: Fix eieio memory ordering semantics
  target/ppc: declare vmsumsh[ms] helper with call flags
  target/ppc: declare vmsumuh[ms] helper with call flags
  target/ppc: declare vmsum[um]bm helpers with call flags
  target/ppc: introduce do_va_helper
  target/ppc: declare xxextractuw and xxinsertw helpers with call flags
  target/ppc: declare xvxsigsp helper with call flags
  target/ppc: declare xscvspdpn helper with call flags
  target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/2417cbd5916d...272be013d3d3



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