qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 0a923b: hw/openrisc: page-align FDT address


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 0a923b: hw/openrisc: page-align FDT address
Date: Sun, 15 May 2022 16:56:58 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 0a923be2f6427fdf2a5769b4b8a08e26c758dfab
      
https://github.com/qemu/qemu/commit/0a923be2f6427fdf2a5769b4b8a08e26c758dfab
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-05-04 (Wed, 04 May 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc: page-align FDT address

The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.

Cc: Stafford Horne <shorne@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 777784bda46847fc0587d711c3aacff8fff3c3f9
      
https://github.com/qemu/qemu/commit/777784bda46847fc0587d711c3aacff8fff3c3f9
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-05-15 (Sun, 15 May 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc: support 4 serial ports in or1ksim

The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.

Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: a92162f4f1dfc2daf1bc8f2bbc3cad3c9d1ea729
      
https://github.com/qemu/qemu/commit/a92162f4f1dfc2daf1bc8f2bbc3cad3c9d1ea729
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-05-15 (Sun, 15 May 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc: use right OMPIC size variable

This appears to be a copy and paste error. The UART size was used
instead of the much smaller OMPIC size. But actually that smaller OMPIC
size is wrong too and doesn't allow the IPI to work in Linux. So set it
to the old value.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed
      
https://github.com/qemu/qemu/commit/e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-05-15 (Sun, 15 May 2022)

  Changed paths:
    M target/openrisc/cpu.c

  Log Message:
  -----------
  target/openrisc: Do not reset delay slot flag on early tb exit

This was found when running linux crypto algorithm selftests used by
wireguard.  We found that randomly the tests would fail.  We found
through investigation that a combination of a tick timer interrupt,
raised when executing a delay slot instruction at a page boundary caused
the issue.

This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec.
On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was
being used as a fallback.  The OpenRISC set_pc implementation clears
dflag, which caused the exception handling logic to not account for the
delay slot.  This was the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.

Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.

Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 10c2a0c5e7d48e590d945c017b5b8af5b4c89a3c
      
https://github.com/qemu/qemu/commit/10c2a0c5e7d48e590d945c017b5b8af5b4c89a3c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-05-15 (Sun, 15 May 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c
    M target/openrisc/cpu.c

  Log Message:
  -----------
  Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu 
into staging

OpenRISC Fixes for 7.0

 - A few or1ksim fixes and enhancements
 - A fix for OpenRISC tcg backend around delay slot handling

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmKAWKsACgkQw7McLV5m
# J+SoFg/8Dlrc2BqjjXw9gpaQ18+3BRI6dMVPqHA22VJks88gykH7UWLUbrCxtKnS
# SBcIcpzu17nKDdfwYWndqCr0UBM/zM3JzFrTv4QEhTEg6Np7lSM2KVNEhjBPVGoW
# A7QOjPFrwItWOfAx6hrcczpj+L50iKuWeMW0XnEfqSeDYisxZcSp2yMoe5h3y7bF
# tlpo+ha/ir/fd2kMlFrQlPWYiWkWM05RLJJOlXhdRMF7hrW5qlHqEB/SVykUTf7V
# 6fqOFvY6r3vE5OFm0Scgf/k2AJIxwV8qXkBJ5/egv+ZqUidZBQ9nXtOw++vF2AWp
# eKoU2/c2XIxiF1Xdpgdi6a/CxlLqrr9jraQROB3GpaL9zGQvd//wUCg0F+QLicLv
# avq4lvNmnat89aXj1DQ+DWpLy0zaZFGmxsPR+KeBJ2wkuEJ3Vd4+uiuAyXnm9M8D
# wEE8mgFQYsTL1WlgHF4uNTDIx8OLS+4gYlBE3tffRksxyLLwzKHHgAfLdNZvhfx8
# QZBuPy+yyO8zjr3RUVUArBs/ukZHP1QwDE6uxmPKV34tvVEbFVeSFY3a1LmYV3w5
# mZNALNqf+h5Dq5Qo7f7cGNMrzhL53GTWPNX0MK5+SBDZF3/fpPZyvCr4Zd69Z5tD
# +YClfWBv8HPjdUf+IFHqyE8rURw/sgNvgB76GpalwcUYXRr7zTM=
# =tmP4
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 14 May 2022 06:34:35 PM PDT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu:
  target/openrisc: Do not reset delay slot flag on early tb exit
  hw/openrisc: use right OMPIC size variable
  hw/openrisc: support 4 serial ports in or1ksim
  hw/openrisc: page-align FDT address

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/48de9b0916ef...10c2a0c5e7d4



reply via email to

[Prev in Thread] Current Thread [Next in Thread]