[Qemu-commits] [qemu/qemu] 620d0b: common-user/host/sparc64: Fix safe

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[Qemu-commits] [qemu/qemu] 620d0b: common-user/host/sparc64: Fix safe_sy

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 620d0b: common-user/host/sparc64: Fix safe_syscall_base
Date:	Mon, 14 Feb 2022 07:29:53 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 620d0b49a40e24465472b667f19b5fb0c63a6f0c
      
https://github.com/qemu/qemu/commit/620d0b49a40e24465472b667f19b5fb0c63a6f0c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M common-user/host/sparc64/safe-syscall.inc.S

  Log Message:
  -----------
  common-user/host/sparc64: Fix safe_syscall_base

Use the "retl" instead of "ret" instruction alias, since we
do not allocate a register window in this function.

Fix the offset to the first stacked parameter, which lies
beyond the register window save area.

Fixes: 95c021dac835 ("linux-user/host/sparc64: Add safe-syscall.inc.S")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c8c89a6a30be0e6f24e6a56d4ef181ec0e4dd064
      
https://github.com/qemu/qemu/commit/c8c89a6a30be0e6f24e6a56d4ef181ec0e4dd064
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M linux-user/include/host/aarch64/host-signal.h
    M linux-user/include/host/alpha/host-signal.h
    M linux-user/include/host/arm/host-signal.h
    M linux-user/include/host/i386/host-signal.h
    M linux-user/include/host/loongarch64/host-signal.h
    M linux-user/include/host/mips/host-signal.h
    M linux-user/include/host/ppc/host-signal.h
    M linux-user/include/host/riscv/host-signal.h
    M linux-user/include/host/s390/host-signal.h
    M linux-user/include/host/sparc/host-signal.h
    M linux-user/include/host/x86_64/host-signal.h
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Introduce host_signal_mask

Do not directly access the uc_sigmask member.
This is preparation for a sparc64 fix.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9940799bdea5d456fdbc11d10f355755843063e9
      
https://github.com/qemu/qemu/commit/9940799bdea5d456fdbc11d10f355755843063e9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M linux-user/include/host/aarch64/host-signal.h
    M linux-user/include/host/alpha/host-signal.h
    M linux-user/include/host/arm/host-signal.h
    M linux-user/include/host/i386/host-signal.h
    M linux-user/include/host/loongarch64/host-signal.h
    M linux-user/include/host/mips/host-signal.h
    M linux-user/include/host/ppc/host-signal.h
    M linux-user/include/host/riscv/host-signal.h
    M linux-user/include/host/s390/host-signal.h
    M linux-user/include/host/sparc/host-signal.h
    M linux-user/include/host/x86_64/host-signal.h
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Introduce host_sigcontext

Do not directly access ucontext_t as the third signal parameter.
This is preparation for a sparc64 fix.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 238b32de39b77b01ef4f205e09b01fda8a3a9216
      
https://github.com/qemu/qemu/commit/238b32de39b77b01ef4f205e09b01fda8a3a9216
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    R linux-user/include/host/sparc/host-signal.h
    M linux-user/include/host/sparc64/host-signal.h

  Log Message:
  -----------
  linux-user: Move sparc/host-signal.h to sparc64/host-signal.h

We do not support sparc32 as a host, so there's no point in
sparc64 redirecting to sparc.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4f152ef27e26d82905244b7cbe344929630d8fae
      
https://github.com/qemu/qemu/commit/4f152ef27e26d82905244b7cbe344929630d8fae
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M linux-user/include/host/sparc64/host-signal.h

  Log Message:
  -----------
  linux-user/include/host/sparc64: Fix host_sigcontext

Sparc64 is unique on linux in *not* passing ucontext_t as
the third argument to a SA_SIGINFO handler.  It passes the
old struct sigcontext instead.

Set both pc and npc in host_signal_set_pc.

Fixes: 8b5bd461935b ("linux-user/host/sparc: Populate host_signal.h")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cfc2a2d69d59f02b32df3098ce17e10ab86d43c6
      
https://github.com/qemu/qemu/commit/cfc2a2d69d59f02b32df3098ce17e10ab86d43c6
  Author: Idan Horowitz <idan.horowitz@gmail.com>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Optimize jump cache flush during tlb range flush

When the length of the range is large enough, clearing the whole cache is
faster than iterating over the (possibly extremely large) set of pages
contained in the range.

This mimics the pre-existing similar optimization done on the flush of the
tlb itself.

Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 25e82fb769eddb83e0b68487b8b08d9426704d54
      
https://github.com/qemu/qemu/commit/25e82fb769eddb83e0b68487b8b08d9426704d54
  Author: Idan Horowitz <idan.horowitz@gmail.com>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M softmmu/cpus.c

  Log Message:
  -----------
  softmmu/cpus: Check if the cpu work list is empty atomically

Instead of taking the lock of the cpu work list in order to check if it's
empty, we can just read the head pointer atomically. This decreases
cpu_work_list_empty's share from 5% to 1.3% in a profile of icount-enabled
aarch64-softmmu.

Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Message-Id: <20220114004358.299534-1-idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c3e97f640642d6ea11cddc1ed9d4d68d180eb18a
      
https://github.com/qemu/qemu/commit/c3e97f640642d6ea11cddc1ed9d4d68d180eb18a
  Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M accel/tcg/cpu-exec.c

  Log Message:
  -----------
  replay: use CF_NOIRQ for special exception-replaying TB

Commit aff0e204cb1f1c036a496c94c15f5dfafcd9b4b4 introduced CF_NOIRQ usage,
but one case was forgotten. Record/replay uses one special TB which is not
really executed, but used to cause a correct exception in replay mode.
This patch adds CF_NOIRQ flag for such block.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <164362834054.1754532.7678416881159817273.stgit@pasha-ThinkPad-X280>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7b17a475404c970de1b192d026e00058cea980a6
      
https://github.com/qemu/qemu/commit/7b17a475404c970de1b192d026e00058cea980a6
  Author: WANG Xuerui <git@xen0n.name>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Fix fallout from recent MO_Q renaming

Apparently we were left behind; just renaming MO_Q to MO_UQ is enough.

Fixes: fc313c64345453c7 ("exec/memop: Adding signedness to quad definitions")
Signed-off-by: WANG Xuerui <git@xen0n.name>
Message-Id: <20220206162106.1092364-1-i.qemu@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b1ee3c67253a40f8e62a799eb5b5a0d2954769f4
      
https://github.com/qemu/qemu/commit/b1ee3c67253a40f8e62a799eb5b5a0d2954769f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Support raising sigbus for user-only

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f85ab3d2e51e45e7fa33b539bc7e1350bdf64dde
      
https://github.com/qemu/qemu/commit/f85ab3d2e51e45e7fa33b539bc7e1350bdf64dde
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h

  Log Message:
  -----------
  tcg/aarch64: Support raising sigbus for user-only

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8605cbcdeedb5f24a20dd1341a7a08bd9f38be71
      
https://github.com/qemu/qemu/commit/8605cbcdeedb5f24a20dd1341a7a08bd9f38be71
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h

  Log Message:
  -----------
  tcg/ppc: Support raising sigbus for user-only

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a3fb7c99c05659c98f4de301a932c70991382e26
      
https://github.com/qemu/qemu/commit/a3fb7c99c05659c98f4de301a932c70991382e26
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h

  Log Message:
  -----------
  tcg/riscv: Support raising sigbus for user-only

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1cd49868d47ceceaa0302582bf024936836392a6
      
https://github.com/qemu/qemu/commit/1cd49868d47ceceaa0302582bf024936836392a6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Support raising sigbus for user-only

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fe1bee3a0a97585e3b59dc1db154c28bc8005882
      
https://github.com/qemu/qemu/commit/fe1bee3a0a97585e3b59dc1db154c28bc8005882
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/tci.c

  Log Message:
  -----------
  tcg/tci: Support raising sigbus for user-only

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6f78c7b0828660f6733528dab7bedf027d4958f6
      
https://github.com/qemu/qemu/commit/6f78c7b0828660f6733528dab7bedf027d4958f6
  Author: WANG Xuerui <git@xen0n.name>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h

  Log Message:
  -----------
  tcg/loongarch64: Support raising sigbus for user-only

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220106134238.3936163-1-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 01dfc0ed7f2c5f8dbab65f31228a2888c7b85a07
      
https://github.com/qemu/qemu/commit/01dfc0ed7f2c5f8dbab65f31228a2888c7b85a07
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Drop support for armv4 and armv5 hosts

Support for unaligned accesses is difficult for pre-v6 hosts.
While debian still builds for armv4, we cannot use a compile
time test, so test the architecture at runtime and error out.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6cef13940cc57124bdef9dffbf03f25784f7a51c
      
https://github.com/qemu/qemu/commit/6cef13940cc57124bdef9dffbf03f25784f7a51c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h

  Log Message:
  -----------
  tcg/arm: Remove use_armv5t_instructions

This is now always true, since we require armv6.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bde2cdb59bcd3b0965a80597e72c835fcf5ef7f4
      
https://github.com/qemu/qemu/commit/bde2cdb59bcd3b0965a80597e72c835fcf5ef7f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h

  Log Message:
  -----------
  tcg/arm: Remove use_armv6_instructions

This is now always true, since we require armv6.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 367d43d85b8a0f6262125ccbad8720d02416265e
      
https://github.com/qemu/qemu/commit/367d43d85b8a0f6262125ccbad8720d02416265e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Check alignment for ldrd and strd

We will shortly allow the use of unaligned memory accesses,
and these require proper alignment.  Use get_alignment_bits
to verify and remove USING_SOFTMMU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8821ec2323dd8793d840fd455c5e20e144bddc9b
      
https://github.com/qemu/qemu/commit/8821ec2323dd8793d840fd455c5e20e144bddc9b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Support unaligned access for softmmu

>From armv6, the architecture supports unaligned accesses.
All we need to do is perform the correct alignment check
in tcg_out_tlb_read.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4bb802073f212b5a7e7cffcd4456484932911b91
      
https://github.com/qemu/qemu/commit/4bb802073f212b5a7e7cffcd4456484932911b91
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Reserve a register for guest_base

Reserve a register for the guest_base using aarch64 for reference.
By doing so, we do not have to recompute it for every memory load.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0c90fa5dce29243c06841d7b07ff2bd97c27c1f4
      
https://github.com/qemu/qemu/commit/0c90fa5dce29243c06841d7b07ff2bd97c27c1f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h

  Log Message:
  -----------
  tcg/arm: Support raising sigbus for user-only

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 23a79c113ed2ae693d882d109862f4a759fbf10e
      
https://github.com/qemu/qemu/commit/23a79c113ed2ae693d882d109862f4a759fbf10e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h

  Log Message:
  -----------
  tcg/mips: Support unaligned access for user-only

This is kinda sorta the opposite of the other tcg hosts, where
we get (normal) alignment checks for free with host SIGBUS and
need to add code to support unaligned accesses.

Fortunately, the ISA contains pairs of instructions that are
used to implement unaligned memory accesses.  Use them.

Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d9e52834656ffa766113f1fbae8efe37aaac1df2
      
https://github.com/qemu/qemu/commit/d9e52834656ffa766113f1fbae8efe37aaac1df2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Support unaligned access for softmmu

We can use the routines just added for user-only to emit
unaligned accesses in softmmu mode too.

Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 414399b6b8a02f03d3b0cba5cfa9205dff618a9b
      
https://github.com/qemu/qemu/commit/414399b6b8a02f03d3b0cba5cfa9205dff618a9b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64

When BH is constant, it is constrained to 11 bits for use in MOVCC.
For the cases in which we must load the constant BH into a register,
we do not need the full logic of tcg_out_movi; we can use the simpler
function for emitting a 13 bit constant.

This eliminates the only case in which TCG_REG_T2 was passed to
tcg_out_movi, which will shortly become invalid.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c71929c345d08fa70edb1eeaa9babaaf5d6a9bf7
      
https://github.com/qemu/qemu/commit/c71929c345d08fa70edb1eeaa9babaaf5d6a9bf7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Split out tcg_out_movi_imm32

Handle 32-bit constants with a separate function, so that
tcg_out_movi_int does not need to recurse.  This slightly
rearranges the order of tests for small constants, but
produces the same output.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 92840d06faeed2038b90d5b168c18d73ca3a44b8
      
https://github.com/qemu/qemu/commit/92840d06faeed2038b90d5b168c18d73ca3a44b8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Add scratch argument to tcg_out_movi_int

This will allow us to control exactly what scratch register is
used for loading the constant.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 684db2a0b04ff024d0a275de85982fe5892185d3
      
https://github.com/qemu/qemu/commit/684db2a0b04ff024d0a275de85982fe5892185d3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Improve code gen for shifted 32-bit constants

We had code for checking for 13 and 21-bit shifted constants,
but we can do better and allow 32-bit shifted constants.
This is still 2 insns shorter than the full 64-bit sequence.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6a6bfa3c60ba70e870f8355b9d3508915c90c13a
      
https://github.com/qemu/qemu/commit/6a6bfa3c60ba70e870f8355b9d3508915c90c13a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Convert patch_reloc to return bool

Since 7ecd02a06f8, if patch_reloc fails we restart translation
with a smaller TB.  SPARC had its function signature changed,
but not the logic.  Replace assert with return false.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c834b8d81b0ee597d185a4d8127dfc76230307c8
      
https://github.com/qemu/qemu/commit/c834b8d81b0ee597d185a4d8127dfc76230307c8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Use the constant pool for 64-bit constants

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e01d60f211251388a5d9ae7e02d0b4500af26966
      
https://github.com/qemu/qemu/commit/e01d60f211251388a5d9ae7e02d0b4500af26966
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Add tcg_out_jmpl_const for better tail calls

Due to mapping changes, we now rarely place the code_gen_buffer
near the main executable.  Which means that direct calls will
now rarely be in range.

So, always use indirect calls for tail calls, which allows us to
avoid clobbering %o7, and therefore we need not save and restore it.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 321dbde33a6aa8e7780a3b6b4746628d215a1fec
      
https://github.com/qemu/qemu/commit/321dbde33a6aa8e7780a3b6b4746628d215a1fec
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc: Support unaligned access for user-only

This is kinda sorta the opposite of the other tcg hosts, where
we get (normal) alignment checks for free with host SIGBUS and
need to add code to support unaligned accesses.

This inline code expansion is somewhat large, but it takes quite
a few instructions to make a function call to a helper anyway.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5c1a101ef6b85537a4ade93c39ea81cadd5c246e
      
https://github.com/qemu/qemu/commit/5c1a101ef6b85537a4ade93c39ea81cadd5c246e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    A tests/tcg/multiarch/sigbus.c

  Log Message:
  -----------
  tests/tcg/multiarch: Add sigbus.c

A mostly generic test for unaligned access raising SIGBUS.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 50a75ff680ec8999baa0bffc49af8c6ad5c0035a
      
https://github.com/qemu/qemu/commit/50a75ff680ec8999baa0bffc49af8c6ad5c0035a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-02-14 (Mon, 14 Feb 2022)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/cputlb.c
    M common-user/host/sparc64/safe-syscall.inc.S
    M linux-user/include/host/aarch64/host-signal.h
    M linux-user/include/host/alpha/host-signal.h
    M linux-user/include/host/arm/host-signal.h
    M linux-user/include/host/i386/host-signal.h
    M linux-user/include/host/loongarch64/host-signal.h
    M linux-user/include/host/mips/host-signal.h
    M linux-user/include/host/ppc/host-signal.h
    M linux-user/include/host/riscv/host-signal.h
    M linux-user/include/host/s390/host-signal.h
    R linux-user/include/host/sparc/host-signal.h
    M linux-user/include/host/sparc64/host-signal.h
    M linux-user/include/host/x86_64/host-signal.h
    M linux-user/signal.c
    M softmmu/cpus.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/sparc/tcg-target.c.inc
    M tcg/tci.c
    A tests/tcg/multiarch/sigbus.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' into 
staging

Fix safe_syscall_base for sparc64.
Fix host signal handling for sparc64-linux.
Speedups for jump cache and work list probing.
Fix for exception replays.
Raise guest SIGBUS for user-only misaligned accesses.

# gpg: Signature made Fri 11 Feb 2022 01:27:16 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20220211: (34 commits)
  tests/tcg/multiarch: Add sigbus.c
  tcg/sparc: Support unaligned access for user-only
  tcg/sparc: Add tcg_out_jmpl_const for better tail calls
  tcg/sparc: Use the constant pool for 64-bit constants
  tcg/sparc: Convert patch_reloc to return bool
  tcg/sparc: Improve code gen for shifted 32-bit constants
  tcg/sparc: Add scratch argument to tcg_out_movi_int
  tcg/sparc: Split out tcg_out_movi_imm32
  tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64
  tcg/mips: Support unaligned access for softmmu
  tcg/mips: Support unaligned access for user-only
  tcg/arm: Support raising sigbus for user-only
  tcg/arm: Reserve a register for guest_base
  tcg/arm: Support unaligned access for softmmu
  tcg/arm: Check alignment for ldrd and strd
  tcg/arm: Remove use_armv6_instructions
  tcg/arm: Remove use_armv5t_instructions
  tcg/arm: Drop support for armv4 and armv5 hosts
  tcg/loongarch64: Support raising sigbus for user-only
  tcg/tci: Support raising sigbus for user-only
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/cc5ce8b8b6be...50a75ff680ec
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