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[Qemu-commits] [qemu/qemu] fd50a0: Update copyright dates to 2022
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] fd50a0: Update copyright dates to 2022 |
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Date: |
Sat, 29 Jan 2022 07:55:39 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fd50a00a57509623ac253614ab10c7ea0eeb8d51
https://github.com/qemu/qemu/commit/fd50a00a57509623ac253614ab10c7ea0eeb8d51
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M docs/conf.py
M include/qemu-common.h
Log Message:
-----------
Update copyright dates to 2022
It's a new year; update the copyright strings for our
help/version/about information and for our documentation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220120124713.288303-1-peter.maydell@linaro.org
Commit: 62a4d87d2e4af378875e0749571fe41cab8706de
https://github.com/qemu/qemu/commit/62a4d87d2e4af378875e0749571fe41cab8706de
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/armv7m.c
Log Message:
-----------
hw/armv7m: Fix broken VMStateDescription
In commit d5093d961585f02 we added a VMStateDescription to
the TYPE_ARMV7M object, to handle migration of its Clocks.
However a cut-and-paste error meant we used the wrong struct
name in the VMSTATE_CLOCK() macro arguments. The result was
that attempting a 'savevm' might result in an assertion
failure.
Cc: qemu-stable@nongnu.org
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/803
Fixes: d5093d961585f02
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220120151609.433555-1-peter.maydell@linaro.org
Commit: 617dff091f3478db9a44320df03f74b9df0617fb
https://github.com/qemu/qemu/commit/617dff091f3478db9a44320df03f74b9df0617fb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/char/exynos4210_uart.c
Log Message:
-----------
hw/char/exynos4210_uart: Fix crash on trying to load VM state
The exynos4210_uart_post_load() function assumes that it is passed
the Exynos4210UartState, but it has been attached to the
VMStateDescription for the Exynos4210UartFIFO type. The result is a
SIGSEGV when attempting to load VM state for any machine type
including this device.
Fix the bug by attaching the post-load function to the VMSD for the
Exynos4210UartState. This is the logical place for it, because the
actions it does relate to the entire UART state, not just the FIFO.
Thanks to the bug reporter @TrungNguyen1909 for the clear bug
description and the suggested fix.
Fixes: c9d3396d80fe7ece9b
("hw/char/exynos4210_uart: Implement post_load function")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/638
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220120151648.433736-1-peter.maydell@linaro.org
Commit: 2f93d8b04a1bcc8e0a576e35ae13c96af42634db
https://github.com/qemu/qemu/commit/2f93d8b04a1bcc8e0a576e35ae13c96af42634db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/omap1.c
M hw/arm/pxa2xx.c
M hw/arm/strongarm.c
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/pmu.c
M hw/ppc/spapr_rtc.c
M hw/rtc/allwinner-rtc.c
M hw/rtc/aspeed_rtc.c
M hw/rtc/ds1338.c
M hw/rtc/exynos4210_rtc.c
M hw/rtc/goldfish_rtc.c
M hw/rtc/m41t80.c
M hw/rtc/m48t59.c
M hw/rtc/mc146818rtc.c
M hw/rtc/pl031.c
M hw/rtc/twl92230.c
M hw/rtc/xlnx-zynqmp-rtc.c
M hw/s390x/tod-tcg.c
M hw/scsi/megasas.c
M include/qemu-common.h
A include/sysemu/rtc.h
M net/dump.c
M softmmu/rtc.c
Log Message:
-----------
rtc: Move RTC function prototypes to their own header
softmmu/rtc.c defines two public functions: qemu_get_timedate() and
qemu_timedate_diff(). Currently we keep the prototypes for these in
qemu-common.h, but most files don't need them. Move them to their
own header, a new include/sysemu/rtc.h.
Since the C files using these two functions did not need to include
qemu-common.h for any other reason, we can remove those include lines
when we add the include of the new rtc.h.
The license for the .h file follows that of the softmmu/rtc.c
where both the functions are defined.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 8c1c0a1b72f1d9138c2a219064072a4462d4cc8e
https://github.com/qemu/qemu/commit/8c1c0a1b72f1d9138c2a219064072a4462d4cc8e
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/misc/meson.build
A hw/misc/xlnx-versal-pmc-iou-slcr.c
A include/hw/misc/xlnx-versal-pmc-iou-slcr.h
Log Message:
-----------
hw/misc: Add a model of Versal's PMC SLCR
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-2-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9a6d491831e6e12a971f6a0c59e9553e96a9241c
https://github.com/qemu/qemu/commit/9a6d491831e6e12a971f6a0c59e9553e96a9241c
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f7c9aecbf850fd819643ea884de338f810e285f1
https://github.com/qemu/qemu/commit/f7c9aecbf850fd819643ea884de338f810e285f1
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm/xlnx-versal: Connect Versal's PMC SLCR
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-4-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ba4fbdbd9b8be7bed4285bc4cf684488b48fb518
https://github.com/qemu/qemu/commit/ba4fbdbd9b8be7bed4285bc4cf684488b48fb518
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M include/hw/dma/xlnx_csu_dma.h
Log Message:
-----------
include/hw/dma/xlnx_csu_dma: Add in missing includes in the header
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-5-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 00f05c02f9e7342fb423110061bdf66921fe80b2
https://github.com/qemu/qemu/commit/00f05c02f9e7342fb423110061bdf66921fe80b2
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/dma/xlnx_csu_dma.c
M include/hw/dma/xlnx_csu_dma.h
Log Message:
-----------
hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method
An option on real hardware when embedding a DMA engine into a peripheral
is to make the peripheral control the engine through a custom DMA control
(hardware) interface between the two. Software drivers in this scenario
configure and trigger DMA operations through the controlling peripheral's
register API (for example, writing a specific bit in a register could
propagate down to a transfer start signal on the DMA control interface).
At the same time the status, results and interrupts for the transfer might
still be intended to be read and caught through the DMA engine's register
API (and signals).
This patch adds a class 'read' method for allowing to start read transfers
from peripherals embedding and controlling the Xilinx CSU DMA engine as in
above scenario.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cbb45ff038cdbfcc8af158191405e2597f28c562
https://github.com/qemu/qemu/commit/cbb45ff038cdbfcc8af158191405e2597f28c562
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/ssi/meson.build
A hw/ssi/xlnx-versal-ospi.c
A include/hw/ssi/xlnx-versal-ospi.h
Log Message:
-----------
hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-7-francisco.iglesias@xilinx.com
[PMM: fixed indent]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3
https://github.com/qemu/qemu/commit/868d96800477a3dfa5d0e0f6cb3a88c3b1fab6a3
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220121161141.14389-8-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6b3fac72d91fc1363bd7d79cf14050bd12a56918
https://github.com/qemu/qemu/commit/6b3fac72d91fc1363bd7d79cf14050bd12a56918
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220121161141.14389-9-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4461f0fb23bf8867c0d5a378d6b08c651c1fc7ab
https://github.com/qemu/qemu/commit/4461f0fb23bf8867c0d5a378d6b08c651c1fc7ab
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/xlnx-versal-virt.c
Log Message:
-----------
hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220121161141.14389-10-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 72e58848b2393271f1c9866905d9c61ba21d952e
https://github.com/qemu/qemu/commit/72e58848b2393271f1c9866905d9c61ba21d952e
Author: Francisco Iglesias <francisco.iglesias@xilinx.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add an entry for Xilinx Versal OSPI
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220121161141.14389-11-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5212297c474c816f65b1ad6d0d0efe88a08ba6b9
https://github.com/qemu/qemu/commit/5212297c474c816f65b1ad6d0d0efe88a08ba6b9
Author: Andrew Baumann <Andrew.Baumann@microsoft.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself (for raspi).
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Message-id:
MW4PR21MB1940E8BB52F4053C943B1FCD9E219@MW4PR21MB1940.namprd21.prod.outlook.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0166f5c46627b872a9d26eae8ded4be45263a321
https://github.com/qemu/qemu/commit/0166f5c46627b872a9d26eae8ded4be45263a321
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M scripts/update-linux-headers.sh
Log Message:
-----------
scripts: Explain the difference between linux-headers and standard-headers
If you don't know it, it's hard to figure out the difference between
the linux-headers folder and the include/standard-headers folder.
So let's add a short explanation to clarify the difference.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: fc6177af1137789dccb9e257bfae778d18381f90
https://github.com/qemu/qemu/commit/fc6177af1137789dccb9e257bfae778d18381f90
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Log CPU index in 'Taking exception' log
In an SMP system it can be unclear which CPU is taking an exception;
add the CPU index (which is the same value used in the TCG 'Trace
%d:' logging) to the "Taking exception" log line to clarify it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-2-peter.maydell@linaro.org
Commit: 195209d3682847b253175af7a1cffd2c007273a2
https://github.com/qemu/qemu/commit/195209d3682847b253175af7a1cffd2c007273a2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3_its: Add tracepoints
The ITS currently has no tracepoints; add a minimal set
that allows basic monitoring of guest register accesses and
reading of commands from the command queue.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-3-peter.maydell@linaro.org
Commit: e5ff041f62fd01154dc91f9ac43ac3498b4689e1
https://github.com/qemu/qemu/commit/e5ff041f62fd01154dc91f9ac43ac3498b4689e1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS
In our implementation, all ITSes connected to a GIC share a single
AddressSpace, which we keep in the GICv3State::dma_as field and
initialized based on the GIC's 'sysmem' property. The right place
to set it up by calling address_space_init() is therefore in the
GIC's realize method, not the ITS's realize.
This fixes a theoretical bug where QEMU hangs on startup if the board
model creates two ITSes connected to the same GIC -- we would call
address_space_init() twice on the same AddressSpace*, which creates
an infinite loop in the QTAILQ that softmmu/memory.c uses to store
its list of AddressSpaces and causes any subsequent attempt to
iterate through that list to loop forever. There aren't any board
models like that in the tree at the moment, though.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-4-peter.maydell@linaro.org
Commit: 1e794a3be1687a8561c7188a3d3fc26f525cf487
https://github.com/qemu/qemu/commit/1e794a3be1687a8561c7188a3d3fc26f525cf487
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set
The current ITS code clears GITS_CREADR when GITS_CTLR.ENABLED is set.
This is not correct -- guest code can validly clear ENABLED and then
set it again and expect the ITS to continue processing where it left
off. Remove the erroneous assignment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-5-peter.maydell@linaro.org
Commit: 0cc38f359cbb50dd4f182b4ad3b7f7a17b1a4721
https://github.com/qemu/qemu/commit/0cc38f359cbb50dd4f182b4ad3b7f7a17b1a4721
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER
The ITS specification says that when the guest writes to GITS_CBASER
this causes GITS_CREADR to be cleared. However it does not have an
equivalent clause for GITS_CWRITER. (This is because GITS_CREADR is
read-only, but GITS_CWRITER is writable and the guest can initialize
it.) Remove the code that clears GITS_CWRITER on GITS_CBASER writes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-6-peter.maydell@linaro.org
Commit: 703090770c19dad32f42a8bc27393ed01b7bc42f
https://github.com/qemu/qemu/commit/703090770c19dad32f42a8bc27393ed01b7bc42f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3.c
Log Message:
-----------
hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs
The GICD_CTLR distributor register has enable bits which control
whether the different interrupt groups (Group 0, Non-secure Group 1
and Secure Group 1) are forwarded to the CPU. We get this right for
traditional interrupts, but forgot to account for it when adding
LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not
set we must not forward them to the CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-7-peter.maydell@linaro.org
Commit: 714d8bde0423b38117bfebd88e2f09a01a0efbfd
https://github.com/qemu/qemu/commit/714d8bde0423b38117bfebd88e2f09a01a0efbfd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3_its: Sort ITS command list into numeric order
The list of #defines for the ITS command packet numbers is neither
in alphabetical nor numeric order. Sort it into numeric order.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-8-peter.maydell@linaro.org
Commit: d7d19c0aeb7d657c76c88913744ff53fc7e24c23
https://github.com/qemu/qemu/commit/d7d19c0aeb7d657c76c88913744ff53fc7e24c23
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_redist.c
Log Message:
-----------
hw/intc/arm_gicv3_redist: Remove unnecessary zero checks
The ITS-related parts of the redistributor code make some checks for
whether registers like GICR_PROPBASER and GICR_PENDBASER are zero.
There is no requirement in the specification for treating zeroes in
these address registers specially -- they contain guest physical
addresses and it is entirely valid (if unusual) for the guest to
choose to put the tables they address at guest physical address zero.
We use these values only to calculate guest addresses, and attempts
by the guest to use a bad address will be handled by the
address_space_* functions which we use to do the loads and stores.
Remove the unnecessary checks.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-9-peter.maydell@linaro.org
Commit: 1611956bce06b0721ea949e24c089ef22967672a
https://github.com/qemu/qemu/commit/1611956bce06b0721ea949e24c089ef22967672a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_common.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
Commit: 7e062b98a2541ca9a632160aadbe8574c8bdce24
https://github.com/qemu/qemu/commit/7e062b98a2541ca9a632160aadbe8574c8bdce24
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Provide read accessor for translation_ops
The MemoryRegionOps gicv3_its_translation_ops currently provides only
a .write_with_attrs function, because the only register in this
region is the write-only GITS_TRANSLATER. However, if you don't
provide a read function and the guest tries reading from this memory
region, QEMU will crash because
memory_region_read_with_attrs_accessor() calls a NULL pointer.
Add a read function which always returns 0, to cover both bogus
attempts to read GITS_TRANSLATER and also reads from the rest of the
region, which is documented to be reserved, RES0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-11-peter.maydell@linaro.org
Commit: 0ffe88e6919d210c806078aaf0c34911554f1438
https://github.com/qemu/qemu/commit/0ffe88e6919d210c806078aaf0c34911554f1438
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers
The ITS has a bank of 8 GITS_BASER<n> registers, which allow the
guest to specify the base address of various data tables. Each
register has a read-only type field indicating which table it is for
and a read-write field where the guest can write in the base address
(among other things). We currently allow the guest to write the
writeable fields for all eight registers, even if the type field is 0
indicating "Unimplemented". This means the guest can provoke QEMU
into asserting by writing an address into one of these unimplemented
base registers, which bypasses the "if (!value) continue" check in
extract_table_params() and lets us hit the assertion that the type
field is one of the permitted table types.
Prevent the assertion by not allowing the guest to write to the
unimplemented base registers. This means their value will remain 0
and extract_table_params() will ignore them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-12-peter.maydell@linaro.org
Commit: 8b8bb0146b5383188e045ab75a53a0e179614cad
https://github.com/qemu/qemu/commit/8b8bb0146b5383188e045ab75a53a0e179614cad
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
M include/hw/intc/arm_gicv3_its_common.h
Log Message:
-----------
hw/intc/arm_gicv3_its: Check table bounds against correct limit
Currently when we fill in a TableDesc based on the value the guest
has written to the GITS_BASER<n> register, we calculate both:
* num_entries : the number of entries in the table, constrained
by the amount of memory the guest has given it
* num_ids : the number of IDs we support for this table,
constrained by the implementation choices and the architecture
(eg DeviceIDs are 16 bits, so num_ids is 1 << 16)
When validating ITS commands, however, we check only num_ids,
thus allowing a broken guest to specify table entries that
index off the end of it. This will only corrupt guest memory,
but the ITS is supposed to reject such commands as invalid.
Instead of calculating both num_entries and num_ids, set
num_entries to the minimum of the two limits, and check that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-13-peter.maydell@linaro.org
Commit: f6d1d9b4074d64de92f3ab4dfa50dc19548fdfd7
https://github.com/qemu/qemu/commit/f6d1d9b4074d64de92f3ab4dfa50dc19548fdfd7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3_its: Implement MOVALL
Implement the ITS MOVALL command, which takes all the pending
interrupts on a source redistributor and makes the not-pending on
that source redistributor and pending on a destination redistributor.
This is a GICv3 ITS command which we forgot to implement. (It is
not used by Linux guests.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-14-peter.maydell@linaro.org
Commit: 961b4912c1330aaf11a354c9d8f5c63e1ba0ae3b
https://github.com/qemu/qemu/commit/961b4912c1330aaf11a354c9d8f5c63e1ba0ae3b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3_its: Implement MOVI
Implement the ITS MOVI command. This command specifies a (physical) LPI
by DeviceID and EventID and provides a new ICID for it. The ITS must
find the interrupt translation table entry for the LPI, which will
tell it the old ICID. It then moves the pending state of the LPI from
the old redistributor to the new one and updates the ICID field in
the translation table entry.
This is another GICv3 ITS command that we forgot to implement. Linux
does use this one, but only if the guest powers off one of its CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-15-peter.maydell@linaro.org
Commit: 08048cbd5e7dc0a0359ccb8c7968e4d011174801
https://github.com/qemu/qemu/commit/08048cbd5e7dc0a0359ccb8c7968e4d011174801
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
hw/arm: ast2600: Fix address mapping of second SPI controller
Address should be 0x1E631000 and not 0x1E641000 as initially introduced.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838
Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support")
Suggested-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220126083520.4135713-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c023d3675a3ffb54fc30504dcd715bc6f6e234f
https://github.com/qemu/qemu/commit/2c023d3675a3ffb54fc30504dcd715bc6f6e234f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp
The exception caused by an SVC instruction may be taken to AArch32
Hyp mode for two reasons:
* HCR.TGE indicates that exceptions from EL0 should trap to EL2
* we were already in Hyp mode
The entrypoint in the vector table to be used differs in these two
cases: for an exception routed to Hyp mode from EL0, we enter at the
common 0x14 "hyp trap" entrypoint. For SVC from Hyp mode to Hyp
mode, we enter at the 0x08 (svc/hvc trap) entrypoint.
In the v8A Arm ARM pseudocode this is done in AArch32.TakeSVCException.
QEMU incorrectly routed both of these exceptions to the 0x14
entrypoint. Correct the entrypoint for SVC from Hyp to Hyp by making
use of the existing logic which handles "normal entrypoint for
Hyp-to-Hyp, otherwise 0x14" for traps like UNDEF and data/prefetch
aborts (reproduced here since it's outside the visible context
in the diff for this commit):
if (arm_current_el(env) != 2 && addr < 0x14) {
addr = 0x14;
}
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220117131953.3936137-1-peter.maydell@linaro.org
Commit: 95a6af2a006e7160c958215c20e513ed29a0a76c
https://github.com/qemu/qemu/commit/95a6af2a006e7160c958215c20e513ed29a0a76c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M MAINTAINERS
M docs/conf.py
M hw/arm/armv7m.c
M hw/arm/aspeed_ast2600.c
M hw/arm/omap1.c
M hw/arm/pxa2xx.c
M hw/arm/strongarm.c
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M hw/block/m25p80.c
M hw/char/exynos4210_uart.c
M hw/dma/xlnx_csu_dma.c
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
M hw/intc/trace-events
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/pmu.c
M hw/misc/meson.build
A hw/misc/xlnx-versal-pmc-iou-slcr.c
M hw/ppc/spapr_rtc.c
M hw/rtc/allwinner-rtc.c
M hw/rtc/aspeed_rtc.c
M hw/rtc/ds1338.c
M hw/rtc/exynos4210_rtc.c
M hw/rtc/goldfish_rtc.c
M hw/rtc/m41t80.c
M hw/rtc/m48t59.c
M hw/rtc/mc146818rtc.c
M hw/rtc/pl031.c
M hw/rtc/twl92230.c
M hw/rtc/xlnx-zynqmp-rtc.c
M hw/s390x/tod-tcg.c
M hw/scsi/megasas.c
M hw/ssi/meson.build
A hw/ssi/xlnx-versal-ospi.c
M include/hw/arm/xlnx-versal.h
M include/hw/dma/xlnx_csu_dma.h
M include/hw/intc/arm_gicv3_its_common.h
A include/hw/misc/xlnx-versal-pmc-iou-slcr.h
A include/hw/ssi/xlnx-versal-ospi.h
M include/qemu-common.h
A include/sysemu/rtc.h
M net/dump.c
M scripts/update-linux-headers.sh
M softmmu/rtc.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/m_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220128'
into staging
target-arm queue:
* Update copyright dates to 2022
* hw/armv7m: Fix broken VMStateDescription
* hw/char/exynos4210_uart: Fix crash on trying to load VM state
* rtc: Move RTC function prototypes to their own header
* xlnx-versal-virt: Support PMC SLCR
* xlnx-versal-virt: Support OSPI flash memory controller
* scripts: Explain the difference between linux-headers and standard-headers
* target/arm: Log CPU index in 'Taking exception' log
* arm_gicv3_its: Various bugfixes and cleanups
* arm_gicv3_its: Implement the missing MOVI and MOVALL commands
* ast2600: Fix address mapping of second SPI controller
* target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp
# gpg: Signature made Fri 28 Jan 2022 15:29:36 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20220128: (32 commits)
target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp
hw/arm: ast2600: Fix address mapping of second SPI controller
hw/intc/arm_gicv3_its: Implement MOVI
hw/intc/arm_gicv3_its: Implement MOVALL
hw/intc/arm_gicv3_its: Check table bounds against correct limit
hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers
hw/intc/arm_gicv3_its: Provide read accessor for translation_ops
hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
hw/intc/arm_gicv3_redist: Remove unnecessary zero checks
hw/intc/arm_gicv3_its: Sort ITS command list into numeric order
hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs
hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER
hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set
hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS
hw/intc/arm_gicv3_its: Add tracepoints
target/arm: Log CPU index in 'Taking exception' log
scripts: Explain the difference between linux-headers and standard-headers
MAINTAINERS: Remove myself (for raspi).
MAINTAINERS: Add an entry for Xilinx Versal OSPI
hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7a1043cef917...95a6af2a006e