[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 28ca46: hw: timer: ibex_timer: Fixup reading
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 28ca46: hw: timer: ibex_timer: Fixup reading w/o register |
|
Date: |
Fri, 21 Jan 2022 04:58:15 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 28ca4689ae94a27a6a337546425cda30d0e885c3
https://github.com/qemu/qemu/commit/28ca4689ae94a27a6a337546425cda30d0e885c3
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/timer/ibex_timer.c
M include/hw/timer/ibex_timer.h
Log Message:
-----------
hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0df470c3886eda19afdbd5ccd5550ce794feef7b
https://github.com/qemu/qemu/commit/0df470c3886eda19afdbd5ccd5550ce794feef7b
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/riscv/opentitan.c
Log Message:
-----------
riscv: opentitan: fixup plic stride len
The following change was made to rectify incorrectly set stride length
on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was
discovered whilst attempting to fix a bug where a timer_interrupt was
not serviced on TockOS-OpenTitan.
[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dda94e5c66e4c48c3709acf5532c295a80845730
https://github.com/qemu/qemu/commit/dda94e5c66e4c48c3709acf5532c295a80845730
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/timer/ibex_timer.c
Log Message:
-----------
hw: timer: ibex_timer: update/add reg address
The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
The CTRL register is @ 0x04.
This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS-OpenTitan.
2. Adds ALERT_TEST register as documented on [1], adding repective
switch cases to error handle and later implement functionality.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b91a0fa70cdd23ca7929d4e255fcfe93e1fe7513
https://github.com/qemu/qemu/commit/b91a0fa70cdd23ca7929d4e255fcfe93e1fe7513
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
A linux-headers/asm-riscv/kvm.h
Log Message:
-----------
update-linux-headers: Add asm-riscv/kvm.h
Add asm-riscv/kvm.h for RISC-V KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91654e613bf67863f27854a7c8e292a273b50a40
https://github.com/qemu/qemu/commit/91654e613bf67863f27854a7c8e292a273b50a40
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
A target/riscv/kvm.c
M target/riscv/meson.build
Log Message:
-----------
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0a312b85cb433386804a2ca79f4a1f7ab75f64a7
https://github.com/qemu/qemu/commit/0a312b85cb433386804a2ca79f4a1f7ab75f64a7
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: Implement function kvm_arch_init_vcpu
Get isa info from kvm while kvm init.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 937f0b45120bea964ca4ababbe98e1a2de05a077
https://github.com/qemu/qemu/commit/937f0b45120bea964ca4ababbe98e1a2de05a077
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: Implement kvm_arch_get_registers
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-5-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9997cc1e19d1f909551783c280cfe441a0838943
https://github.com/qemu/qemu/commit/9997cc1e19d1f909551783c280cfe441a0838943
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: Implement kvm_arch_put_registers
Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ad40be27084536408b47a9209181f776ec2c54a5
https://github.com/qemu/qemu/commit/ad40be27084536408b47a9209181f776ec2c54a5
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/intc/sifive_plic.c
M hw/riscv/boot.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
M target/riscv/cpu.c
M target/riscv/cpu.h
A target/riscv/kvm-stub.c
M target/riscv/kvm.c
A target/riscv/kvm_riscv.h
M target/riscv/meson.build
Log Message:
-----------
target/riscv: Support start kernel directly by KVM
Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. Add kvm_riscv.h to place riscv specific interface.
In addition, PLIC is created without M-mode PLIC contexts when KVM
is enabled.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-id: 20220112081329.1835-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2b650fbbcc2b5d34943bb5697d8799b2c1a885e1
https://github.com/qemu/qemu/commit/2b650fbbcc2b5d34943bb5697d8799b2c1a885e1
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm-stub.c
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: Support setting external interrupt by KVM
When KVM is enabled, set the S-mode external interrupt through
kvm_riscv_set_irq function.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-8-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4eb471258bd0e331678bece4c894c477928b3b0b
https://github.com/qemu/qemu/commit/4eb471258bd0e331678bece4c894c477928b3b0b
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/kvm.c
A target/riscv/sbi_ecall_interface.h
Log Message:
-----------
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 10f1ca27e0fe9930d372591cd5f302e7249aa705
https://github.com/qemu/qemu/commit/10f1ca27e0fe9930d372591cd5f302e7249aa705
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add host cpu type
'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 27abe66f31efa8bcd15f0f998db2127b4ffb628a
https://github.com/qemu/qemu/commit/27abe66f31efa8bcd15f0f998db2127b4ffb628a
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: Add kvm_riscv_get/put_regs_timer
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9ad3e016ae1ed2f30c39051bc20f1da327bd9400
https://github.com/qemu/qemu/commit/9ad3e016ae1ed2f30c39051bc20f1da327bd9400
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: Implement virtual time adjusting with vm state changing
We hope that virtual time adjusts with vm state changing. When a vm
is stopped, guest virtual time should stop counting and kvm_timer
should be stopped. When the vm is resumed, guest virtual time should
continue to count and kvm_timer should be restored.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-12-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1eb9a5da31abb0a7b613756f5bb7c887b7ef60ea
https://github.com/qemu/qemu/commit/1eb9a5da31abb0a7b613756f5bb7c887b7ef60ea
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Support virtual time context synchronization
Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-13-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fbf43c7dbf18156d4dce73183dd17b83f6ca65fc
https://github.com/qemu/qemu/commit/fbf43c7dbf18156d4dce73183dd17b83f6ca65fc
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M meson.build
Log Message:
-----------
target/riscv: enable riscv kvm accel
Add riscv kvm support in meson.build file.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-id: 20220112081329.1835-14-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cfeeeb482a5279f240407a9d7266274c67c21d2e
https://github.com/qemu/qemu/commit/cfeeeb482a5279f240407a9d7266274c67c21d2e
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M softmmu/device_tree.c
Log Message:
-----------
softmmu/device_tree: Silence compiler warning with --enable-sanitizers
If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
complains:
.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
in this function [-Werror=maybe-uninitialized]
int namelen, retval;
^~~~~~
It's a false warning since the while loop is always executed at least
once (p has to be non-NULL, otherwise the derefence in the if-statement
earlier will crash). Thus let's switch to a do-while loop here instead
to make the compiler happy in all cases.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220107133844.145039-1-thuth@redhat.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 22599b795c8395fa3e2a90c3b32ca1622035feeb
https://github.com/qemu/qemu/commit/22599b795c8395fa3e2a90c3b32ca1622035feeb
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M softmmu/device_tree.c
Log Message:
-----------
softmmu/device_tree: Remove redundant pointer assignment
The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20220111032758.27804-1-wangyanan55@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b4a99d40276eb5bdfa849cc04344d9a2c4c820ef
https://github.com/qemu/qemu/commit/b4a99d40276eb5bdfa849cc04344d9a2c4c820ef
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b
https://github.com/qemu/qemu/commit/c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 494104093fafab12208a8f1f0cb2ab5f5c8c7035
https://github.com/qemu/qemu/commit/494104093fafab12208a8f1f0cb2ab5f5c8c7035
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: aaae69942f5c73a724daf09dcbd963cd852ccb64
https://github.com/qemu/qemu/commit/aaae69942f5c73a724daf09dcbd963cd852ccb64
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586
https://github.com/qemu/qemu/commit/13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40d78c85f6f321c00588230a400477250a85c2e7
https://github.com/qemu/qemu/commit/40d78c85f6f321c00588230a400477250a85c2e7
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe
https://github.com/qemu/qemu/commit/193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 235d1161d4ddbcd2d80aad7253ef69f2f5819926
https://github.com/qemu/qemu/commit/235d1161d4ddbcd2d80aad7253ef69f2f5819926
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 68fa38970ea0f9fdcbf01f6e04531de72d40f755
https://github.com/qemu/qemu/commit/68fa38970ea0f9fdcbf01f6e04531de72d40f755
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bfefe406b7666bfc624bf54820aa14bd43838dc5
https://github.com/qemu/qemu/commit/bfefe406b7666bfc624bf54820aa14bd43838dc5
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 32e579b8c510f0c8d7023d87b0cfacf782cb4a62
https://github.com/qemu/qemu/commit/32e579b8c510f0c8d7023d87b0cfacf782cb4a62
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf
https://github.com/qemu/qemu/commit/da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: abe2d74032d6d12a6918715086bbdf8843296f36
https://github.com/qemu/qemu/commit/abe2d74032d6d12a6918715086bbdf8843296f36
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8527b5db728b572c288fdcadb126d369040731be
https://github.com/qemu/qemu/commit/8527b5db728b572c288fdcadb126d369040731be
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f4dcf51cdcd25e8df150b0a394ccefc0611975dc
https://github.com/qemu/qemu/commit/f4dcf51cdcd25e8df150b0a394ccefc0611975dc
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6db02328a7537fb62c282700f34d9b0c0a845854
https://github.com/qemu/qemu/commit/6db02328a7537fb62c282700f34d9b0c0a845854
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9
https://github.com/qemu/qemu/commit/2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8d8897accb1c9b28267b3c7eb402b6bc5d967f7e
https://github.com/qemu/qemu/commit/8d8897accb1c9b28267b3c7eb402b6bc5d967f7e
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
M include/hw/riscv/spike.h
Log Message:
-----------
hw/riscv: spike: Allow using binary firmware as bios
Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.
The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 092dc6df92f2f97487747eb1044ac2bcac64924d
https://github.com/qemu/qemu/commit/092dc6df92f2f97487747eb1044ac2bcac64924d
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M hw/riscv/spike.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Remove macros for ELF BIOS image names
Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4211fc5532343adaa8f648cedfa8e44643944717
https://github.com/qemu/qemu/commit/4211fc5532343adaa8f648cedfa8e44643944717
Author: Anup Patel <apatel@ventanamicro.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M .gitlab-ci.d/opensbi.yml
M pc-bios/meson.build
R pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
R pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
M roms/Makefile
Log Message:
-----------
roms/opensbi: Remove ELF images
Now that all RISC-V machines can use OpenSBI BIN images, we remove
OpenSBI ELF images and also exclude these images from BIOS build.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 79f26b3b951dd8eeec23d437c41f0944167ce44d
https://github.com/qemu/qemu/commit/79f26b3b951dd8eeec23d437c41f0944167ce44d
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/csr.c
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Adjust pmpcfg access with mxl
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b655dc7cd91588a77c3df6f618246fd88ad14249
https://github.com/qemu/qemu/commit/b655dc7cd91588a77c3df6f618246fd88ad14249
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/helper.h
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Don't save pc when exception return
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a14db52f7fa9f6843d1806e8d4cd56f3410bb59d
https://github.com/qemu/qemu/commit/a14db52f7fa9f6843d1806e8d4cd56f3410bb59d
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Sign extend link reg for jal and jalr
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40f0c2046c490ef4b8bed4ca628620ab8a2bdf87
https://github.com/qemu/qemu/commit/40f0c2046c490ef4b8bed4ca628620ab8a2bdf87
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Sign extend pc for different XLEN
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 440544e1cff9877cdf17aae4ecfe775410b1eff2
https://github.com/qemu/qemu/commit/440544e1cff9877cdf17aae4ecfe775410b1eff2
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Create xl field in env
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc
https://github.com/qemu/qemu/commit/8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Ignore the pc bits above XLEN
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bf9e776ec19a7e93dc520824c23cf8754fe274fd
https://github.com/qemu/qemu/commit/bf9e776ec19a7e93dc520824c23cf8754fe274fd
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Extend pc for runtime pc write
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1191be09a90a866549993d4852cef7e094655e42
https://github.com/qemu/qemu/commit/1191be09a90a866549993d4852cef7e094655e42
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: Use gdb xml according to max mxlen
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 47bdec821b8dda7658e3e802a26b9bd8319cdb49
https://github.com/qemu/qemu/commit/47bdec821b8dda7658e3e802a26b9bd8319cdb49
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Relax debug check for pm write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 83b519b8a44d6b7d9b9d9763e7189061e116215d
https://github.com/qemu/qemu/commit/83b519b8a44d6b7d9b9d9763e7189061e116215d
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Adjust csr write mask with XLEN
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40bfa5f6950afbec943353304fcd4367cc143548
https://github.com/qemu/qemu/commit/40bfa5f6950afbec943353304fcd4367cc143548
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Create current pm fields in env
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0cff460de9e3417d248a5756b1cfbd9211657f94
https://github.com/qemu/qemu/commit/0cff460de9e3417d248a5756b1cfbd9211657f94
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Alloc tcg global for cur_pm[mask|base]
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4302bef9e17831902a7e7c8082cac1c8ed151759
https://github.com/qemu/qemu/commit/4302bef9e17831902a7e7c8082cac1c8ed151759
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Calculate address according to XLEN
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4208dc7e9e6fe1bb7a0698eac31f44388046dc00
https://github.com/qemu/qemu/commit/4208dc7e9e6fe1bb7a0698eac31f44388046dc00
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Split pm_enabled into mask and base
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d96a271a8daedb83247baf89349ead0cb8f0c449
https://github.com/qemu/qemu/commit/d96a271a8daedb83247baf89349ead0cb8f0c449
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Split out the vill from vtype
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 31961cfe505e11cc4ec4cfde52c851957e1bf605
https://github.com/qemu/qemu/commit/31961cfe505e11cc4ec4cfde52c851957e1bf605
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Adjust vsetvl according to XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eef11ce325f1544ca0cafb1c734cdb8b1d0cb123
https://github.com/qemu/qemu/commit/eef11ce325f1544ca0cafb1c734cdb8b1d0cb123
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Remove VILL field in VTYPE
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 01d09525da655fed6cabc49a6088c4e11f93612a
https://github.com/qemu/qemu/commit/01d09525da655fed6cabc49a6088c4e11f93612a
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix check range for first fault only
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d6b9d9302342fc273441811b43dd42dbd3b799e0
https://github.com/qemu/qemu/commit/d6b9d9302342fc273441811b43dd42dbd3b799e0
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Adjust vector address with mask
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d8c40c24fd5276536a95052ab35763c21def6f01
https://github.com/qemu/qemu/commit/d8c40c24fd5276536a95052ab35763c21def6f01
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Adjust scalar reg in vector with XLEN
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5a2ae2350e78cfdc7ca9885b8c3d62137115a494
https://github.com/qemu/qemu/commit/5a2ae2350e78cfdc7ca9885b8c3d62137115a494
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Set default XLEN for hypervisor
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f310df58bd2c570be8b802bffb37cb30da0c346e
https://github.com/qemu/qemu/commit/f310df58bd2c570be8b802bffb37cb30da0c346e
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Enable uxl field write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f297245f6a780f496fb171af6fcd21ff3e6783c3
https://github.com/qemu/qemu/commit/f297245f6a780f496fb171af6fcd21ff3e6783c3
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Relax UXL field for debugging
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5e9d14f2bea6df89c0675df953f9c839560d2266
https://github.com/qemu/qemu/commit/5e9d14f2bea6df89c0675df953f9c839560d2266
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-21 (Fri, 21 Jan 2022)
Changed paths:
M .gitlab-ci.d/opensbi.yml
M hw/char/riscv_htif.c
M hw/intc/sifive_plic.c
M hw/riscv/boot.c
M hw/riscv/opentitan.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M hw/timer/ibex_timer.c
M include/hw/char/riscv_htif.h
M include/hw/riscv/boot.h
M include/hw/riscv/spike.h
M include/hw/timer/ibex_timer.h
A linux-headers/asm-riscv/kvm.h
M meson.build
M pc-bios/meson.build
R pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
R pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
M roms/Makefile
M softmmu/device_tree.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
A target/riscv/kvm-stub.c
A target/riscv/kvm.c
A target/riscv/kvm_riscv.h
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/op_helper.c
M target/riscv/pmp.c
A target/riscv/sbi_ecall_interface.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20220121-1' into staging
Third RISC-V PR for QEMU 7.0
* Fixes for OpenTitan timer
* Correction of OpenTitan PLIC stride length
* RISC-V KVM support
* Device tree code cleanup
* Support for the Zve64f and Zve32f extensions
* OpenSBI binary loading support for the Spike machine
* Removal of OpenSBI ELFs
* Support for the UXL field in xstatus
# gpg: Signature made Fri 21 Jan 2022 05:57:09 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220121-1: (61 commits)
target/riscv: Relax UXL field for debugging
target/riscv: Enable uxl field write
target/riscv: Set default XLEN for hypervisor
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Adjust vector address with mask
target/riscv: Fix check range for first fault only
target/riscv: Remove VILL field in VTYPE
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Split out the vill from vtype
target/riscv: Split pm_enabled into mask and base
target/riscv: Calculate address according to XLEN
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Create current pm fields in env
target/riscv: Adjust csr write mask with XLEN
target/riscv: Relax debug check for pm write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Extend pc for runtime pc write
target/riscv: Ignore the pc bits above XLEN
target/riscv: Create xl field in env
target/riscv: Sign extend pc for different XLEN
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/2c89b5af5e72...5e9d14f2bea6