[Qemu-commits] [qemu/qemu] 01b5ab: hw/intc/arm_gicv3: Move checking of redist-region-...

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 01b5ab8cc08ab0afb6574f46a4d966725a00a1de
      
https://github.com/qemu/qemu/commit/01b5ab8cc08ab0afb6574f46a4d966725a00a1de
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Move checking of redist-region-count to 
arm_gicv3_common_realize

The GICv3 devices have an array property redist-region-count.
Currently we check this for errors (bad values) in
gicv3_init_irqs_and_mmio(), just before we use it.  Move this error
checking to the arm_gicv3_common_realize() function, where we
sanity-check all of the other base-class properties. (This will
always be before gicv3_init_irqs_and_mmio() is called, because
that function is called in the subclass realize methods, after
they have called the parent-class realize.)

The motivation for this refactor is:
 * we would like to use the redist_region_count[] values in
   arm_gicv3_common_realize() in a subsequent patch, so we need
   to have already done the sanity-checking first
 * this removes the only use of the Error** argument to
   gicv3_init_irqs_and_mmio(), so we can remove some error-handling
   boilerplate

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 046164155abe7594ad1d8729dbe150e95badeaed
      
https://github.com/qemu/qemu/commit/046164155abe7594ad1d8729dbe150e95badeaed
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    M hw/intc/arm_gicv3_common.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1

The 'Last' bit in the GICR_TYPER GICv3 redistributor register is
supposed to be set to 1 if this is the last redistributor in a series
of contiguous redistributor pages.  Currently we set Last only for
the redistributor for CPU (num_cpu - 1).  This only works if there is
a single redistributor region; if there are multiple redistributor
regions then we need to set the Last bit for the last redistributor
in each region.

This doesn't cause any problems currently because only the KVM GICv3
supports multiple redistributor regions, and it ignores the value in
GICv3State::gicr_typer.  But we need to fix this before we can enable
support for multiple regions in the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e5cba10ee16566a479cebec3890e91df91e33ab5
      
https://github.com/qemu/qemu/commit/e5cba10ee16566a479cebec3890e91df91e33ab5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/intc/arm_gicv3_redist.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Support multiple redistributor regions

Our GICv3 QOM interface includes an array property
redist-region-count which allows board models to specify that the
registributor registers are not in a single contiguous range, but
split into multiple pieces.  We implemented this for KVM, but
currently the TCG GICv3 model insists that there is only one region.
You can see the limit being hit with a setup like:
  qemu-system-aarch64 -machine virt,gic-version=3 -smp 124

Add support for split regions to the TCG GICv3.  To do this we switch
from allocating a simple array of MemoryRegions to an array of
GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
the opaque pointer in the MemoryRegion read/write callbacks.  Each
GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
the read/write callback to get hold of the GICv3State, and an index
which allows us to calculate which CPU's redistributor is being
accessed.

Note that arm_gicv3_kvm always passes in NULL as the ops argument
to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
callbacks we need to update to handle this new scheme are the
gicv3_redist_read/write functions used by the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1adf528ec3bdf62ea3b580b7ad562534a3676ff5
      
https://github.com/qemu/qemu/commit/1adf528ec3bdf62ea3b580b7ad562534a3676ff5
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    M hw/rtc/meson.build
    M hw/rtc/pl031.c

  Log Message:
  -----------
  hw/rtc/pl031: Send RTC_CHANGE QMP event

The PL031 currently is not able to report guest RTC change to the QMP
monitor as opposed to mc146818 or spapr RTCs. This patch adds the call
to qapi_event_send_rtc_change() when the Load Register is written. The
value which is reported corresponds to the difference between the guest
reference time and the reference time kept in softmmu/rtc.c.

For instance adding 20s to the guest RTC value will report 20. Adding
an extra 20s to the guest RTC value will report 20 + 20 = 40.

The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c
require to compile the PL031 with specific_ss.add() to avoid
./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned
"TARGET_<ARCH>".

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210920122535.269988-1-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3e595538b8338ea7789d1d4003b0504258b6aa31
      
https://github.com/qemu/qemu/commit/3e595538b8338ea7789d1d4003b0504258b6aa31
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-11-16 (Tue, 16 Nov 2021)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/intc/arm_gicv3_redist.c
    M hw/rtc/meson.build
    M hw/rtc/pl031.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20211115-1' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Support multiple redistributor regions for TCG GICv3
 * Send RTC_CHANGE QMP event from pl031

# gpg: Signature made Mon 15 Nov 2021 07:53:40 PM CET
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20211115-1' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/rtc/pl031: Send RTC_CHANGE QMP event
  hw/intc/arm_gicv3: Support multiple redistributor regions
  hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
  hw/intc/arm_gicv3: Move checking of redist-region-count to 
arm_gicv3_common_realize

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/757b8dd4e970...3e595538b833