[Qemu-commits] [qemu/qemu] 6a2b0f: tests/docker: Remove fedora-i386-cros

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[Qemu-commits] [qemu/qemu] 6a2b0f: tests/docker: Remove fedora-i386-cros

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 6a2b0f: tests/docker: Remove fedora-i386-cross from DOCKER...
Date:	Wed, 06 Oct 2021 08:56:31 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 6a2b0fd171082eae19f1da043cf53b5a5a7b9c6c
      
https://github.com/qemu/qemu/commit/6a2b0fd171082eae19f1da043cf53b5a5a7b9c6c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tests/docker/Makefile.include

  Log Message:
  -----------
  tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES

The image was upgraded to a full image in ee381b7fe146.
This makes it possible to use docker-test@image syntax
with this container.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20210930163636.721311-2-richard.henderson@linaro.org>


  Commit: 08a13c4b247338329951238a6c47b94f70c387d2
      
https://github.com/qemu/qemu/commit/08a13c4b247338329951238a6c47b94f70c387d2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tests/docker/dockerfiles/fedora-i386-cross.docker

  Log Message:
  -----------
  tests/docker: Fix fedora-i386-cross cross-compilation

By using PKG_CONFIG_PATH instead of PKG_CONFIG_LIBDIR,
we were still including the 64-bit packages.  Install
pcre-devel.i686 to fill a missing glib2 dependency.

By using --extra-cflags instead of --cpu, we incorrectly
use the wrong probing during meson.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20210930163636.721311-3-richard.henderson@linaro.org>


  Commit: db637f270b52f8c2a1c55e7e707532532295715c
      
https://github.com/qemu/qemu/commit/db637f270b52f8c2a1c55e7e707532532295715c
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M include/tcg/tcg.h

  Log Message:
  -----------
  tcg: add dup_const_tl wrapper

dup_const always generates a uint64_t, which may exceed the size of a
target_long (generating warnings with recent-enough compilers).

To ensure that we can use dup_const both for 64bit and 32bit targets,
this adds dup_const_tl, which either maps back to dup_const (for 64bit
targets) or provides a similar implementation using 32bit constants.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Message-Id: <20211003214243.3813425-1-philipp.tomsich@vrull.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c433e298d99228e41a78d480a505cfcc8c9ea067
      
https://github.com/qemu/qemu/commit/c433e298d99228e41a78d480a505cfcc8c9ea067
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Drop signness in tracing in cputlb.c

We are already inconsistent about whether or not
MO_SIGN is set in trace_mem_get_info.  Dropping it
entirely allows some simplification.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4b473e0c60d802bb69accab3177d350fc580e2a4
      
https://github.com/qemu/qemu/commit/4b473e0c60d802bb69accab3177d350fc580e2a4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M include/exec/memop.h
    M target/arm/translate-a64.c
    M target/s390x/tcg/translate_vx.c.inc
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390/tcg-target.c.inc
    M tcg/sparc/tcg-target.c.inc
    M tcg/tcg-op.c

  Log Message:
  -----------
  tcg: Expand MO_SIZE to 3 bits

We have lacked expressive support for memory sizes larger
than 64-bits for a while.  Fixing that requires adjustment
to several points where we used this for array indexing,
and two places that develop -Wswitch warnings after the change.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9002ffcb7264947d9a193567b457dea42f15c321
      
https://github.com/qemu/qemu/commit/9002ffcb7264947d9a193567b457dea42f15c321
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/tcg/tcg.h
    M target/arm/helper-a64.c
    M target/arm/m_helper.c
    M target/i386/tcg/mem_helper.c
    M target/m68k/op_helper.c
    M target/mips/tcg/msa_helper.c
    M target/s390x/tcg/mem_helper.c
    M target/sparc/ldst_helper.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390/tcg-target.c.inc
    M tcg/sparc/tcg-target.c.inc
    M tcg/tcg-ldst.c.inc
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci.c

  Log Message:
  -----------
  tcg: Rename TCGMemOpIdx to MemOpIdx

We're about to move this out of tcg.h, so rename it
as we did when moving MemOp.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: abe2e23eb703b7e2b0479b4672d087cc37b0e667
      
https://github.com/qemu/qemu/commit/abe2e23eb703b7e2b0479b4672d087cc37b0e667
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    A include/exec/memopidx.h
    M include/tcg/tcg.h

  Log Message:
  -----------
  tcg: Split out MemOpIdx to exec/memopidx.h

Move this code from tcg/tcg.h to its own header.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b0702c91c66a9a9d8831ecb3d08f511e7d167489
      
https://github.com/qemu/qemu/commit/b0702c91c66a9a9d8831ecb3d08f511e7d167489
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M tcg/tcg-op.c
    M trace/mem.h

  Log Message:
  -----------
  trace/mem: Pass MemOpIdx to trace_mem_get_info

We (will) often have the complete MemOpIdx handy, so use that.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c3e83e376cf028fade97072d86f33e4a92ddf9a2
      
https://github.com/qemu/qemu/commit/c3e83e376cf028fade97072d86f33e4a92ddf9a2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h

  Log Message:
  -----------
  accel/tcg: Pass MemOpIdx to atomic_trace_*_post

We will shortly use the MemOpIdx directly, but in the meantime
re-compute the trace meminfo.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 37aff08726b533c5df6a5a8685cca8a0de5e6619
      
https://github.com/qemu/qemu/commit/37aff08726b533c5df6a5a8685cca8a0de5e6619
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/cputlb.c
    M accel/tcg/plugin-gen.c
    M accel/tcg/user-exec.c
    M include/qemu/plugin.h
    M plugins/api.c
    M plugins/core.c
    M tcg/tcg-op.c

  Log Message:
  -----------
  plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb

Use the MemOpIdx directly, rather than the rearrangement
of the same bits currently done by the trace infrastructure.
Pass in enum qemu_plugin_mem_rw so that we are able to treat
read-modify-write operations as a single operation.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0583f775d2740f64739febf6496d9207552399f6
      
https://github.com/qemu/qemu/commit/0583f775d2740f64739febf6496d9207552399f6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M tcg/tcg-op.c
    M trace-events
    R trace/mem.h

  Log Message:
  -----------
  trace: Split guest_mem_before

There is no point in encoding load/store within a bit of
the memory trace info operand.  Represent atomic operations
as a single read-modify-write tracepoint.  Use MemOpIdx
instead of inventing a form specifically for traces.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dc29f4746fc8c641fb1182495c2662381cc16e23
      
https://github.com/qemu/qemu/commit/dc29f4746fc8c641fb1182495c2662381cc16e23
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M include/hw/core/cpu.h

  Log Message:
  -----------
  hw/core/cpu: Re-sort the non-pointers to the end of CPUClass

Despite the comment, the members were not kept at the end.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2552d60ebd6c519027d74bd452db7580b90e5cbd
      
https://github.com/qemu/qemu/commit/2552d60ebd6c519027d74bd452db7580b90e5cbd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/tcg-op-vec.c

  Log Message:
  -----------
  tcg: Expand usadd/ussub with umin/umax

For usadd, we only have to consider overflow.  Since ~B + B == -1,
the maximum value for A that saturates is ~B.

For ussub, we only have to consider underflow.  The minimum value
that saturates to 0 from A - B is B.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3704993f545efbe7b5a9ede83525f0d9c07cb31f
      
https://github.com/qemu/qemu/commit/3704993f545efbe7b5a9ede83525f0d9c07cb31f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M meson.build
    R tcg/s390/tcg-target-con-set.h
    R tcg/s390/tcg-target-con-str.h
    R tcg/s390/tcg-target.c.inc
    R tcg/s390/tcg-target.h
    A tcg/s390x/tcg-target-con-set.h
    A tcg/s390x/tcg-target-con-str.h
    A tcg/s390x/tcg-target.c.inc
    A tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Rename from tcg/s390

This emphasizes that we don't support s390, only 64-bit s390x hosts.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 748b7f3ef78654f0ed11c85ed0b34a02f97ea856
      
https://github.com/qemu/qemu/commit/748b7f3ef78654f0ed11c85ed0b34a02f97ea856
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Change FACILITY representation

We will shortly need to be able to check facilities beyond the
first 64.  Instead of explicitly masking against s390_facilities,
create a HAVE_FACILITY macro that indexes an array.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Change name to HAVE_FACILITY (david)


  Commit: eee6251b48f4d65e10feaff3f015241585d89f49
      
https://github.com/qemu/qemu/commit/eee6251b48f4d65e10feaff3f015241585d89f49
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg

They are rightly values in the same enumeration.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 34ef7676090e35ffb7f7d8b8d92a843a6ee94931
      
https://github.com/qemu/qemu/commit/34ef7676090e35ffb7f7d8b8d92a843a6ee94931
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target-con-str.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    A tcg/s390x/tcg-target.opc.h

  Log Message:
  -----------
  tcg/s390x: Add host vector framework

Add registers and function stubs.  The functionality
is disabled via squashing s390_facilities[2] to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2dabf74252e2b9b9f23b1991d69a8def61442a2c
      
https://github.com/qemu/qemu/commit/2dabf74252e2b9b9f23b1991d69a8def61442a2c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Implement tcg_out_ld/st for vector types

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b33ce7251c9591635ca0f93bf5e75e7dbb844b5c
      
https://github.com/qemu/qemu/commit/b33ce7251c9591635ca0f93bf5e75e7dbb844b5c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Implement tcg_out_mov for vector types

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 79cada8693d3e32162e41323b4bfbeaa765cad35
      
https://github.com/qemu/qemu/commit/79cada8693d3e32162e41323b4bfbeaa765cad35
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Implement tcg_out_dup*_vec

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a429ee2978a1bb81cfb737e382a47c119a2c0886
      
https://github.com/qemu/qemu/commit/a429ee2978a1bb81cfb737e382a47c119a2c0886
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Implement minimal vector operations

Implementing add, sub, and, or, xor as the minimal set.
This allows us to actually enable vectors in query_s390_facilities.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ae77bbe5747dc655bed213006798f9b07e2f79bf
      
https://github.com/qemu/qemu/commit/ae77bbe5747dc655bed213006798f9b07e2f79bf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional but trivial.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 479b61cbfafba997b97aec2e4d323c86240c24b0
      
https://github.com/qemu/qemu/commit/479b61cbfafba997b97aec2e4d323c86240c24b0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement TCG_TARGET_HAS_mul_vec

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 22cb37b41720c8bcd48941b29b7c6ac1f990ab94
      
https://github.com/qemu/qemu/commit/22cb37b41720c8bcd48941b29b7c6ac1f990ab94
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement vector shift operations

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 220db7a6c461d9e33a50134f72a2e0cb3c6c5e62
      
https://github.com/qemu/qemu/commit/220db7a6c461d9e33a50134f72a2e0cb3c6c5e62
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4223c9c1c6358f65fb2df2708c86f95faf235e30
      
https://github.com/qemu/qemu/commit/4223c9c1c6358f65fb2df2708c86f95faf235e30
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.opc.h

  Log Message:
  -----------
  tcg/s390x: Implement TCG_TARGET_HAS_sat_vec

The unsigned saturations are handled via generic code
using min/max.  The signed saturations are expanded using
double-sized arithmetic and a saturating pack.

Since all operations are done via expansion, do not
actually set TCG_TARGET_HAS_sat_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9bca986df88b8ea46b100e3d21cc9e653c83e0b3
      
https://github.com/qemu/qemu/commit/9bca986df88b8ea46b100e3d21cc9e653c83e0b3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ea3f2af8f1b87d7bced9b75ef2e788b66ec49961
      
https://github.com/qemu/qemu/commit/ea3f2af8f1b87d7bced9b75ef2e788b66ec49961
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec

This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6723ff639cace5c91a7e0508fe08ea58675442d6
      
https://github.com/qemu/qemu/commit/6723ff639cace5c91a7e0508fe08ea58675442d6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-06 (Wed, 06 Oct 2021)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h
    M accel/tcg/cputlb.c
    M accel/tcg/plugin-gen.c
    M accel/tcg/user-exec.c
    M include/exec/memop.h
    A include/exec/memopidx.h
    M include/hw/core/cpu.h
    M include/qemu/plugin.h
    M include/tcg/tcg.h
    M meson.build
    M plugins/api.c
    M plugins/core.c
    M target/arm/helper-a64.c
    M target/arm/m_helper.c
    M target/arm/translate-a64.c
    M target/i386/tcg/mem_helper.c
    M target/m68k/op_helper.c
    M target/mips/tcg/msa_helper.c
    M target/s390x/tcg/mem_helper.c
    M target/s390x/tcg/translate_vx.c.inc
    M target/sparc/ldst_helper.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    R tcg/s390/tcg-target-con-set.h
    R tcg/s390/tcg-target-con-str.h
    R tcg/s390/tcg-target.c.inc
    R tcg/s390/tcg-target.h
    A tcg/s390x/tcg-target-con-set.h
    A tcg/s390x/tcg-target-con-str.h
    A tcg/s390x/tcg-target.c.inc
    A tcg/s390x/tcg-target.h
    A tcg/s390x/tcg-target.opc.h
    M tcg/sparc/tcg-target.c.inc
    M tcg/tcg-ldst.c.inc
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci.c
    M tests/docker/Makefile.include
    M tests/docker/dockerfiles/fedora-i386-cross.docker
    M trace-events
    R trace/mem.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211006' into staging

More fixes for fedora-i386-cross
Add dup_const_tl
Expand MemOp MO_SIZE
Move MemOpIdx out of tcg.h
Vector support for tcg/s390x

# gpg: Signature made Wed 06 Oct 2021 08:12:53 AM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* remotes/rth/tags/pull-tcg-20211006: (28 commits)
  tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec
  tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec
  tcg/s390x: Implement TCG_TARGET_HAS_sat_vec
  tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec
  tcg/s390x: Implement vector shift operations
  tcg/s390x: Implement TCG_TARGET_HAS_mul_vec
  tcg/s390x: Implement andc, orc, abs, neg, not vector operations
  tcg/s390x: Implement minimal vector operations
  tcg/s390x: Implement tcg_out_dup*_vec
  tcg/s390x: Implement tcg_out_mov for vector types
  tcg/s390x: Implement tcg_out_ld/st for vector types
  tcg/s390x: Add host vector framework
  tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg
  tcg/s390x: Change FACILITY representation
  tcg/s390x: Rename from tcg/s390
  tcg: Expand usadd/ussub with umin/umax
  hw/core/cpu: Re-sort the non-pointers to the end of CPUClass
  trace: Split guest_mem_before
  plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
  accel/tcg: Pass MemOpIdx to atomic_trace_*_post
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/5564f068162d...6723ff639cac
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