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[Qemu-commits] [qemu/qemu] a1477d: hvf: Add Apple Silicon support

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] a1477d: hvf: Add Apple Silicon support
Date: Tue, 21 Sep 2021 08:32:58 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a1477da3ddeb1b76adb71af7b5c46a18120dc952
      
https://github.com/qemu/qemu/commit/a1477da3ddeb1b76adb71af7b5c46a18120dc952
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-09-20 (Mon, 20 Sep 2021)

  Changed paths:
    M MAINTAINERS
    M accel/hvf/hvf-accel-ops.c
    M include/sysemu/hvf_int.h
    M meson.build
    A target/arm/hvf/hvf.c
    A target/arm/hvf/trace-events
    M target/i386/hvf/hvf.c

  Log Message:
  -----------
  hvf: Add Apple Silicon support

With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.

This patch adds all necessary architecture specific code to get basic VMs
working, including save/restore.

Known limitations:

  - WFI handling is missing (follows in later patch)
  - No watchpoint/breakpoint support

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-5-agraf@csgraf.de
[PMM: added missing #include]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 219c101fa7f9c528458cd6a491af371f01e20cba
      
https://github.com/qemu/qemu/commit/219c101fa7f9c528458cd6a491af371f01e20cba
  Author: Peter Collingbourne <pcc@google.com>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M include/sysemu/hvf_int.h
    M target/arm/hvf/hvf.c

  Log Message:
  -----------
  arm/hvf: Add a WFI handler

Sleep on WFI until the VTIMER is due but allow ourselves to be woken
up on IPI.

In this implementation IPI is blocked on the CPU thread at startup and
pselect() is used to atomically unblock the signal and begin sleeping.
The signal is sent unconditionally so there's no need to worry about
races between actually sleeping and the "we think we're sleeping"
state. It may lead to an extra wakeup but that's better than missing
it entirely.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210916155404.86958-6-agraf@csgraf.de
[agraf: Remove unused 'set' variable, always advance PC on WFX trap,
        support vm stop / continue operations and cntv offsets]
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 585df85efea9e4cc915737d7981cb900287c0d2a
      
https://github.com/qemu/qemu/commit/585df85efea9e4cc915737d7981cb900287c0d2a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/hvf/hvf.c
    A target/arm/hvf_arm.h
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  hvf: arm: Implement -cpu host

Now that we have working system register sync, we push more target CPU
properties into the virtual machine. That might be useful in some
situations, but is not the typical case that users want.

So let's add a -cpu host option that allows them to explicitly pass all
CPU capabilities of their host CPU into the guest.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-7-agraf@csgraf.de
[PMM: drop unnecessary #include line from .h file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2c9c0bf9d1a3eb2e6d7411887ed1653254cf11a8
      
https://github.com/qemu/qemu/commit/2c9c0bf9d1a3eb2e6d7411887ed1653254cf11a8
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/hvf/hvf.c
    M target/arm/hvf/trace-events

  Log Message:
  -----------
  hvf: arm: Implement PSCI handling

We need to handle PSCI calls. Most of the TCG code works for us,
but we can simplify it to only handle aa64 mode and we need to
handle SUSPEND differently.

This patch takes the TCG code as template and duplicates it in HVF.

To tell the guest that we support PSCI 0.2 now, update the check in
arm_cpu_initfn() as well.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-8-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 844a06bbe41d22b1ccd445e5351fb7429e49f0b7
      
https://github.com/qemu/qemu/commit/844a06bbe41d22b1ccd445e5351fb7429e49f0b7
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M meson.build
    A target/arm/hvf/meson.build
    M target/arm/meson.build

  Log Message:
  -----------
  arm: Add Hypervisor.framework build target

Now that we have all logic in place that we need to handle Hypervisor.framework
on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
can build it.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210916155404.86958-9-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dd43ac07ef6bf2dbdfd2179f7fff95aa442c0ba1
      
https://github.com/qemu/qemu/commit/dd43ac07ef6bf2dbdfd2179f7fff95aa442c0ba1
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/hvf/hvf.c

  Log Message:
  -----------
  hvf: arm: Add rudimentary PMC support

We can expose cycle counters on the PMU easily. To be as compatible as
possible, let's do so, but make sure we don't expose any other architectural
counters that we can not model yet.

This allows OSs to work that require PMU support.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-10-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 84848481c3d2c1e1b7fb375894fa20dab56b4bde
      
https://github.com/qemu/qemu/commit/84848481c3d2c1e1b7fb375894fa20dab56b4bde
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Avoid goto_tb if we're trying to exit to the main loop

Currently gen_jmp_tb() assumes that if it is called then the jump it
is handling is the only reason that we might be trying to end the TB,
so it will use goto_tb if it can.  This is usually the case: mostly
"we did something that means we must end the TB" happens on a
non-branch instruction.  However, there are cases where we decide
early in handling an instruction that we need to end the TB and
return to the main loop, and then the insn is a complex one that
involves gen_jmp_tb().  For instance, for M-profile FP instructions,
in gen_preserve_fp_state() which is called from vfp_access_check() we
want to force an exit to the main loop if lazy state preservation is
active and we are in icount mode.

Make gen_jmp_tb() look at the current value of is_jmp, and only use
goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-2-peter.maydell@linaro.org


  Commit: 85e7d1e9ff11e5df827cc7b81034b85efae7d315
      
https://github.com/qemu/qemu/commit/85e7d1e9ff11e5df827cc7b81034b85efae7d315
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration

Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4.  QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.

We're going to add come in gen_update_fp_context() which relies on
the "always 4" property.  Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause.  Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-3-peter.maydell@linaro.org


  Commit: 267022139753777bffaf3181fba1da679234d5d3
      
https://github.com/qemu/qemu/commit/267022139753777bffaf3181fba1da679234d5d3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-m-nocp.c
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add TB flag for "MVE insns not predicated"

Our current codegen for MVE always calls out to helper functions,
because some byte lanes might be predicated.  The common case is that
in fact there is no predication active and all lanes should be
updated together, so we can produce better code by detecting that and
using the TCG generic vector infrastructure.

Add a TB flag that is set when we can guarantee that there is no
active MVE predication, and a bool in the DisasContext.  Subsequent
patches will use this flag to generate improved code for some
instructions.

In most cases when the predication state changes we simply end the TB
after that instruction.  For the code called from vfp_access_check()
that handles lazy state preservation and creating a new FP context,
we can usually avoid having to try to end the TB because luckily the
new value of the flag following the register changes in those
sequences doesn't depend on any runtime decisions.  We do have to end
the TB if the guest has enabled lazy FP state preservation but not
automatic state preservation, but this is an odd corner case that is
not going to be common in real-world code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-4-peter.maydell@linaro.org


  Commit: 451f9d66cf114f5263d6bd12a21c33896dd32f80
      
https://github.com/qemu/qemu/commit/451f9d66cf114f5263d6bd12a21c33896dd32f80
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE logic ops

When not predicating, implement the MVE bitwise logical insns
directly using TCG vector operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-5-peter.maydell@linaro.org


  Commit: bc3087f2531d2ddf0d2d8f842a01db90fb1568c2
      
https://github.com/qemu/qemu/commit/bc3087f2531d2ddf0d2d8f842a01db90fb1568c2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE arithmetic ops

Optimize MVE arithmetic ops when we have a TCG
vector operation we can use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-6-peter.maydell@linaro.org


  Commit: 4b1561c4720bff2b438f53a73349aca118d6a519
      
https://github.com/qemu/qemu/commit/4b1561c4720bff2b438f53a73349aca118d6a519
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VNEG, VABS

Optimize the MVE VNEG and VABS insns by using TCG
vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-7-peter.maydell@linaro.org


  Commit: f8d94803f1d82fa9268053abd16f984bc535b3cd
      
https://github.com/qemu/qemu/commit/f8d94803f1d82fa9268053abd16f984bc535b3cd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VDUP

Optimize the MVE VDUP insns by using TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-8-peter.maydell@linaro.org


  Commit: 5cf525a8a68f5734feef8899d5eb013dde128776
      
https://github.com/qemu/qemu/commit/5cf525a8a68f5734feef8899d5eb013dde128776
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VMVN

Optimize the MVE VMVN insn by using TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-9-peter.maydell@linaro.org


  Commit: 752970ef7c82e14a65ed979ee19a8cfcd84871e4
      
https://github.com/qemu/qemu/commit/752970ef7c82e14a65ed979ee19a8cfcd84871e4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VSHL, VSHR immediate forms

Optimize the MVE VSHL and VSHR immediate forms by using TCG vector
ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-10-peter.maydell@linaro.org


  Commit: a7789fabe15ee0e0d0f227c287a5c0d01ebcc4b4
      
https://github.com/qemu/qemu/commit/a7789fabe15ee0e0d0f227c287a5c0d01ebcc4b4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VSHLL and VMOVL

Optimize the MVE VSHLL insns by using TCG vector ops when possible.
This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
with zero shift count".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-11-peter.maydell@linaro.org


  Commit: ce75c43f6db70b409bcb03f8dea05463928e12e0
      
https://github.com/qemu/qemu/commit/ce75c43f6db70b409bcb03f8dea05463928e12e0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE VSLI and VSRI

Optimize the MVE shift-and-insert insns by using TCG
vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-12-peter.maydell@linaro.org


  Commit: 4b445c926add3fdec13958736e482e88857bcad8
      
https://github.com/qemu/qemu/commit/4b445c926add3fdec13958736e482e88857bcad8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Optimize MVE 1op-immediate insns

Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to
use TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-13-peter.maydell@linaro.org


  Commit: 81ceb36b965c9d5ed5b1eb0ed80e23705802de15
      
https://github.com/qemu/qemu/commit/81ceb36b965c9d5ed5b1eb0ed80e23705802de15
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M MAINTAINERS
    M accel/hvf/hvf-accel-ops.c
    M contrib/elf2dmp/download.c
    M contrib/elf2dmp/pdb.c
    M hw/intc/arm_gicv3_cpuif.c
    M include/sysemu/hvf_int.h
    M meson.build
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    A target/arm/hvf/hvf.c
    A target/arm/hvf/meson.build
    A target/arm/hvf/trace-events
    A target/arm/hvf_arm.h
    M target/arm/internals.h
    M target/arm/kvm_arm.h
    M target/arm/machine.c
    M target/arm/meson.build
    M target/arm/translate-m-nocp.c
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/i386/hvf/hvf.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921' 
into staging

target-arm queue:
 * Optimize codegen for MVE when predication not active
 * hvf: Add Apple Silicon support
 * hw/intc: Set GIC maintenance interrupt level to only 0 or 1
 * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator
 * elf2dmp: Fix coverity nits

# gpg: Signature made Tue 21 Sep 2021 16:31:17 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210921: (27 commits)
  target/arm: Optimize MVE 1op-immediate insns
  target/arm: Optimize MVE VSLI and VSRI
  target/arm: Optimize MVE VSHLL and VMOVL
  target/arm: Optimize MVE VSHL, VSHR immediate forms
  target/arm: Optimize MVE VMVN
  target/arm: Optimize MVE VDUP
  target/arm: Optimize MVE VNEG, VABS
  target/arm: Optimize MVE arithmetic ops
  target/arm: Optimize MVE logic ops
  target/arm: Add TB flag for "MVE insns not predicated"
  target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
  target/arm: Avoid goto_tb if we're trying to exit to the main loop
  hvf: arm: Add rudimentary PMC support
  arm: Add Hypervisor.framework build target
  hvf: arm: Implement PSCI handling
  hvf: arm: Implement -cpu host
  arm/hvf: Add a WFI handler
  hvf: Add Apple Silicon support
  hvf: Introduce hvf_arch_init() callback
  hvf: Add execute to dirty log permission bitmap
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fc81bcd4ab5c...81ceb36b965c
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