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[Qemu-commits] [qemu/qemu] 3676a8: target/i386: add missing bits to CR4_
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 3676a8: target/i386: add missing bits to CR4_RESERVED_MASK |
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Date: |
Fri, 10 Sep 2021 09:54:27 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3676a8d5b24cec765d168a000b8e606b97558d67
https://github.com/qemu/qemu/commit/3676a8d5b24cec765d168a000b8e606b97558d67
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: add missing bits to CR4_RESERVED_MASK
Booting Fedora kernels with -cpu max hangs very early in boot. Disabling
the la57 CPUID bit fixes the problem. git bisect traced the regression to
commit 213ff024a2f92020290296cb9dc29c2af3d4a221 (HEAD, refs/bisect/bad)
Author: Lara Lazier <laramglazier@gmail.com>
Date: Wed Jul 21 17:26:50 2021 +0200
target/i386: Added consistency checks for CR4
All MBZ bits in CR4 must be zero. (APM2 15.5)
Added reserved bitmask and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210721152651.14683-2-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In this commit CR4_RESERVED_MASK is missing CR4_LA57_MASK and
two others. Adding this lets Fedora kernels boot once again.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Message-Id: <20210831175033.175584-1-berrange@redhat.com>
[Removed VMXE/SMXE, matching the commit message. - Paolo]
Fixes: 213ff024a2 ("target/i386: Added consistency checks for CR4", 2021-07-22)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f07b88cfb79a242ddd017ac00e5ed38942ad849
https://github.com/qemu/qemu/commit/5f07b88cfb79a242ddd017ac00e5ed38942ad849
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: VMRUN and VMLOAD canonicalizations
APM2 requires that VMRUN and VMLOAD canonicalize (sign extend to 63
from 48/57) all base addresses in the segment registers that have been
respectively loaded.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210804113058.45186-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7ab43055b497deaacab61d18424e52803497f42e
https://github.com/qemu/qemu/commit/7ab43055b497deaacab61d18424e52803497f42e
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/svm.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF feature
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210730070742.9674-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: da2c76875a1141e95adea8b437cfdfc8dee9a41c
https://github.com/qemu/qemu/commit/da2c76875a1141e95adea8b437cfdfc8dee9a41c
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/machine.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Moved int_ctl into CPUX86State structure
Moved int_ctl into the CPUX86State structure. It removes some
unnecessary stores and loads, and prepares for tracking the vIRQ
state even when it is masked due to vGIF.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: be73de94c2e7b5238e7e411f3599429a1489273f
https://github.com/qemu/qemu/commit/be73de94c2e7b5238e7e411f3599429a1489273f
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF V_IRQ masking capability
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f3654407b1ecd4d43a5c958d7ae26504b310efe1
https://github.com/qemu/qemu/commit/f3654407b1ecd4d43a5c958d7ae26504b310efe1
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added ignore TPR check in ctl_has_irq
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 54df597cda8dfe736c71e6f804ba7ff19e9e2f50
https://github.com/qemu/qemu/commit/54df597cda8dfe736c71e6f804ba7ff19e9e2f50
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added changed priority check for VIRQ
Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ce6cfb8e591fea3fbe9f84717d4f388e58757fde
https://github.com/qemu/qemu/commit/ce6cfb8e591fea3fbe9f84717d4f388e58757fde
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-09 (Thu, 09 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/svm.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added vVMLOAD and vVMSAVE feature
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode
without
causing a VMEXIT. (APM2 15.33.1)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5aa4f884f9af44fc98a6ede06854249740355b26
https://github.com/qemu/qemu/commit/5aa4f884f9af44fc98a6ede06854249740355b26
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M docs/index.rst
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
M docs/tools/qemu-img.rst
M docs/tools/qemu-nbd.rst
M docs/tools/qemu-pr-helper.rst
M docs/tools/qemu-storage-daemon.rst
M docs/tools/qemu-trace-stap.rst
Log Message:
-----------
docs: standardize book titles to === with overline
Documents within a Sphinx manual are separate files and therefore can use
different conventions for headings. However, keeping some consistency is
useful so that included files are easy to get right.
This patch uses a standard heading format for book titles, so that it is
obvious when a file sits at the top level toctree of a book or man page.
The heading is irrelevant for man pages, but keep it consistent as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 12448b95be99b127dfd846935d3092da6688b0fe
https://github.com/qemu/qemu/commit/12448b95be99b127dfd846935d3092da6688b0fe
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M docs/about/index.rst
M docs/devel/index.rst
M docs/interop/index.rst
M docs/specs/index.rst
M docs/system/index.rst
M docs/tools/index.rst
M docs/user/index.rst
Log Message:
-----------
docs: standardize directory index to --- with overline
Use a standard heading format for the index.rst file in a directory.
Using overlines makes it clear that individual documents can use e.g.
=== for chapter titles and --- for section titles, as suggested in the
Linux kernel guidelines[1]. They could do it anyway, because documents
included in a toctree are parsed separately and therefore are not tied
to the same conventions for headings. However, keeping some consistency is
useful since sometimes files are included from multiple places.
[1] https://www.kernel.org/doc/html/latest/doc-guide/sphinx.html
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1810368204cd89c8255088f0abb2e626286820cd
https://github.com/qemu/qemu/commit/1810368204cd89c8255088f0abb2e626286820cd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
Log Message:
-----------
docs/system: standardize man page sections to --- with overline
Man pages in docs/system use file inclusion heavily. Use headings with
overlines in the main files, so that the same included file work well
from both manuals and man pages.
This style of heading is a bit more heavy-weight, so it is not used by
the other man pages in interop/ and tools/. If in the future they
are changed to use include files, for example to avoid having sections
named "synopsis" or "description", they can switch to --- with overline
as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1756fefcb01ff08727c83be4bb1a32d4337bdaad
https://github.com/qemu/qemu/commit/1756fefcb01ff08727c83be4bb1a32d4337bdaad
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M docs/system/cpu-models-x86.rst.inc
A docs/system/i386/cpu.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs/system: move x86 CPU configuration to a separate document
Currently, cpu-models-x86.rst.inc is included in target-i386.rst directly.
To make the toctree more homogeneous when adding more documentation,
include it through a first-class .rst file.
Together with the previous changes to the man page skeletons, this also
frees "===" for the headings, so that cpu-models-x86.rst.inc need not
assume anything about the headings used by target-i386.rst.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f05309d8805e92a6fb9a5ee5840ad9b556f9340
https://github.com/qemu/qemu/commit/5f05309d8805e92a6fb9a5ee5840ad9b556f9340
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M meson.build
Log Message:
-----------
meson.build: Do not look for VNC-related libraries if have_system is not set
When running "./configure --static --disable-system" there is currently
a warning if the static version of libpng is missing:
WARNING: Static library 'png16' not found for dependency 'libpng', may not
be statically linked
Since it does not make sense to look for the VNC-related libraries at all
when we're building without system emulator binaries, let's add a check
for have_system here to silence this warning.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210906153939.165567-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 838b99a176ab6684d94c3c52f4976ebdb8449d8b
https://github.com/qemu/qemu/commit/838b99a176ab6684d94c3c52f4976ebdb8449d8b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M pc-bios/keymaps/meson.build
M trace/meson.build
Log Message:
-----------
meson: look up cp and dtrace with find_program()
Avoid that meson prints a "Program xyz found" test once per
custom_target.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 23081a97ce0ace1a8f57e90162549388eba05ecd
https://github.com/qemu/qemu/commit/23081a97ce0ace1a8f57e90162549388eba05ecd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M ui/meson.build
Log Message:
-----------
meson: do not use python.full_path() unnecessarily
The "python" variable is an external program and can be passed
directly to custom_target. This avoids the need to look it up
multiple times, which was previously silent but is now explicit
in recent Meson versions.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b374557244641446ec11e92c4c4a61be06b61de9
https://github.com/qemu/qemu/commit/b374557244641446ec11e92c4c4a61be06b61de9
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M ui/meson.build
Log Message:
-----------
meson: remove dead variable
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4a02aab27690ffeb29d5497a64061c30d90e3816
https://github.com/qemu/qemu/commit/4a02aab27690ffeb29d5497a64061c30d90e3816
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/nvram/fw_cfg.c
Log Message:
-----------
fw_cfg: add etc/msr_feature_control
The file already existed, but nobody had noticed the warning until now.
Add it at the bottom, since that is where unknown files go in legacy mode.
Fixes: 217f1b4a721 ("target-i386: Publish advised value of
MSR_IA32_FEATURE_CONTROL via fw_cfg")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a35a49df2a73130681fc129c6f6cf9e5b0646540
https://github.com/qemu/qemu/commit/a35a49df2a73130681fc129c6f6cf9e5b0646540
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M util/qemu-thread-posix.c
Log Message:
-----------
util: Suppress -Wstringop-overflow in qemu_thread_start
This seems to be either a glibc or gcc bug, but the code
appears to be fine with the warning suppressed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210803211907.150525-1-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 55f5c09809adeb14a047761303d0db9f4b089bff
https://github.com/qemu/qemu/commit/55f5c09809adeb14a047761303d0db9f4b089bff
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/vfio/common.c
M include/exec/memory.h
M softmmu/memory.c
M softmmu/physmem.c
Log Message:
-----------
memory: Add RAM_PROTECTED flag to skip IOMMU mappings
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 875e0818b0e8352813278689f1baa46c8cf5ee0a
https://github.com/qemu/qemu/commit/875e0818b0e8352813278689f1baa46c8cf5ee0a
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M configs/devices/i386-softmmu/default.mak
M hw/i386/Kconfig
Log Message:
-----------
Kconfig: Add CONFIG_SGX support
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-32-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 252064ca9bc2d462277f91e4d6f2ebda0917d089
https://github.com/qemu/qemu/commit/252064ca9bc2d462277f91e4d6f2ebda0917d089
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
A include/hw/i386/hostmem-epc.h
Log Message:
-----------
hostmem: Add hostmem-epc as a backend for SGX EPC
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
EPC page, hardware performs additional access control checks to
restrict access to the page. After the current page access checks
and translations are performed, the hardware checks that the EPC
page is accessible to the program currently executing. Generally an
EPC page is only accessed by the owner of the executing enclave or
an instruction which is setting up an EPC page.
Because of its unique requirements, Linux manages EPC separately from
normal memory. Similar to memfd, the device /dev/sgx_vepc can be
opened to obtain a file descriptor which can in turn be used to mmap()
EPC memory.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6efca9ca04f3be5b97bf671922ac1d7a6e263886
https://github.com/qemu/qemu/commit/6efca9ca04f3be5b97bf671922ac1d7a6e263886
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M qapi/qom.json
Log Message:
-----------
qom: Add memory-backend-epc ObjectOptions support
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX since v6.1, or the sgx backend
object cannot bootup.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-4-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cf4dde10ad2e86c8c9c0f4381b4748a890c59555
https://github.com/qemu/qemu/commit/cf4dde10ad2e86c8c9c0f4381b4748a890c59555
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/meson.build
A hw/i386/sgx-epc.c
A include/hw/i386/sgx-epc.h
Log Message:
-----------
i386: Add 'sgx-epc' device to expose EPC sections to guest
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
been created.
The 'sgx-epc' device is essentially a placholder at this time, it will
be fully implemented in a future patch along with a dedicated command
to create 'sgx-epc' devices.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 77dc9133a0bb4cb001c00f19fc2137b0d9db515f
https://github.com/qemu/qemu/commit/77dc9133a0bb4cb001c00f19fc2137b0d9db515f
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
M hw/i386/x86.c
M include/hw/i386/pc.h
M include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M qapi/machine.json
M qemu-options.hx
Log Message:
-----------
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 14ce8ea2a9359f24be453bc875e4373aded9be94
https://github.com/qemu/qemu/commit/14ce8ea2a9359f24be453bc875e4373aded9be94
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add primary SGX CPUID and MSR defines
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled (in FEATURE_CONTROL).
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6fbe783ac3460d47aab9c8df03f3f5df055382f2
https://github.com/qemu/qemu/commit/6fbe783ac3460d47aab9c8df03f3f5df055382f2
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC management
- ENCLV instruction set for VMM oversubscription of EPC
- ENCLS-C instruction set for thread safe variants of ENCLS
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 51bc1bc3418e19e2ba318f270c8f309e88a593fc
https://github.com/qemu/qemu/commit/51bc1bc3418e19e2ba318f270c8f309e88a593fc
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-9-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f4bda8cbf22a756f805ee35d39f94ca4cf65baf8
https://github.com/qemu/qemu/commit/f4bda8cbf22a756f805ee35d39f94ca4cf65baf8
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the enclave has has been initialized by EINIT. Cannot
be set by software, i.e. forced to zero in CPUID.
- DEBUG: permits a debugger to read/write into the enclave.
- MODE64BIT: the enclave runs in 64-bit mode
- PROVISIONKEY: grants has access to the provision key
- EINITTOKENKEY: grants access to the EINIT token key, i.e. the
enclave can generate EINIT tokens
- KSS: Key Separation and Sharing enabled for the enclave.
Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates
the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly
exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all
reserved and bits 127:64 correspond to the allowed XSAVE Feature Request
Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX,
AVX, etc... and is not exposed to the user.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-10-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3103ead9a84363d15015fa7b7a742e363a972f79
https://github.com/qemu/qemu/commit/3103ead9a84363d15015fa7b7a742e363a972f79
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/machine.c
Log Message:
-----------
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KVM advertises SGX LC via CPUID if and only if the MSRs are writable.
Unconditionally initialize those MSRs to digest of Intel's signing key
when CPU is realized and reset to reflect the fact. This avoids
potential bug in case kvm_arch_put_registers() is called before
kvm_arch_get_registers() is called, in which case guest's virtual
SGX_LEPUBKEYHASH MSRs will be set to 0, although KVM initializes those
to digest of Intel's signing key by default, since KVM allows those MSRs
to be updated by Qemu to support live migration.
Save/restore the SGX Launch Enclave Public Key Hash MSRs if SGX Launch
Control (LC) is exposed to the guest. Likewise, migrate the MSRs if they
are writable by the guest.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Kai Huang <kai.huang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-11-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 852f61a93466db0b03a8bbe6a08bcf1dceb604be
https://github.com/qemu/qemu/commit/852f61a93466db0b03a8bbe6a08bcf1dceb604be
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Add feature control MSR dependency when SGX is enabled
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-12-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 80590e26aef2a0d3c49649c4d70e7100f51e54ab
https://github.com/qemu/qemu/commit/80590e26aef2a0d3c49649c4d70e7100f51e54ab
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/meson.build
A hw/i386/sgx-stub.c
A hw/i386/sgx.c
M include/hw/i386/pc.h
M include/hw/i386/sgx-epc.h
M target/i386/cpu.c
Log Message:
-----------
i386: Update SGX CPUID info according to hardware/KVM/user input
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
ultimately emulation will fail as software cannot generate a valid
quote/report. The complexity of partially emulating SGX in Qemu far
outweighs the value added, e.g. an SGX specific simulator for userspace
applications can emulate SGX for development and testing purposes.
Note, access to the PROVISIONKEY is not yet advertised to the guest as
KVM blocks access to the PROVISIONKEY by default and requires userspace
to provide additional credentials (via ioctl()) to expose PROVISIONKEY.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-13-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5aead0f6b1ffb66c720186a2a87bece78ef31167
https://github.com/qemu/qemu/commit/5aead0f6b1ffb66c720186a2a87bece78ef31167
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
Log Message:
-----------
i386: kvm: Add support for exposing PROVISIONKEY to guest
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-14-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 96c9a59842fe186f69fc3ef0228e0e27f08e68e5
https://github.com/qemu/qemu/commit/96c9a59842fe186f69fc3ef0228e0e27f08e68e5
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Propagate SGX CPUID sub-leafs to KVM
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic and user
defined, the number of SGX sub-leafs is "NULL" terminated.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-15-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0c4c1e6293c802935386afecfd0292a16f4b697d
https://github.com/qemu/qemu/commit/0c4c1e6293c802935386afecfd0292a16f4b697d
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
Adjust min CPUID level to 0x12 when SGX is enabled
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-16-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b921873e2c06fee7467efa1010abbbca6f3e0f9c
https://github.com/qemu/qemu/commit/b921873e2c06fee7467efa1010abbbca6f3e0f9c
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/fw_cfg.c
Log Message:
-----------
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-17-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: de792e2be94dea18205d59c9f651cec6a65f2392
https://github.com/qemu/qemu/commit/de792e2be94dea18205d59c9f651cec6a65f2392
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/sgx-epc.h
Log Message:
-----------
hw/i386/pc: Account for SGX EPC sections when calculating device memory
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity because we don't support EPC NUMA affinity
now. Once the SGX EPC NUMA support in the kernel SGX driver, we will
support this in the future.
Note that SGX EPC is currently hardcoded to reside above 4g.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-18-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9488301edae8f52b7f125a29fc8933e2de9ea6de
https://github.com/qemu/qemu/commit/9488301edae8f52b7f125a29fc8933e2de9ea6de
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/pc: Add e820 entry for SGX EPC section(s)
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-19-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 96d80c3bc09154fb23ce4ba6f016dabf109f4e48
https://github.com/qemu/qemu/commit/96d80c3bc09154fb23ce4ba6f016dabf109f4e48
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
i386: acpi: Add SGX EPC entry to ACPI tables
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI tables,
i.e. software must enumerate the EPC sections via CPUID. Furthermore,
software expects to see only a single EPC Device in the ACPI tables
regardless of the number of EPC sections in the system.
However, several versions of Windows do rely on the ACPI tables to
enumerate the address and size of the EPC. So, regardless of the number
of EPC sections exposed to the guest, create exactly *one* EPC device
with a _CRS entry that spans the entirety of all EPC sections (which are
guaranteed to be contiguous in Qemu).
Note, NUMA support for EPC memory is intentionally not considered as
enumerating EPC NUMA information is not yet defined for bare metal.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-20-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ad0f87f8c3354f0d237ae95945276575e0d0d4fe
https://github.com/qemu/qemu/commit/ad0f87f8c3354f0d237ae95945276575e0d0d4fe
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
q35: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-21-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b83210ba72fa02a5b22e03a8fde5fbd75f900a1a
https://github.com/qemu/qemu/commit/b83210ba72fa02a5b22e03a8fde5fbd75f900a1a
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
i440fx: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-22-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c126481e6d0fde8fd9c54a89c6b844171d08b83d
https://github.com/qemu/qemu/commit/c126481e6d0fde8fd9c54a89c6b844171d08b83d
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
M monitor/hmp-cmds.c
M qapi/machine.json
Log Message:
-----------
sgx-epc: Add the fill_device_info() callback support
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info memory-devices
Memory device [sgx-epc]: ""
memaddr: 0x180000000
size: 29360128
memdev: /objects/mem1
Memory device [sgx-epc]: ""
memaddr: 0x181c00000
size: 10485760
memdev: /objects/mem2
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-33-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e909ed9fe827acba5bbd6f804f04766a8879fe01
https://github.com/qemu/qemu/commit/e909ed9fe827acba5bbd6f804f04766a8879fe01
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
A docs/system/i386/sgx.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs/system: Add SGX documentation to the system manual
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-34-yang.zhong@intel.com>
[Convert to reStructuredText, and adopt the standard === --- ~~~ headings
suggested for example by Linux. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d338cbe722a6719e4b13a06fc6753fb4d95a98d2
https://github.com/qemu/qemu/commit/d338cbe722a6719e4b13a06fc6753fb4d95a98d2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-10 (Fri, 10 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
M configs/devices/i386-softmmu/default.mak
M docs/about/index.rst
M docs/devel/index.rst
M docs/index.rst
M docs/interop/index.rst
M docs/specs/index.rst
M docs/system/cpu-models-x86.rst.inc
A docs/system/i386/cpu.rst
A docs/system/i386/sgx.rst
M docs/system/index.rst
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
M docs/system/target-i386.rst
M docs/tools/index.rst
M docs/tools/qemu-img.rst
M docs/tools/qemu-nbd.rst
M docs/tools/qemu-pr-helper.rst
M docs/tools/qemu-storage-daemon.rst
M docs/tools/qemu-trace-stap.rst
M docs/user/index.rst
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/fw_cfg.c
M hw/i386/meson.build
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
A hw/i386/sgx-epc.c
A hw/i386/sgx-stub.c
A hw/i386/sgx.c
M hw/i386/x86.c
M hw/nvram/fw_cfg.c
M hw/vfio/common.c
M include/exec/memory.h
A include/hw/i386/hostmem-epc.h
M include/hw/i386/pc.h
A include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M meson.build
M monitor/hmp-cmds.c
M pc-bios/keymaps/meson.build
M qapi/machine.json
M qapi/qom.json
M qemu-options.hx
M softmmu/memory.c
M softmmu/physmem.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/machine.c
M target/i386/svm.h
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
M trace/meson.build
M ui/meson.build
M util/qemu-thread-posix.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into
staging
* SGX support (Sean, Yang)
* vGIF and vVMLOAD/VMSAVE support (Lara)
* Fix LA57 support in TCG (Daniel)
* Avoid pointless warnings for static user-only compilation (Thomas)
* Avoid repeated detection of programs
* target-i386.rst restructuring
# gpg: Signature made Fri 10 Sep 2021 10:49:00 BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (42 commits)
docs/system: Add SGX documentation to the system manual
sgx-epc: Add the fill_device_info() callback support
i440fx: Add support for SGX EPC
q35: Add support for SGX EPC
i386: acpi: Add SGX EPC entry to ACPI tables
i386/pc: Add e820 entry for SGX EPC section(s)
hw/i386/pc: Account for SGX EPC sections when calculating device memory
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Adjust min CPUID level to 0x12 when SGX is enabled
i386: Propagate SGX CPUID sub-leafs to KVM
i386: kvm: Add support for exposing PROVISIONKEY to guest
i386: Update SGX CPUID info according to hardware/KVM/user input
i386: Add feature control MSR dependency when SGX is enabled
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
i386: Add primary SGX CPUID and MSR defines
vl: Add sgx compound properties to expose SGX EPC sections to guest
i386: Add 'sgx-epc' device to expose EPC sections to guest
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/668a38c6f92c...d338cbe722a6
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