[Qemu-commits] [qemu/qemu] c8b69a: target/mips: Remove JR opcode unused

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[Qemu-commits] [qemu/qemu] c8b69a: target/mips: Remove JR opcode unused

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] c8b69a: target/mips: Remove JR opcode unused arguments
Date:	Wed, 25 Aug 2021 13:15:23 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: c8b69a2a92bebed915af69bb685816e715956ecc
      
https://github.com/qemu/qemu/commit/c8b69a2a92bebed915af69bb685816e715956ecc
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Remove JR opcode unused arguments

JR opcode (Jump Register) only takes 1 argument, $rs.
JALR (Jump And Link Register) takes 3: $rs, $rd and $hint.

Commit 6af0bf9c7c3 added their processing into decode_opc() as:

    case 0x08 ... 0x09: /* Jumps */
        gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);

having both opcodes handled in the same function: gen_compute_branch.

Per JR encoding, both $rd and $hint ('sa') are decoded as zero.

Later this code got extracted to decode_opc_special(),
commit 7a387fffce5 used definitions instead of magic values:

    case OPC_JR ... OPC_JALR:
        gen_compute_branch(ctx, op1, rs, rd, sa);

Finally commit 0aefa33318b moved OPC_JR out of decode_opc_special,
to a new 'decode_opc_special_legacy' function:

  @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState 
*env, DisasContext *ctx)
  +    case OPC_JR:
  +        gen_compute_branch(ctx, op1, 4, rs, rd, sa);
  +        break;

  @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, 
DisasContext *ctx)
  -    case OPC_JR ... OPC_JALR:
  +    case OPC_JALR:
           gen_compute_branch(ctx, op1, 4, rs, rd, sa);
           break;

Since JR is now handled individually, it is pointless to decode
and pass it unused arguments. Replace them by simple zero value
to avoid confusion with this opcode.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210730225507.2642827-1-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2e176eaf9c54a23ea2f37ccbeef2045f422b0e30
      
https://github.com/qemu/qemu/commit/2e176eaf9c54a23ea2f37ccbeef2045f422b0e30
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Simplify PREF opcode

check_insn() checks for any bit in the set, and INSN_R5900 is
just another bit added to the set. No need to special-case it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-2-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4919f69c658be36c97d63660bd41377b06ea6822
      
https://github.com/qemu/qemu/commit/4919f69c658be36c97d63660bd41377b06ea6822
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Decode vendor extensions before MIPS ISAs

In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
opcodes to decodetree") we misplaced the decoder call. Move
it to the correct place.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 12f79f11731194d7cb61c4a0d9b2de5416a773de
      
https://github.com/qemu/qemu/commit/12f79f11731194d7cb61c4a0d9b2de5416a773de
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/meson.build
    R target/mips/tcg/mips32r6.decode
    R target/mips/tcg/mips64r6.decode
    A target/mips/tcg/rel6.decode
    M target/mips/tcg/rel6_translate.c

  Log Message:
  -----------
  target/mips: Merge 32-bit/64-bit Release6 decodetree definitions

We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-4-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 34fe9fa3683a7ff54315c62960eba6eeac2a36ac
      
https://github.com/qemu/qemu/commit/34fe9fa3683a7ff54315c62960eba6eeac2a36ac
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c
    M target/mips/tcg/rel6.decode
    M target/mips/tcg/rel6_translate.c
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips: Rename 'rtype' as 'r'

We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-5-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fb3164e412dac312cc472968d049ee1a074dd7d3
      
https://github.com/qemu/qemu/commit/fb3164e412dac312cc472968d049ee1a074dd7d3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.h

  Log Message:
  -----------
  target/mips: Introduce generic TRANS() macro for decodetree helpers

Plain copy/paste of the TRANS() macro introduced in the PPC
commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer
loads to decodetree") to the MIPS target.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210808173018.90960-2-f4bug@amsat.org>


  Commit: 07565cbf4abb81efa6dc4742c243bdc4b3444398
      
https://github.com/qemu/qemu/commit/07565cbf4abb81efa6dc4742c243bdc4b3444398
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/helper.h
    A target/mips/tcg/vr54xx_helper.h.inc

  Log Message:
  -----------
  target/mips: Extract NEC Vr54xx helper definitions

Extract the NEC Vr54xx helper definitions to
'vendor-vr54xx_helper.h'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-15-f4bug@amsat.org>


  Commit: 6629f79f53ea9a1caa3f3c842fa3d02488116486
      
https://github.com/qemu/qemu/commit/6629f79f53ea9a1caa3f3c842fa3d02488116486
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/meson.build
    M target/mips/tcg/op_helper.c
    A target/mips/tcg/vr54xx_helper.c

  Log Message:
  -----------
  target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c

Extract NEC Vr54xx helpers from op_helper.c to a new file:
'vr54xx_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-14-f4bug@amsat.org>


  Commit: 9d0053923904215d95e8e5ab14b38bb792a0a68f
      
https://github.com/qemu/qemu/commit/9d0053923904215d95e8e5ab14b38bb792a0a68f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/meson.build
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h
    A target/mips/tcg/vr54xx.decode
    A target/mips/tcg/vr54xx_translate.c

  Log Message:
  -----------
  target/mips: Introduce decodetree structure for NEC Vr54xx extension

The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801235926.3178085-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5fa38eedbd0b3fad052a11c5efc8031a20ed9b25
      
https://github.com/qemu/qemu/commit/5fa38eedbd0b3fad052a11c5efc8031a20ed9b25
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/vr54xx.decode
    M target/mips/tcg/vr54xx_translate.c

  Log Message:
  -----------
  target/mips: Convert Vr54xx MACC* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

 * MACC         Multiply, accumulate, and move LO
 * MACCHI       Multiply, accumulate, and move HI
 * MACCHIU      Unsigned multiply, accumulate, and move HI
 * MACCU        Unsigned multiply, accumulate, and move LO

Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>


  Commit: a5e2932068f1b09fa3be3b79a88f935b6e9620c3
      
https://github.com/qemu/qemu/commit/a5e2932068f1b09fa3be3b79a88f935b6e9620c3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/vr54xx.decode
    M target/mips/tcg/vr54xx_translate.c

  Log Message:
  -----------
  target/mips: Convert Vr54xx MUL* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

 * MULHI        Multiply and move HI
 * MULHIU       Unsigned multiply and move HI
 * MULS         Multiply, negate, and move LO
 * MULSHI       Multiply, negate, and move HI
 * MULSHIU      Unsigned multiply, negate, and move HI
 * MULSU        Unsigned multiply, negate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-7-f4bug@amsat.org>


  Commit: bf7720024c62c9e2707b11aa7fe178be691b2f35
      
https://github.com/qemu/qemu/commit/bf7720024c62c9e2707b11aa7fe178be691b2f35
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/vr54xx.decode
    M target/mips/tcg/vr54xx_translate.c

  Log Message:
  -----------
  target/mips: Convert Vr54xx MSA* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

 * MSAC         Multiply, negate, accumulate, and move LO
 * MSACHI       Multiply, negate, accumulate, and move HI
 * MSACHIU      Unsigned multiply, negate, accumulate, and move HI
 * MSACU        Unsigned multiply, negate, accumulate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-8-f4bug@amsat.org>


  Commit: 98d207cf9c232e6ac451b2aba24baa007956f578
      
https://github.com/qemu/qemu/commit/98d207cf9c232e6ac451b2aba24baa007956f578
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/cpu-defs.c.inc

  Log Message:
  -----------
  target/mips: Document Loongson-3A CPU definitions

Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>


  Commit: 71ed30b7d4c7bc7d8069eba601d7384e378f3024
      
https://github.com/qemu/qemu/commit/71ed30b7d4c7bc7d8069eba601d7384e378f3024
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/cpu-defs.c.inc

  Log Message:
  -----------
  target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.

Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>


  Commit: c1feb46d12a7e7aeed804f2cca69f509c1bea8ef
      
https://github.com/qemu/qemu/commit/c1feb46d12a7e7aeed804f2cca69f509c1bea8ef
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT

We already call check_cp1_enabled() earlier in the "pre-conditions"
checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue.
Remove the duplicated calls.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210816001031.1720432-1-f4bug@amsat.org>


  Commit: b24339bcd05b9d772f86c74732932bac98a15f4e
      
https://github.com/qemu/qemu/commit/b24339bcd05b9d772f86c74732932bac98a15f4e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Remove gen_helper_0e3i()

gen_helper_0e3i() is unused since commit 895c2d04359
("target-mips: switch to AREG0 free mode"), remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-2-f4bug@amsat.org>


  Commit: 53152abfc148ebfb7843ef3596f4be5bc8e5eff9
      
https://github.com/qemu/qemu/commit/53152abfc148ebfb7843ef3596f4be5bc8e5eff9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Remove gen_helper_1e2i()

gen_helper_1e2i() is unused since commit 33a07fa2db6
("target/mips: reimplement SC instruction emulation
and use cmpxchg"), remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-3-f4bug@amsat.org>


  Commit: 78bdd3886577ce4f3e573685b155622e19bcca38
      
https://github.com/qemu/qemu/commit/78bdd3886577ce4f3e573685b155622e19bcca38
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in gen_helper_0e2i()

$rt register is used read-only, so we can replace tcg_const_i32()
temporary by tcg_constant_i32().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>


  Commit: 26fe92763aaf3b0d704fbdb32daf434147dc6ca7
      
https://github.com/qemu/qemu/commit/26fe92763aaf3b0d704fbdb32daf434147dc6ca7
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Simplify gen_helper() macros by using tcg_constant_i32()

In all call sites the last argument is always used as a
read-only value, so we can replace tcg_const_i32() temporary
by tcg_constant_i32().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-5-f4bug@amsat.org>


  Commit: a1b4b060d756dbc2d221d340b7adbc3e694e06d6
      
https://github.com/qemu/qemu/commit/a1b4b060d756dbc2d221d340b7adbc3e694e06d6
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros

gen_helper_1e1i() is one-line long and is used in one place:
simply inline it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-6-f4bug@amsat.org>


  Commit: ae71abadd58037dd457f021f9be381e32f1815ec
      
https://github.com/qemu/qemu/commit/ae71abadd58037dd457f021f9be381e32f1815ec
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Inline gen_helper_0e0i()

gen_helper_0e0i() is one-line long and is only used twice:
simply inline it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>


  Commit: a8b18de7f5f8283633e5fc3378fbd6d0c9f4a1ae
      
https://github.com/qemu/qemu/commit/a8b18de7f5f8283633e5fc3378fbd6d0c9f4a1ae
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in generate_exception_err()

excp/err are temporaries input, so we can replace tcg_const_i32()
calls by tcg_constant_i32() equivalent.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>


  Commit: 761533fc9a8df2e7d276b7e1fc22cad7d0fd0352
      
https://github.com/qemu/qemu/commit/761533fc9a8df2e7d276b7e1fc22cad7d0fd0352
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h

  Log Message:
  -----------
  target/mips: Define gen_helper() macros in translate.h

To be able to split some code calling the gen_helper() macros
out of the huge translate.c, we need to define them in the
'translate.h' local header.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-9-f4bug@amsat.org>


  Commit: 5b3cc34c346e216c81f0750f586a016c33f2e08f
      
https://github.com/qemu/qemu/commit/5b3cc34c346e216c81f0750f586a016c33f2e08f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/ldst_helper.c

  Log Message:
  -----------
  target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

As a first step, inline the GET_OFFSET() macro, calling
cpu_is_bigendian() to get the 'direction' of the offset.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-2-f4bug@amsat.org>


  Commit: 4885b99a6e05d16f40af18a062a5cb45fa92ec27
      
https://github.com/qemu/qemu/commit/4885b99a6e05d16f40af18a062a5cb45fa92ec27
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/ldst_helper.c

  Log Message:
  -----------
  target/mips: Replace GET_LMASK() macro by get_lmask(32) function

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.

We can remove one use of the TARGET_WORDS_BIGENDIAN definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-3-f4bug@amsat.org>


  Commit: 23a04dcdf6fa6b34933778b16ee8200027dc6e68
      
https://github.com/qemu/qemu/commit/23a04dcdf6fa6b34933778b16ee8200027dc6e68
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/ldst_helper.c

  Log Message:
  -----------
  target/mips: Replace GET_LMASK64() macro by get_lmask(64) function

The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.

Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.

We can remove another use of the TARGET_WORDS_BIGENDIAN definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818215517.2560994-4-f4bug@amsat.org>


  Commit: 0cfd392d7b419cdbe5284b8227d95ab3daaea860
      
https://github.com/qemu/qemu/commit/0cfd392d7b419cdbe5284b8227d95ab3daaea860
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h

  Log Message:
  -----------
  target/mips: Store CP0_Config0 in DisasContext

Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818164321.2474534-5-f4bug@amsat.org>


  Commit: bf78469cc8ddb117b6db4a353e59fb4664a96de4
      
https://github.com/qemu/qemu/commit/bf78469cc8ddb117b6db4a353e59fb4664a96de4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h

  Log Message:
  -----------
  target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()

Add the inlined cpu_is_bigendian() function in "translate.h".

Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210818164321.2474534-6-f4bug@amsat.org>


  Commit: d8ae530ec00368d4adfb996b5ef6c74cb4460504
      
https://github.com/qemu/qemu/commit/d8ae530ec00368d4adfb996b5ef6c74cb4460504
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/mips/cpu-defs.c.inc
    M target/mips/helper.h
    M target/mips/tcg/ldst_helper.c
    M target/mips/tcg/meson.build
    R target/mips/tcg/mips32r6.decode
    R target/mips/tcg/mips64r6.decode
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/op_helper.c
    A target/mips/tcg/rel6.decode
    M target/mips/tcg/rel6_translate.c
    M target/mips/tcg/translate.c
    M target/mips/tcg/translate.h
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c
    A target/mips/tcg/vr54xx.decode
    A target/mips/tcg/vr54xx_helper.c
    A target/mips/tcg/vr54xx_helper.h.inc
    A target/mips/tcg/vr54xx_translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr

# gpg: Signature made Wed 25 Aug 2021 12:04:31 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210825: (28 commits)
  target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()
  target/mips: Store CP0_Config0 in DisasContext
  target/mips: Replace GET_LMASK64() macro by get_lmask(64) function
  target/mips: Replace GET_LMASK() macro by get_lmask(32) function
  target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers
  target/mips: Define gen_helper() macros in translate.h
  target/mips: Use tcg_constant_i32() in generate_exception_err()
  target/mips: Inline gen_helper_0e0i()
  target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros
  target/mips: Simplify gen_helper() macros by using tcg_constant_i32()
  target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
  target/mips: Remove gen_helper_1e2i()
  target/mips: Remove gen_helper_0e3i()
  target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT
  target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
  target/mips: Document Loongson-3A CPU definitions
  target/mips: Convert Vr54xx MSA* opcodes to decodetree
  target/mips: Convert Vr54xx MUL* opcodes to decodetree
  target/mips: Convert Vr54xx MACC* opcodes to decodetree
  target/mips: Introduce decodetree structure for NEC Vr54xx extension
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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