[Qemu-commits] [qemu/qemu] 518470: target/riscv: pmp: Fix some typos

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 5184701e929d5810fc8c53d7e7f1828d9ceb9bba
      
https://github.com/qemu/qemu/commit/5184701e929d5810fc8c53d7e7f1828d9ceb9bba
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: pmp: Fix some typos

%s/CSP/CSR
%s/thie/the

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 657e992ce320a837cc07fc79ebffbd7ecabcb95b
      
https://github.com/qemu/qemu/commit/657e992ce320a837cc07fc79ebffbd7ecabcb95b
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: csr: Remove redundant check in fp csr read/write routines

The following check:

    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
        return -RISCV_EXCP_ILLEGAL_INST;
    }

is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 29b088d29ccfc7117cf1a1ee71d041e5afb1aaa4
      
https://github.com/qemu/qemu/commit/29b088d29ccfc7117cf1a1ee71d041e5afb1aaa4
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M docs/system/riscv/sifive_u.rst

  Log Message:
  -----------
  docs/system: riscv: Fix CLINT name in the sifive_u doc

It's Core *Local* Interruptor, not 'Level'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d8136159530dbd152849d2c2285a3e53b8c559f2
      
https://github.com/qemu/qemu/commit/d8136159530dbd152849d2c2285a3e53b8c559f2
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    A docs/system/riscv/virt.rst
    M docs/system/target-riscv.rst

  Log Message:
  -----------
  docs/system: riscv: Add documentation for virt machine

This adds detailed documentation for RISC-V `virt` machine,
including the following information:

  - Supported devices
  - Hardware configuration information
  - Boot options
  - Running Linux kernel
  - Running U-Boot

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: da716525f97e3d4ba829e8c48699602a402f5977
      
https://github.com/qemu/qemu/commit/da716525f97e3d4ba829e8c48699602a402f5977
  Author: Jose Martins <josemartins90@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: hardwire bits in hideleg and hedeleg

The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
 - Improve indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e433ac45c0387e749c5fc8ab80869a7db78ebd04
      
https://github.com/qemu/qemu/commit/e433ac45c0387e749c5fc8ab80869a7db78ebd04
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M docs/system/riscv/microchip-icicle-kit.rst

  Log Message:
  -----------
  docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot

This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.

It also updates the truth table to have a new '-dtb' column which is
required by direct kernel boot.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9130414cc3fb1b3c9feefa24c4beddd7ccbdbfe4
      
https://github.com/qemu/qemu/commit/9130414cc3fb1b3c9feefa24c4beddd7ccbdbfe4
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Correct the CLINT timebase frequency

At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d0634c883b168d663d50b6c76e39f7406895b928
      
https://github.com/qemu/qemu/commit/d0634c883b168d663d50b6c76e39f7406895b928
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Currently the firmware dynamic info (fw_dyn) is put right after
the reset vector, which is not 8-byte aligned on RV64. OpenSBI
fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
which expects fw_dyn to be on the 8-byte boundary, otherwise the
misaligned load exception may happen. Fortunately this does not
cause any issue on QEMU, as QEMU does support misaligned load.

RV32 does not have any issue as it is 4-byte aligned already.
Change to make sure it is 8-byte aligned which works for both
RV32 and RV64.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cb6f21ae9565d629e7b2340b8ff9e9805df221d6
      
https://github.com/qemu/qemu/commit/cb6f21ae9565d629e7b2340b8ff9e9805df221d6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M hw/char/ibex_uart.c

  Log Message:
  -----------
  char: ibex_uart: Update the register layout

Update the register layout to match the latest OpenTitan bitstream.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com


  Commit: 0119186085d83279b000572d142bd215d11deaa0
      
https://github.com/qemu/qemu/commit/0119186085d83279b000572d142bd215d11deaa0
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com


  Commit: d6b87906f09f72a837dc68c33bfc3d913ef74b7d
      
https://github.com/qemu/qemu/commit/d6b87906f09f72a837dc68c33bfc3d913ef74b7d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: opentitan: Add the flash alias

OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com


  Commit: 961fef0ace0b2a997544deec2f01981b9c9c96e3
      
https://github.com/qemu/qemu/commit/961fef0ace0b2a997544deec2f01981b9c9c96e3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M docs/system/riscv/microchip-icicle-kit.rst
    M docs/system/riscv/sifive_u.rst
    A docs/system/riscv/virt.rst
    M docs/system/target-riscv.rst
    M hw/char/ibex_uart.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M include/hw/riscv/opentitan.h
    M target/riscv/csr.c
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210712' into staging

Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates

# gpg: Signature made Mon 12 Jul 2021 23:53:01 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210712:
  hw/riscv: opentitan: Add the flash alias
  hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
  char: ibex_uart: Update the register layout
  hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
  hw/riscv: sifive_u: Correct the CLINT timebase frequency
  docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
  target/riscv: hardwire bits in hideleg and hedeleg
  docs/system: riscv: Add documentation for virt machine
  docs/system: riscv: Fix CLINT name in the sifive_u doc
  target/riscv: csr: Remove redundant check in fp csr read/write routines
  target/riscv: pmp: Fix some typos

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/9a367ac8fda7...961fef0ace0b