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[Qemu-commits] [qemu/qemu] 82faef: hw/acpi: Provide stub version of acpi
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 82faef: hw/acpi: Provide stub version of acpi_ghes_record_... |
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Date: |
Thu, 24 Jun 2021 11:45:57 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 82faef92fb149b6bad699c3275473fda6fd486b6
https://github.com/qemu/qemu/commit/82faef92fb149b6bad699c3275473fda6fd486b6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
A hw/acpi/ghes-stub.c
M hw/acpi/meson.build
Log Message:
-----------
hw/acpi: Provide stub version of acpi_ghes_record_errors()
Generic code in target/arm wants to call acpi_ghes_record_errors();
provide a stub version so that we don't fail to link when
CONFIG_ACPI_APEI is not set. This requires us to add a new
ghes-stub.c file to contain it and the meson.build mechanics
to use it when appropriate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Message-id: 20210603171259.27962-2-peter.maydell@linaro.org
Commit: 1c81f5735af3e2356bb75482a58786a4f26d8300
https://github.com/qemu/qemu/commit/1c81f5735af3e2356bb75482a58786a4f26d8300
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/acpi/ghes-stub.c
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
Log Message:
-----------
hw/acpi: Provide function acpi_ghes_present()
Allow code elsewhere in the system to check whether the ACPI GHES
table is present, so it can determine whether it is OK to try to
record an error by calling acpi_ghes_record_errors().
(We don't need to migrate the new 'present' field in AcpiGhesState,
because it is set once at system initialization and doesn't change.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Message-id: 20210603171259.27962-3-peter.maydell@linaro.org
Commit: 15613357ba53a4763594f64476058b85b3014757
https://github.com/qemu/qemu/commit/15613357ba53a4763594f64476058b85b3014757
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
The virt_is_acpi_enabled() function is specific to the virt board, as
is the check for its 'ras' property. Use the new acpi_ghes_present()
function to check whether we should report memory errors via
acpi_ghes_record_errors().
This avoids a link error if QEMU was built without support for the
virt board, and provides a mechanism that can be used by any future
board models that want to add ACPI memory error reporting support
(they only need to call acpi_ghes_add_fw_cfg()).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Message-id: 20210603171259.27962-4-peter.maydell@linaro.org
Commit: 741292face087213b846faed7055ff51b7fee2dd
https://github.com/qemu/qemu/commit/741292face087213b846faed7055ff51b7fee2dd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
A docs/system/arm/emulation.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs/system/arm: Document which architecture extensions we emulate
These days the Arm architecture has a wide range of fine-grained
optional extra architectural features. We implement quite a lot
of these but by no means all of them. Document what we do implement,
so that users can find out without having to dig through back-issues
of our Changelog on the wiki.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210617140328.28622-1-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 41b3ffc59966c78383e177e1dd38f884e886d960
https://github.com/qemu/qemu/commit/41b3ffc59966c78383e177e1dd38f884e886d960
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm/translate-vfp.c: Whitespace fixes
In the code for handling VFP system register accesses there is some
stray whitespace after a unary '-' operator, and also some incorrect
indent in a couple of function prototypes. We're about to move this
code to another file, so fix the code style issues first so
checkpatch doesn't complain about the code-movement patch.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-2-peter.maydell@linaro.org
Commit: 9931d9d84bec87fae30b69590420d8ae459387a6
https://github.com/qemu/qemu/commit/9931d9d84bec87fae30b69590420d8ae459387a6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Handle FPU being disabled in FPCXT_NS accesses
If the guest makes an FPCXT_NS access when the FPU is disabled,
one of two things happens:
* if there is no active FP context, then the insn behaves the
same way as if the FPU was enabled: writes ignored, reads
same value as FPDSCR_NS
* if there is an active FP context, then we take a NOCP
exception
Add code to the sysreg read/write functions which emits
code to take the NOCP exception in the latter case.
At the moment this will never be used, because the NOCP checks in
m-nocp.decode happen first, and so the trans functions are never
called when the FPU is disabled. The code will be needed when we
move the sysreg access insns to before the NOCP patterns in the
following commit.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-3-peter.maydell@linaro.org
Commit: fa856736b6d0dabdcbe1b199ef2bb4fdec0f4911
https://github.com/qemu/qemu/commit/fa856736b6d0dabdcbe1b199ef2bb4fdec0f4911
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/m-nocp.decode
M target/arm/translate-a32.h
M target/arm/translate-m-nocp.c
M target/arm/translate-vfp.c
M target/arm/vfp.decode
Log Message:
-----------
target/arm: Don't NOCP fault for FPCXT_NS accesses
The M-profile architecture requires that accesses to FPCXT_NS when
there is no active FP state must not take a NOCP fault even if the
FPU is disabled. We were not implementing this correctly, because
in our decode we catch the NOCP faults early in m-nocp.decode.
Fix this bug by moving all the handling of M-profile FP system
register accesses from vfp.decode into m-nocp.decode and putting
it above the NOCP blocks. This provides the correct behaviour:
* for accesses other than FPCXT_NS the trans functions call
vfp_access_check(), which will check for FPU disabled and
raise a NOCP exception if necessary
* for FPCXT_NS we have the special case code that doesn't
call vfp_access_check()
* when these trans functions want to raise an UNDEF they return
false, so the decoder will fall through into the NOCP blocks.
This means that NOCP correctly takes precedence over UNDEF
for these insns. (This is a difference from the other insns
handled by m-nocp.decode, where UNDEF takes precedence and
which we implement by having those trans functions call
unallocated_encoding() in the appropriate places.)
[Note for backport to stable: this commit has a semantic dependency
on commit 9a486856e9173af, which was not marked as cc-stable because
we didn't know we'd need it for a for-stable bugfix.]
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-4-peter.maydell@linaro.org
Commit: e494cd0a1abce13a9a934c1cfdaaeabd389a77c7
https://github.com/qemu/qemu/commit/e494cd0a1abce13a9a934c1cfdaaeabd389a77c7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-m-nocp.c
Log Message:
-----------
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
A few subcases of VLDR/VSTR sysreg succeed but do not perform a
memory access:
* VSTR of VPR when unprivileged
* VLDR to VPR when unprivileged
* VLDR to FPCXT_NS when fpInactive
In these cases, even though we don't do the memory access we should
still update the base register and perform the stack limit check if
the insn's addressing mode specifies writeback. Our implementation
failed to do this, because we handle these side-effects inside the
memory_to_fp_sysreg() and fp_sysreg_to_memory() callback functions,
which are only called if there's something to load or store.
Fix this by adding an extra argument to the callbacks which is set to
true to actually perform the access and false to only do side effects
like writeback, and calling the callback with do_access = false
for the three cases listed above.
This produces slightly suboptimal code for the case of a write
to FPCXT_NS when the FPU is inactive and the insn didn't have
side effects (ie no writeback, or via VMSR), in which case we'll
generate a conditional branch over an unconditional branch.
But this doesn't seem to be important enough to merit requiring
the callback to report back whether it generated any code or not.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-5-peter.maydell@linaro.org
Commit: 95aceeeac9a37d05c106ba807867616496d5c90e
https://github.com/qemu/qemu/commit/95aceeeac9a37d05c106ba807867616496d5c90e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Factor FP context update code out into helper function
Factor the code in full_vfp_access_check() which updates the
ownership of the FP context and creates a new FP context
out into its own function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-6-peter.maydell@linaro.org
Commit: e8cedaf779c0c2b13e0cc1ca580beaf5a6562a73
https://github.com/qemu/qemu/commit/e8cedaf779c0c2b13e0cc1ca580beaf5a6562a73
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Split vfp_access_check() into A and M versions
vfp_access_check and its helper routine full_vfp_access_check() has
gradually grown and is now an awkward mix of A-profile only and
M-profile only pieces. Refactor it into an A-profile only and an
M-profile only version, taking advantage of the fact that now the
only direct call to full_vfp_access_check() is in A-profile-only
code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-7-peter.maydell@linaro.org
Commit: 88137f787f374ac4117877bcc8c8af97326a10bd
https://github.com/qemu/qemu/commit/88137f787f374ac4117877bcc8c8af97326a10bd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/translate-a32.h
M target/arm/translate-m-nocp.c
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
Instead of open-coding the "take NOCP exception if FPU disabled,
otherwise call gen_preserve_fp_state()" code in the accessors for
FPCXT_NS, add an argument to vfp_access_check_m() which tells it to
skip the gen_update_fp_context() call, so we can use it for the
FPCXT_NS case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-8-peter.maydell@linaro.org
Commit: 507b6a500c2f0f6cf6182aa69efac4c20eb3e97b
https://github.com/qemu/qemu/commit/507b6a500c2f0f6cf6182aa69efac4c20eb3e97b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
A target/arm/helper-mve.h
M target/arm/helper.h
M target/arm/internals.h
M target/arm/meson.build
M target/arm/mve.decode
A target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
Implement the forms of the MVE VLDR and VSTR insns which perform
non-widening loads of bytes, halfwords or words from memory into
vector elements of the same width (encodings T5, T6, T7).
(At the moment we know for MVE and M-profile in general that
vfp_access_check() can never return false, but we include the
conventional return-true-on-failure check for consistency
with non-M-profile translation code.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-2-peter.maydell@linaro.org
Commit: 2fc6b7510c6859478264b7402ba01dbee86b7e46
https://github.com/qemu/qemu/commit/2fc6b7510c6859478264b7402ba01dbee86b7e46
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
Implement the variants of MVE VLDR (encodings T1, T2) which perform
"widening" loads where bytes or halfwords are loaded from memory and
zero or sign-extended into halfword or word length vector elements,
and the narrowing MVE VSTR (encodings T1, T2) where bytes or
halfwords are stored from halfword or word elements.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-3-peter.maydell@linaro.org
Commit: 0f0f2bd54817ffad1ccb15dd0fb3adf2db1ec394
https://github.com/qemu/qemu/commit/0f0f2bd54817ffad1ccb15dd0fb3adf2db1ec394
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCLZ
Implement the MVE VCLZ insn (and the necessary machinery
for MVE 1-input vector ops).
Note that for non-load instructions predication is always performed
at a byte level granularity regardless of element size (R_ZLSJ),
and so the masking logic here differs from that used in the VLDR
and VSTR helpers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-4-peter.maydell@linaro.org
Commit: 6437f1f77c3bca329b6464e9357647f33d85e9ef
https://github.com/qemu/qemu/commit/6437f1f77c3bca329b6464e9357647f33d85e9ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCLS
Implement the MVE VCLS insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-5-peter.maydell@linaro.org
Commit: 249b5309c44831555b7fb6dab68d7a6f9f573882
https://github.com/qemu/qemu/commit/249b5309c44831555b7fb6dab68d7a6f9f573882
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VREV16, VREV32, VREV64
Implement the MVE instructions VREV16, VREV32 and VREV64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-6-peter.maydell@linaro.org
Commit: 8abd3c80b18757c54e9b270244ca351e407b6405
https://github.com/qemu/qemu/commit/8abd3c80b18757c54e9b270244ca351e407b6405
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMVN (register)
Implement the MVE VMVN(register) operation. Note that for
predication this operation is byte-by-byte.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-7-peter.maydell@linaro.org
Commit: 59c917733809c6ac7d08a10ec3cf23ae50130248
https://github.com/qemu/qemu/commit/59c917733809c6ac7d08a10ec3cf23ae50130248
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VABS
Implement the MVE VABS functions (both integer and floating point).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-8-peter.maydell@linaro.org
Commit: 399a8c766c0526b51cd180e1b1c776d6dc95bad8
https://github.com/qemu/qemu/commit/399a8c766c0526b51cd180e1b1c776d6dc95bad8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VNEG
Implement the MVE VNEG insn (both integer and floating point forms).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-9-peter.maydell@linaro.org
Commit: 614dd4f3ba2a025eae5235c3466ef6da191879f6
https://github.com/qemu/qemu/commit/614dd4f3ba2a025eae5235c3466ef6da191879f6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M include/tcg/tcg-op.h
M include/tcg/tcg.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
The Arm MVE VDUP implementation would like to be able to emit code to
duplicate a byte or halfword value into an i32. We have code to do
this already in tcg-op-gvec.c, so all we need to do is make the
functions global.
For consistency with other functions made available to the frontends:
* we rename to tcg_gen_dup_*
* we expose both the _i32 and _i64 forms
* we provide the #define for a _tl form
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210617121628.20116-10-peter.maydell@linaro.org
Commit: ab59362fca0c23fbd21daceb78d6b2966fbf9793
https://github.com/qemu/qemu/commit/ab59362fca0c23fbd21daceb78d6b2966fbf9793
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VDUP
Implement the MVE VDUP insn, which duplicates a value from
a general-purpose register into every lane of a vector
register (subject to predication).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-11-peter.maydell@linaro.org
Commit: 68245e442c9e5175d5e9d3a797dcab7eee800253
https://github.com/qemu/qemu/commit/68245e442c9e5175d5e9d3a797dcab7eee800253
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
Implement the MVE vector logical operations operating
on two registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-12-peter.maydell@linaro.org
Commit: 9333fe4dd39709ce9898750d517568e5c2fb2e32
https://github.com/qemu/qemu/commit/9333fe4dd39709ce9898750d517568e5c2fb2e32
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VADD, VSUB, VMUL
Implement the MVE VADD, VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-13-peter.maydell@linaro.org
Commit: ba62cc56e8a0aa84337c50766d499ba4199394df
https://github.com/qemu/qemu/commit/ba62cc56e8a0aa84337c50766d499ba4199394df
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMULH
Implement the MVE VMULH insn, which performs a vector
multiply and returns the high half of the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-14-peter.maydell@linaro.org
Commit: fca87b78f3d178518a38063498d477f5e10c5c22
https://github.com/qemu/qemu/commit/fca87b78f3d178518a38063498d477f5e10c5c22
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VRMULH
Implement the MVE VRMULH insn, which performs a rounding multiply
and then returns the high half.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-15-peter.maydell@linaro.org
Commit: cd367ff3919e020b50a10cf4955fc31042e73f24
https://github.com/qemu/qemu/commit/cd367ff3919e020b50a10cf4955fc31042e73f24
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMAX, VMIN
Implement the MVE VMAX and VMIN insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-16-peter.maydell@linaro.org
Commit: bc67aa8d561e6ebf93b724c9abf3a7a1f95839c9
https://github.com/qemu/qemu/commit/bc67aa8d561e6ebf93b724c9abf3a7a1f95839c9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VABD
Implement the MVE VABD insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-17-peter.maydell@linaro.org
Commit: abc48e310cc95f616ae65ccb167019eebf7e705b
https://github.com/qemu/qemu/commit/abc48e310cc95f616ae65ccb167019eebf7e705b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VHADD, VHSUB
Implement MVE VHADD and VHSUB insns, which perform an addition
or subtraction and then halve the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-18-peter.maydell@linaro.org
Commit: ac6ad1dca84e39038e149c7b91adf9642e89ca70
https://github.com/qemu/qemu/commit/ac6ad1dca84e39038e149c7b91adf9642e89ca70
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMULL
Implement the MVE VMULL insn, which multiplies two single
width integer elements to produce a double width result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-19-peter.maydell@linaro.org
Commit: 1d2386f70a0cb2ad9c5fab2cf1eedb80bb5b313d
https://github.com/qemu/qemu/commit/1d2386f70a0cb2ad9c5fab2cf1eedb80bb5b313d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE VMLALDAV
Implement the MVE VMLALDAV insn, which multiplies pairs of integer
elements, accumulating them into a 64-bit result in a pair of
general-purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-20-peter.maydell@linaro.org
Commit: 181cd97143629a304f75acf894ca79b26bf32378
https://github.com/qemu/qemu/commit/181cd97143629a304f75acf894ca79b26bf32378
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMLSLDAV
Implement the MVE insn VMLSLDAV, which multiplies source elements,
alternately adding and subtracting them, and accumulates into a
64-bit result in a pair of general purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-21-peter.maydell@linaro.org
Commit: 38548747335a0796ab1d636c8b5bcf5c248ce437
https://github.com/qemu/qemu/commit/38548747335a0796ab1d636c8b5bcf5c248ce437
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate
the results of a rounded multiply of pairs of elements into a 72-bit
accumulator, returning the top 64 bits in a pair of general purpose
registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-22-peter.maydell@linaro.org
Commit: e51896b3866ffb74df5aaa3b33c35e7113e5c6b9
https://github.com/qemu/qemu/commit/e51896b3866ffb74df5aaa3b33c35e7113e5c6b9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VADD (scalar)
Implement the scalar form of the MVE VADD insn. This takes the
scalar operand from a general purpose register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-23-peter.maydell@linaro.org
Commit: 91a358fdfb3b116a6ea72a38d5c217caad1d45b5
https://github.com/qemu/qemu/commit/91a358fdfb3b116a6ea72a38d5c217caad1d45b5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSUB, VMUL (scalar)
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-24-peter.maydell@linaro.org
Commit: 644f717c35ec29d53f6fc34523e096fbad6eeaf9
https://github.com/qemu/qemu/commit/644f717c35ec29d53f6fc34523e096fbad6eeaf9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VHADD, VHSUB (scalar)
Implement the scalar variants of the MVE VHADD and VHSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-25-peter.maydell@linaro.org
Commit: b050543b68308427792cc024fb2905b041ebc253
https://github.com/qemu/qemu/commit/b050543b68308427792cc024fb2905b041ebc253
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VBRSR
Implement the MVE VBRSR insn, which reverses a specified
number of bits in each element, setting the rest to zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-26-peter.maydell@linaro.org
Commit: 387debdb93d2635fb6d62bff38887d17ef4d8117
https://github.com/qemu/qemu/commit/387debdb93d2635fb6d62bff38887d17ef4d8117
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/mve.decode
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VPST
Implement the MVE VPST insn, which sets the predicate mask
fields in the VPR to the immediate value encoded in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-27-peter.maydell@linaro.org
Commit: 39f2ec8592dd3c823034dc4decc64c7e4cc42bfd
https://github.com/qemu/qemu/commit/39f2ec8592dd3c823034dc4decc64c7e4cc42bfd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating
addition of a scalar to each element. Note that individual bytes of
each result element are used or discarded according to the predicate
mask, but FPSCR.QC is only set if the predicate mask for the lowest
byte of the element is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-28-peter.maydell@linaro.org
Commit: 66c0576754b100606e041fef54e5b897417426c7
https://github.com/qemu/qemu/commit/66c0576754b100606e041fef54e5b897417426c7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply
elements by the scalar, double, possibly round, take the high half
and saturate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-29-peter.maydell@linaro.org
Commit: a88903537d73b1d9728e3d824920b4d0096f10bc
https://github.com/qemu/qemu/commit/a88903537d73b1d9728e3d824920b4d0096f10bc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMULL scalar
Implement the MVE VQDMULL scalar insn. This multiplies the top or
bottom half of each element by the scalar, doubles and saturates
to a double-width result.
Note that this encoding overlaps with VQADD and VQSUB; it uses
what in VQADD and VQSUB would be the 'size=0b11' encoding.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-30-peter.maydell@linaro.org
Commit: 380caf6c0762f43a9468aeebaf4ba7e1dd8edc9a
https://github.com/qemu/qemu/commit/380caf6c0762f43a9468aeebaf4ba7e1dd8edc9a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-31-peter.maydell@linaro.org
Commit: f741707bb36f7281ceccbdc0c44dcce61fbe1023
https://github.com/qemu/qemu/commit/f741707bb36f7281ceccbdc0c44dcce61fbe1023
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQADD, VQSUB (vector)
Implement the vector forms of the MVE VQADD and VQSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-32-peter.maydell@linaro.org
Commit: 483da6613937ea34fbf4b970668021dd76e46636
https://github.com/qemu/qemu/commit/483da6613937ea34fbf4b970668021dd76e46636
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQSHL (vector)
Implement the MVE VQSHL insn (encoding T4, which is the
vector-shift-by-vector version).
The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from
the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-33-peter.maydell@linaro.org
Commit: 9dc868c41d8c630f3c13040e2732b4df6d4739de
https://github.com/qemu/qemu/commit/9dc868c41d8c630f3c13040e2732b4df6d4739de
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQRSHL
Implement the MV VQRSHL (vector) insn. Again, the code to perform
the actual shifts is borrowed from neon_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-34-peter.maydell@linaro.org
Commit: 0372cad813193bab3fb88985129ac59c801ca065
https://github.com/qemu/qemu/commit/0372cad813193bab3fb88985129ac59c801ca065
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSHL insn
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-35-peter.maydell@linaro.org
Commit: bb002345ebfe09f6f96fc41043f93d2e286cd136
https://github.com/qemu/qemu/commit/bb002345ebfe09f6f96fc41043f93d2e286cd136
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VRSHL
Implement the MVE VRSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-36-peter.maydell@linaro.org
Commit: fd677f8055fa88d72f01eb9aeb1dd90606d85444
https://github.com/qemu/qemu/commit/fd677f8055fa88d72f01eb9aeb1dd90606d85444
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMLADH and VQRDMLADH
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply
elements, and then add pairs of products, double, possibly round,
saturate and return the high half of the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-37-peter.maydell@linaro.org
Commit: 92f117326af14d9bffc2ec99e0f112d33c0615ca
https://github.com/qemu/qemu/commit/92f117326af14d9bffc2ec99e0f112d33c0615ca
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are
like VQDMLADH and VQRDMLADH except that products are subtracted
rather than added.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-38-peter.maydell@linaro.org
Commit: 43364321f354b8722d5bab730052b625adc3a92c
https://github.com/qemu/qemu/commit/43364321f354b8722d5bab730052b625adc3a92c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VQDMULL (vector)
Implement the vector form of the MVE VQDMULL insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-39-peter.maydell@linaro.org
Commit: 1eb987a89d944515b05ccd8b913bee7fd0d547ae
https://github.com/qemu/qemu/commit/1eb987a89d944515b05ccd8b913bee7fd0d547ae
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VRHADD
Implement the MVE VRHADD insn, which performs a rounded halving
addition.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-40-peter.maydell@linaro.org
Commit: 89bc4c4f78c2435fdf8dc10b650cfe73c75f1f2c
https://github.com/qemu/qemu/commit/89bc4c4f78c2435fdf8dc10b650cfe73c75f1f2c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VADC, VSBC
Implement the MVE VADC and VSBC insns. These perform an
add-with-carry or subtract-with-carry of the 32-bit elements in each
lane of the input vectors, where the carry-out of each add is the
carry-in of the next. The initial carry input is either 1 or is from
FPSCR.C; the carry out at the end is written back to FPSCR.C.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-41-peter.maydell@linaro.org
Commit: 67ec113b119360092dee679ca0f5eca8ac60992c
https://github.com/qemu/qemu/commit/67ec113b119360092dee679ca0f5eca8ac60992c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCADD
Implement the MVE VCADD insn, which performs a complex add with
rotate. Note that the size=0b11 encoding is VSBC.
The architecture grants some leeway for the "destination and Vm
source overlap" case for the size MO_32 case, but we choose not to
make use of it, instead always calculating all 16 bytes worth of
results before setting the destination register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-42-peter.maydell@linaro.org
Commit: 8625693ac48f54e87f663736c0bbde7ea450f1f7
https://github.com/qemu/qemu/commit/8625693ac48f54e87f663736c0bbde7ea450f1f7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VHCADD
Implement the MVE VHCADD insn, which is similar to VCADD
but performs a halving step. This one overlaps with VADC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-43-peter.maydell@linaro.org
Commit: 6f060a636bf46869e43a28a0f426ddaea16314f9
https://github.com/qemu/qemu/commit/6f060a636bf46869e43a28a0f426ddaea16314f9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VADDV
Implement the MVE VADDV insn, which performs an addition
across vector lanes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-44-peter.maydell@linaro.org
Commit: 4f57ef959cf83cc780658c7e97ba5f737aa666f2
https://github.com/qemu/qemu/commit/4f57ef959cf83cc780658c7e97ba5f737aa666f2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M target/arm/translate-a32.h
M target/arm/translate-mve.c
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
In a CPU with MVE, the VMOV (vector lane to general-purpose register)
and VMOV (general-purpose register to vector lane) insns are not
predicated, but they are subject to beatwise execution if they
are not in an IT block.
Since our implementation always executes all 4 beats in one tick,
this means only that we need to handle PSR.ECI:
* we must do the usual check for bad ECI state
* we must advance ECI state if the insn succeeds
* if ECI says we should not be executing the beat corresponding
to the lane of the vector register being accessed then we
should skip performing the move
Note that if PSR.ECI is non-zero then we cannot be in an IT block.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-45-peter.maydell@linaro.org
Commit: 86f0d4c7290eb2b21ec3eb44956ec245441275db
https://github.com/qemu/qemu/commit/86f0d4c7290eb2b21ec3eb44956ec245441275db
Author: Peter Collingbourne <pcc@google.com>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Implement MTE3
MTE3 introduces an asymmetric tag checking mode, in which loads are
checked synchronously and stores are checked asynchronously. Add
support for it.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210616195614.11785-1-pcc@google.com
[PMM: Add line to emulation.rst]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 90a76c6316cfe6416fc33814a838fb3928f746ee
https://github.com/qemu/qemu/commit/90a76c6316cfe6416fc33814a838fb3928f746ee
Author: Alexandre Iooss <erdnaxe@crans.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M MAINTAINERS
A docs/system/arm/nrf.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs/system: arm: Add nRF boards description
This adds the target guide for BBC Micro:bit.
Information is taken from https://wiki.qemu.org/Features/MicroBit
and from hw/arm/nrf51_soc.c.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20210621075625.540471-1-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ecba223da6215d6f6ce2d343b70b2e9a19bfb90b
https://github.com/qemu/qemu/commit/ecba223da6215d6f6ce2d343b70b2e9a19bfb90b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-24 (Thu, 24 Jun 2021)
Changed paths:
M MAINTAINERS
A docs/system/arm/emulation.rst
A docs/system/arm/nrf.rst
M docs/system/target-arm.rst
A hw/acpi/ghes-stub.c
M hw/acpi/ghes.c
M hw/acpi/meson.build
M include/hw/acpi/ghes.h
M include/tcg/tcg-op.h
M include/tcg/tcg.h
M target/arm/cpu64.c
A target/arm/helper-mve.h
M target/arm/helper.h
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/m-nocp.decode
M target/arm/meson.build
M target/arm/mte_helper.c
M target/arm/mve.decode
A target/arm/mve_helper.c
M target/arm/translate-a32.h
M target/arm/translate-m-nocp.c
M target/arm/translate-mve.c
M target/arm/translate-vfp.c
M target/arm/translate.h
M target/arm/vfp.decode
M tcg/tcg-op-gvec.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210624'
into staging
target-arm queue:
* Don't require 'virt' board to be compiled in for ACPI GHES code
* docs: Document which architecture extensions we emulate
* Fix bugs in M-profile FPCXT_NS accesses
* First slice of MVE patches
* Implement MTE3
* docs/system: arm: Add nRF boards description
# gpg: Signature made Thu 24 Jun 2021 14:59:16 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210624: (57 commits)
docs/system: arm: Add nRF boards description
target/arm: Implement MTE3
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
target/arm: Implement MVE VADDV
target/arm: Implement MVE VHCADD
target/arm: Implement MVE VCADD
target/arm: Implement MVE VADC, VSBC
target/arm: Implement MVE VRHADD
target/arm: Implement MVE VQDMULL (vector)
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
target/arm: Implement MVE VQDMLADH and VQRDMLADH
target/arm: Implement MVE VRSHL
target/arm: Implement MVE VSHL insn
target/arm: Implement MVE VQRSHL
target/arm: Implement MVE VQSHL (vector)
target/arm: Implement MVE VQADD, VQSUB (vector)
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
target/arm: Implement MVE VQDMULL scalar
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
target/arm: Implement MVE VQADD and VQSUB
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d0ac9a61474c...ecba223da621