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[Qemu-commits] [qemu/qemu] a4fbbd: tcg: Change parameters for tcg_target
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] a4fbbd: tcg: Change parameters for tcg_target_const_match |
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Date: |
Sat, 05 Jun 2021 08:12:35 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a4fbbd779a29b912299bc2830f0157513080ddb7
https://github.com/qemu/qemu/commit/a4fbbd779a29b912299bc2830f0157513080ddb7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Change parameters for tcg_target_const_match
Change the return value to bool, because that's what is should
have been from the start. Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.
Change the value argument to int64_t. We will need the extra
width for 32-bit hosts wanting to match vector constants.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 000cf4777aadda69d14a6994ca0d195a36733cbd
https://github.com/qemu/qemu/commit/000cf4777aadda69d14a6994ca0d195a36733cbd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
A tcg/arm/tcg-target.opc.h
Log Message:
-----------
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6e49fad23f56f2618ddcbca78f0d4e1fc692ae9d
https://github.com/qemu/qemu/commit/6e49fad23f56f2618ddcbca78f0d4e1fc692ae9d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Implement tcg_out_ld/st for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2df2a8cf77e76370698164e3d361e07075d2a699
https://github.com/qemu/qemu/commit/2df2a8cf77e76370698164e3d361e07075d2a699
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Implement tcg_out_mov for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 213e8d84735f56e16d4485509ef48ccb6488d4a9
https://github.com/qemu/qemu/commit/213e8d84735f56e16d4485509ef48ccb6488d4a9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Implement tcg_out_dup*_vec
Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d74b86ed4ad452eb5069ca0c168c731a5c429127
https://github.com/qemu/qemu/commit/d74b86ed4ad452eb5069ca0c168c731a5c429127
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement minimal vector operations
Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7df44cf6e9e5726c5f9c56a398fc606566673007
https://github.com/qemu/qemu/commit/7df44cf6e9e5726c5f9c56a398fc606566673007
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement andc, orc, abs, neg, not vector operations
These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d4c4e9c51b91d413cf3020ce80ba4914186bfbb4
https://github.com/qemu/qemu/commit/d4c4e9c51b91d413cf3020ce80ba4914186bfbb4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_shi_vec
This consists of the three immediate shifts: shli, shri, sari.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 752b17693e7af43ba77cee59eb9a1ec6966b3ded
https://github.com/qemu/qemu/commit/752b17693e7af43ba77cee59eb9a1ec6966b3ded
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_mul_vec
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4fcd301707ccc656f27e3dc324cdbe20122a9740
https://github.com/qemu/qemu/commit/4fcd301707ccc656f27e3dc324cdbe20122a9740
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
This is saturating add and subtract, signed and unsigned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dbbeff77645242241fe2296b88a7b1d3b3614ffe
https://github.com/qemu/qemu/commit/dbbeff77645242241fe2296b88a7b1d3b3614ffe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
This is minimum and maximum, signed and unsigned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f2b46c7162f86b05bbc05f1728b1d2a0e6a9e457
https://github.com/qemu/qemu/commit/f2b46c7162f86b05bbc05f1728b1d2a0e6a9e457
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 31d366390cc4316e55362d40cfc52542d6eea5ab
https://github.com/qemu/qemu/commit/31d366390cc4316e55362d40cfc52542d6eea5ab
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.opc.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5047ae648b7f25d3cdb6ce4995c62aa7806abd7f
https://github.com/qemu/qemu/commit/5047ae648b7f25d3cdb6ce4995c62aa7806abd7f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.opc.h
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0006039e29b9e6118beab300146f7c4931f7a217
https://github.com/qemu/qemu/commit/0006039e29b9e6118beab300146f7c4931f7a217
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-04 (Fri, 04 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6f398e533f5e259b4f937f4aa9de970f7201d166
https://github.com/qemu/qemu/commit/6f398e533f5e259b4f937f4aa9de970f7201d166
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-05 (Sat, 05 Jun 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
A tcg/arm/tcg-target.opc.h
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' into
staging
Host vector support for arm neon.
# gpg: Signature made Fri 04 Jun 2021 19:56:59 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210604:
tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
tcg/arm: Implement TCG_TARGET_HAS_mul_vec
tcg/arm: Implement TCG_TARGET_HAS_shi_vec
tcg/arm: Implement andc, orc, abs, neg, not vector operations
tcg/arm: Implement minimal vector operations
tcg/arm: Implement tcg_out_dup*_vec
tcg/arm: Implement tcg_out_mov for vector types
tcg/arm: Implement tcg_out_ld/st for vector types
tcg/arm: Add host vector framework
tcg: Change parameters for tcg_target_const_match
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/908a87706ec6...6f398e533f5e