[Qemu-commits] [qemu/qemu] 7df6a1: target/arm: Add isar feature check fu

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[Qemu-commits] [qemu/qemu] 7df6a1: target/arm: Add isar feature check fu

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 7df6a1: target/arm: Add isar feature check functions for MVE
Date:	Thu, 03 Jun 2021 09:00:21 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 7df6a1ffdbdcaf98fa57747dc79216ac089e6215
      
https://github.com/qemu/qemu/commit/7df6a1ffdbdcaf98fa57747dc79216ac089e6215
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar feature check functions for MVE

Add the isar feature check functions we will need for v8.1M MVE:
 * a check for MVE present: this corresponds to the pseudocode's
   CheckDecodeFaults(ExtType_Mve)
 * a check for the optional floating-point part of MVE: this
   corresponds to CheckDecodeFaults(ExtType_MveFp)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-2-peter.maydell@linaro.org


  Commit: 69049bcf5114f7af379b4f3cccfb0b213b30f88a
      
https://github.com/qemu/qemu/commit/69049bcf5114f7af379b4f3cccfb0b213b30f88a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Update feature checks for insns which are "MVE or FP"

Some v8M instructions are present if either the floating point
extension or MVE is implemented.  Update our implementation of them
to check for MVE as well as for FP.

This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or
CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are
essentially the loads and stores, moves and sysreg accesses, except
for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent
patches because they need a refactor to provide a place to put the
new MVE check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-3-peter.maydell@linaro.org


  Commit: 70b305d4f0f0e024b6c1adeb0630be8491bbae6a
      
https://github.com/qemu/qemu/commit/70b305d4f0f0e024b6c1adeb0630be8491bbae6a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp

The do_vfp_2op_sp() and do_vfp_2op_dp() functions currently check
whether floating point is supported via the aa32_fpdp_v2 and
aa32_fpsp_v2 isar checks.  For v8.1M MVE support, the VMOV_reg trans
functions (but not any of the others) need to update this to also
allow the insn if MVE is implemented.  Move the check out of the do_
function and into its callsites (which are all implemented via the
DO_VFP_2OP macro), so we have a place to change the check for the
VMOV insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-4-peter.maydell@linaro.org


  Commit: 7e435b9ea645b370aa32364fa22f8e4cd9e7d9ec
      
https://github.com/qemu/qemu/commit/7e435b9ea645b370aa32364fa22f8e4cd9e7d9ec
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp

Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can
permit the insns if either FP or MVE are present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-5-peter.maydell@linaro.org


  Commit: 300137965dbacec02eb2e26b3c6763b491d1f1b2
      
https://github.com/qemu/qemu/commit/300137965dbacec02eb2e26b3c6763b491d1f1b2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Fix return values in fp_sysreg_checks()

The fp_sysreg_checks() function is supposed to be returning an
FPSysRegCheckResult, which is an enum with three possible values.
However, three places in the function "return false" (a hangover from
a previous iteration of the design where the function just returned a
bool).  Make these return FPSysRegCheckFailed instead (for no
functional change, since both false and FPSysRegCheckFailed are
zero).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-6-peter.maydell@linaro.org


  Commit: 7c3d47dab908ac1770726e68cf72e47bb5a9cbcb
      
https://github.com/qemu/qemu/commit/7c3d47dab908ac1770726e68cf72e47bb5a9cbcb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/machine.c
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Implement M-profile VPR register

If MVE is implemented for an M-profile CPU then it has a VPR
register, which tracks predication information.

Implement the read and write handling of this register, and
the migration of its state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-7-peter.maydell@linaro.org


  Commit: b26b5629c0be4a9539833de4189184a224590d14
      
https://github.com/qemu/qemu/commit/b26b5629c0be4a9539833de4189184a224590d14
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/machine.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Make FPSCR.LTPSIZE writable for MVE

The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.

Make the field writable when MVE is implemented.

We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-8-peter.maydell@linaro.org


  Commit: 7cda2149521f25b7caedd464f2e35104d9990315
      
https://github.com/qemu/qemu/commit/7cda2149521f25b7caedd464f2e35104d9990315
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/armv7m.h
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Allow board models to specify initial NS VTOR

Currently we allow board models to specify the initial value of the
Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M
object which is plumbed through to the CPU.  Allow board models to
also specify the initial value of the Non-secure VTOR via a similar
init-nsvtor property.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-10-peter.maydell@linaro.org


  Commit: f548f20176cb5f440693120f9bde911dd3639748
      
https://github.com/qemu/qemu/commit/f548f20176cb5f440693120f9bde911dd3639748
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M docs/system/arm/aspeed.rst
    M docs/system/arm/nuvoton.rst
    M docs/system/arm/sabrelite.rst
    M hw/arm/aspeed.c
    M hw/arm/mcimx6ul-evk.c
    M hw/arm/mcimx7d-sabre.c
    M hw/arm/npcm7xx_boards.c
    M hw/arm/sabrelite.c
    M hw/misc/npcm7xx_clk.c
    M include/hw/arm/allwinner-h3.h

  Log Message:
  -----------
  arm: Consistently use "Cortex-Axx", not "Cortex Axx"

The official punctuation for Arm CPU names uses a hyphen, like
"Cortex-A9". We mostly follow this, but in a few places usage
without the hyphen has crept in. Fix those so we consistently
use the same way of writing the CPU name.

This commit was created with:
  git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/'

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210527095152.10968-1-peter.maydell@linaro.org


  Commit: 269a7e97865cb863c9ca19e5f2e6a40ac9eddf82
      
https://github.com/qemu/qemu/commit/269a7e97865cb863c9ca19e5f2e6a40ac9eddf82
  Author: Damien Goutte-Gattat <dgouttegattat@incenp.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M docs/conf.py

  Log Message:
  -----------
  docs: Fix installation of man pages with Sphinx 4.x

The 4.x branch of Sphinx introduces a breaking change, as generated man
pages are now written to subdirectories corresponding to the manual
section they belong to. This results in `make install` erroring out when
attempting to install the man pages, because they are not where it
expects to find them.

This patch restores the behavior of Sphinx 3.x regarding man pages.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/256
Signed-off-by: Damien Goutte-Gattat <dgouttegattat@incenp.org>
Message-id: 20210503161422.15028-1-dgouttegattat@incenp.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0711a634355a68cd83966872e387402a8b4b048a
      
https://github.com/qemu/qemu/commit/0711a634355a68cd83966872e387402a8b4b048a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Mark LDS{MIN,MAX} as signed operations

The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must
be signed, so that the inputs are properly extended.
Zero extend the result afterward, as needed.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210602020720.47679-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6e0c60a2be30c333b06d3558a62b0f177199cbfb
      
https://github.com/qemu/qemu/commit/6e0c60a2be30c333b06d3558a62b0f177199cbfb
  Author: Jamie Iles <jamie@nuviainc.com>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: fix missing exception class

The DAIF and PAC checks used raise_exception_ra to raise an exception
and unwind CPU state but raise_exception_ra is currently designed for
handling data aborts as the syndrome is partially precomputed and
encoded in the TB and then merged in merge_syn_data_abort when handling
the data abort.  Using raise_exception_ra for DAIF and PAC checks
results in an empty syndrome being retrieved from data[2] in
restore_state_to_opc and setting ESR to 0.  This manifested as:

  kvm [571]: Unknown exception class: esr: 0x000000 –
  Unknown/Uncategorized

when launching a KVM guest when the host qemu used a CPU supporting
EL2+pointer authentication and enabling pointer authentication in the
guest.

Rework raise_exception_ra such that the state is restored before raising
the exception so that the exception is not clobbered by
restore_state_to_opc.

Fixes: 0d43e1a2d29a ("target/arm: Add PAuth helpers")
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: added comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 154acaba0ea9675f175118787b9ca44cbbbc23b7
      
https://github.com/qemu/qemu/commit/154acaba0ea9675f175118787b9ca44cbbbc23b7
  Author: Jamie Iles <jamie@nuviainc.com>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: fold do_raise_exception into raise_exception

Now that there are no other users of do_raise_exception, fold it into
raise_exception.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5bf100c3200bc74b5d7b4e430c3b23e60caf1605
      
https://github.com/qemu/qemu/commit/5bf100c3200bc74b5d7b4e430c3b23e60caf1605
  Author: Jamie Iles <jamie@nuviainc.com>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: use raise_exception_ra for MTE check failure

Now that raise_exception_ra restores the state before raising the
exception we can use restore_exception_ra to perform the state restore +
exception raising without clobbering the syndrome.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: Keep the one line of the comment that is still relevant]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9d75d45c0b88c87ac25ee4c65e724447834c1d3b
      
https://github.com/qemu/qemu/commit/9d75d45c0b88c87ac25ee4c65e724447834c1d3b
  Author: Jamie Iles <jamie@nuviainc.com>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/m_helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: use raise_exception_ra for stack limit exception

The sequence cpu_restore_state() + raise_exception() is equivalent to
raise_exception_ra(), so use that instead.  (In this case we never
cared about the syndrome value, because M-profile doesn't use the
syndrome; the old code was just written unnecessarily awkwardly.)

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: Retain edited version of comment; rewrite commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c0b9e8a48906f25acce17c9b60447bb7fd9d5cd2
      
https://github.com/qemu/qemu/commit/c0b9e8a48906f25acce17c9b60447bb7fd9d5cd2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16

Note that the SVE BFLOAT16 support does not require SVE2,
it is an independent extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc5200ee4583cb9110ee7bda71a65890d787882e
      
https://github.com/qemu/qemu/commit/fc5200ee4583cb9110ee7bda71a65890d787882e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Unify unallocated path in disas_fp_1src

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3a98ac40fa9fca85bb37f4281e872b7519e733c5
      
https://github.com/qemu/qemu/commit/3a98ac40fa9fca85bb37f4281e872b7519e733c5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate-vfp.c
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement scalar float32 to bfloat16 conversion

This is the 64-bit BFCVT and the 32-bit VCVT{B,T}.BF16.F32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d29b17ca3eac79ab77c76ec8285698b0c57d04b2
      
https://github.com/qemu/qemu/commit/d29b17ca3eac79ab77c76ec8285698b0c57d04b2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/helper.h
    M target/arm/neon-dp.decode
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement vector float32 to bfloat16 conversion

This is BFCVT{N,T} for both AArch64 AdvSIMD and SVE,
and VCVT.BF16.F32 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 60c8f7265d7eb51dfb38ea6701d10cbe2d7c7a64
      
https://github.com/qemu/qemu/commit/60c8f7265d7eb51dfb38ea6701d10cbe2d7c7a64
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M fpu/softfloat-parts.c.inc
    M include/fpu/softfloat-types.h

  Log Message:
  -----------
  softfpu: Add float_round_to_odd_inf

For Arm BFDOT and BFMMLA, we need a version of round-to-odd
that overflows to infinity, instead of the max normal number.

Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cb8657f7f9fcc2ebe8dfb1cbc9e572670d2af568
      
https://github.com/qemu/qemu/commit/cb8657f7f9fcc2ebe8dfb1cbc9e572670d2af568
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement bfloat16 dot product (vector)

This is BFDOT for both AArch64 AdvSIMD and SVE,
and VDOT.BF16 for AArch32 NEON.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 839144784b613998edf7a7277ed2ed2015b0b4d7
      
https://github.com/qemu/qemu/commit/839144784b613998edf7a7277ed2ed2015b0b4d7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement bfloat16 dot product (indexed)

This is BFDOT for both AArch64 AdvSIMD and SVE,
and VDOT.BF16 for AArch32 NEON.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1
      
https://github.com/qemu/qemu/commit/81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement bfloat16 matrix multiply accumulate

This is BFMMLA for both AArch64 AdvSIMD and SVE,
and VMMLA.BF16 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5693887f2e97335362d945c778f2bbddd4e9d1bb
      
https://github.com/qemu/qemu/commit/5693887f2e97335362d945c778f2bbddd4e9d1bb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement bfloat widening fma (vector)

This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE,
and VFMA{B,T}.BF16 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 458d0ab6830f9bcd76af9df4d1d4db8ab646fcef
      
https://github.com/qemu/qemu/commit/458d0ab6830f9bcd76af9df4d1d4db8ab646fcef
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement bfloat widening fma (indexed)

This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE,
and VFMA{B,T}.BF16 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6c47a9053cc2255ec444e0f964abd496fdce6433
      
https://github.com/qemu/qemu/commit/6c47a9053cc2255ec444e0f964abd496fdce6433
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/aarch64: Enable hwcap bits for bfloat16

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3c93dfa42c394fdd55684f2fbf24cf2f39b97d47
      
https://github.com/qemu/qemu/commit/3c93dfa42c394fdd55684f2fbf24cf2f39b97d47
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Enable BFloat16 extensions

Disable BF16 again for !have_neon and !have_vfp during realize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d57bc3c1098f1614db1c5763f3672fe01d768972
      
https://github.com/qemu/qemu/commit/d57bc3c1098f1614db1c5763f3672fe01d768972
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M MAINTAINERS
    A accel/hvf/hvf-all.c
    A accel/hvf/meson.build
    M accel/meson.build
    A include/sysemu/hvf_int.h
    M target/i386/hvf/hvf.c

  Log Message:
  -----------
  hvf: Move assert_hvf_ok() into common directory

Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.

This patch moves assert_hvf_ok() and introduces generic build infrastructure.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-2-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 39a3445012e44b01f6a7e7b29cf7477ef2a656eb
      
https://github.com/qemu/qemu/commit/39a3445012e44b01f6a7e7b29cf7477ef2a656eb
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    A accel/hvf/hvf-accel-ops.c
    A accel/hvf/hvf-accel-ops.h
    M accel/hvf/meson.build
    R target/i386/hvf/hvf-accel-ops.c
    R target/i386/hvf/hvf-accel-ops.h
    M target/i386/hvf/meson.build
    M target/i386/hvf/x86hvf.c

  Log Message:
  -----------
  hvf: Move vcpu thread functions into common directory

Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.

This patch moves the vCPU thread loop over.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-3-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 358e7505b2795d3df505661da7be9dc81eaa91d9
      
https://github.com/qemu/qemu/commit/358e7505b2795d3df505661da7be9dc81eaa91d9
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M include/sysemu/hvf_int.h
    M target/i386/hvf/hvf-i386.h
    M target/i386/hvf/hvf.c
    M target/i386/hvf/x86hvf.h

  Log Message:
  -----------
  hvf: Move cpu functions into common directory

Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.

This patch moves CPU and memory operations over. While at it, make sure
the code is consumable on non-i386 systems.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-4-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 861457ce73bc9e0e56d866b5c06e2c745fe53448
      
https://github.com/qemu/qemu/commit/861457ce73bc9e0e56d866b5c06e2c745fe53448
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M include/sysemu/hvf_int.h
    M target/i386/hvf/hvf-i386.h

  Log Message:
  -----------
  hvf: Move hvf internal definitions into common header

Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.

This patch moves a few internal struct and constant defines over.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-5-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3f965ef4e013d37391f5bb94c243d4a4b1825b1f
      
https://github.com/qemu/qemu/commit/3f965ef4e013d37391f5bb94c243d4a4b1825b1f
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M include/sysemu/hvf_int.h

  Log Message:
  -----------
  hvf: Make hvf_set_phys_mem() static

The hvf_set_phys_mem() function is only called within the same file.
Make it static.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-6-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6e19f86a80746270ab2ab6fe4828c680d982fa72
      
https://github.com/qemu/qemu/commit/6e19f86a80746270ab2ab6fe4828c680d982fa72
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c

  Log Message:
  -----------
  hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t

The ARM version of Hypervisor.framework no longer defines these two
types, so let's just revert to standard ones.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-7-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cfe58455f3b79810375cb4ef560071c1ecff6dea
      
https://github.com/qemu/qemu/commit/cfe58455f3b79810375cb4ef560071c1ecff6dea
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/hvf/hvf-accel-ops.h
    M include/sysemu/hvf_int.h
    M target/i386/hvf/hvf.c

  Log Message:
  -----------
  hvf: Split out common code on vcpu init and destroy

Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.

This patch splits the vcpu init and destroy functions into a generic and
an architecture specific portion. This also allows us to move the generic
functions into the generic hvf code, removing exported functions.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-8-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 65c725b5204f22987950b4368ab7db67bcc87f54
      
https://github.com/qemu/qemu/commit/65c725b5204f22987950b4368ab7db67bcc87f54
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/hvf/hvf-accel-ops.h
    M target/i386/hvf/x86hvf.c

  Log Message:
  -----------
  hvf: Use cpu_synchronize_state()

There is no reason to call the hvf specific hvf_cpu_synchronize_state()
when we can just use the generic cpu_synchronize_state() instead. This
allows us to have less dependency on internal function definitions and
allows us to make hvf_cpu_synchronize_state() static.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-9-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 36464fafcb34c1599b6cd22e409a3de600974944
      
https://github.com/qemu/qemu/commit/36464fafcb34c1599b6cd22e409a3de600974944
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/hvf/hvf-accel-ops.h

  Log Message:
  -----------
  hvf: Make synchronize functions static

The hvf accel synchronize functions are only used as input for local
callback functions, so we can make them static.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-10-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d662ede2b1eb033883b7c96866e84e8b54524ccb
      
https://github.com/qemu/qemu/commit/d662ede2b1eb033883b7c96866e84e8b54524ccb
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    R accel/hvf/hvf-accel-ops.h
    M include/sysemu/hvf_int.h
    M target/i386/hvf/hvf.c

  Log Message:
  -----------
  hvf: Remove hvf-accel-ops.h

We can move the definition of hvf_vcpu_exec() into our internal
hvf header, obsoleting the need for hvf-accel-ops.h.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-11-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b533450e74500dd67f0aa49775809ea33bc465b7
      
https://github.com/qemu/qemu/commit/b533450e74500dd67f0aa49775809ea33bc465b7
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M include/hw/core/cpu.h
    M include/sysemu/hvf_int.h
    M target/i386/hvf/hvf.c
    M target/i386/hvf/vmx.h
    M target/i386/hvf/x86.c
    M target/i386/hvf/x86_descr.c
    M target/i386/hvf/x86_emu.c
    M target/i386/hvf/x86_mmu.c
    M target/i386/hvf/x86_task.c
    M target/i386/hvf/x86hvf.c

  Log Message:
  -----------
  hvf: Introduce hvf vcpu struct

We will need more than a single field for hvf going forward. To keep
the global vcpu struct uncluttered, let's allocate a special hvf vcpu
struct, similar to how hax does it.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-12-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bac969ef30e8a8b73acbeb6d68abff6f68b2056c
      
https://github.com/qemu/qemu/commit/bac969ef30e8a8b73acbeb6d68abff6f68b2056c
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M target/i386/hvf/x86hvf.c

  Log Message:
  -----------
  hvf: Simplify post reset/init/loadvm hooks

The hooks we have that call us after reset, init and loadvm really all
just want to say "The reference of all register state is in the QEMU
vcpu struct, please push it".

We already have a working pushing mechanism though called cpu->vcpu_dirty,
so we can just reuse that for all of the above, syncing state properly the
next time we actually execute a vCPU.

This fixes PSCI resets on ARM, as they modify CPU state even after the
post init call has completed, but before we execute the vCPU again.

To also make the scheme work for x86, we have to make sure we don't
move stale eflags into our env when the vcpu state is dirty.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210519202253.76782-13-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3c65e439b2724cc70af31a87447a0c7292babac5
      
https://github.com/qemu/qemu/commit/3c65e439b2724cc70af31a87447a0c7292babac5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/qtest/bios-tables-test.c

  Log Message:
  -----------
  tests/qtest/bios-tables-test: Check for dup2() failure

Coverity notes that we don't check for dup2() failing.  Add some
assertions so that if it does ever happen we get some indication.
(This is similar to how we handle other "don't expect this syscall to
fail" checks in this test code.)

Fixes: Coverity CID 1432346
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20210525134458.6675-2-peter.maydell@linaro.org


  Commit: 380822edb3252962001a47c02facb7c7e977dc7d
      
https://github.com/qemu/qemu/commit/380822edb3252962001a47c02facb7c7e977dc7d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/qtest/e1000e-test.c

  Log Message:
  -----------
  tests/qtest/e1000e-test: Check qemu_recv() succeeded

The e1000e_send_verify() test calls qemu_recv() but doesn't
check that the call succeeded, which annoys Coverity. Add
an explicit test check for the length of the data.

(This is a test check, not a "we assume this syscall always
succeeds", so we use g_assert_cmpint() rather than g_assert().)

Fixes: Coverity CID 1432324
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20210525134458.6675-3-peter.maydell@linaro.org


  Commit: 2c398ee5e3a4b8db995ec4b211f28a1119bf10ca
      
https://github.com/qemu/qemu/commit/2c398ee5e3a4b8db995ec4b211f28a1119bf10ca
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/qtest/hd-geo-test.c

  Log Message:
  -----------
  tests/qtest/hd-geo-test: Fix checks on mkstemp() return value

Coverity notices that the checks against mkstemp() failing in
create_qcow2_with_mbr() are wrong: mkstemp returns -1 on failure but
the check is just "g_assert(fd)".  Fix to use "g_assert(fd >= 0)",
matching the correct check in create_test_img().

Fixes: Coverity CID 1432274
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20210525134458.6675-4-peter.maydell@linaro.org


  Commit: 909e4a0826cde069555d90a9797590c5988d9b7e
      
https://github.com/qemu/qemu/commit/909e4a0826cde069555d90a9797590c5988d9b7e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/qtest/pflash-cfi02-test.c

  Log Message:
  -----------
  tests/qtest/pflash-cfi02-test: Avoid potential integer overflow

Coverity points out that we calculate a 64-bit value using 32-bit
arithmetic; add the cast to force the multiply to be done as 64-bits.
(The overflow will never happen with the current test data.)

Fixes: Coverity CID 1432320
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20210525134458.6675-5-peter.maydell@linaro.org


  Commit: d2304612b525e6a0d9df93717c0d1e5321b6b845
      
https://github.com/qemu/qemu/commit/d2304612b525e6a0d9df93717c0d1e5321b6b845
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/qtest/tpm-tests.c

  Log Message:
  -----------
  tests/qtest/tpm-tests: Remove unnecessary NULL checks

Coverity points out that in tpm_test_swtpm_migration_test() we
assume that src_tpm_addr and dst_tpm_addr are non-NULL (we
pass them to tpm_util_migration_start_qemu() which will
unconditionally dereference them) but then later explicitly
check them for NULL. Remove the pointless checks.

Fixes: Coverity CID 1432367, 1432359

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20210525134458.6675-6-peter.maydell@linaro.org


  Commit: 1c861885894d840235954060050d240259f5340b
      
https://github.com/qemu/qemu/commit/1c861885894d840235954060050d240259f5340b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M tests/unit/test-vmstate.c

  Log Message:
  -----------
  tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed

Coverity complains that we don't check for failures from dup()
and mkstemp(); add asserts that these syscalls succeeded.

Fixes: Coverity CID 1432516, 1432574
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210525134458.6675-7-peter.maydell@linaro.org


  Commit: 453d9c61dd5681159051c6e4d07e7b2633de2e70
      
https://github.com/qemu/qemu/commit/453d9c61dd5681159051c6e4d07e7b2633de2e70
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-03 (Thu, 03 Jun 2021)

  Changed paths:
    M MAINTAINERS
    A accel/hvf/hvf-accel-ops.c
    A accel/hvf/hvf-all.c
    A accel/hvf/meson.build
    M accel/meson.build
    M docs/conf.py
    M docs/system/arm/aspeed.rst
    M docs/system/arm/nuvoton.rst
    M docs/system/arm/sabrelite.rst
    M fpu/softfloat-parts.c.inc
    M hw/arm/armv7m.c
    M hw/arm/aspeed.c
    M hw/arm/mcimx6ul-evk.c
    M hw/arm/mcimx7d-sabre.c
    M hw/arm/npcm7xx_boards.c
    M hw/arm/sabrelite.c
    M hw/misc/npcm7xx_clk.c
    M include/fpu/softfloat-types.h
    M include/hw/arm/allwinner-h3.h
    M include/hw/arm/armv7m.h
    M include/hw/core/cpu.h
    A include/sysemu/hvf_int.h
    M linux-user/elfload.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper-sve.h
    M target/arm/helper.h
    M target/arm/m_helper.c
    M target/arm/machine.c
    M target/arm/mte_helper.c
    M target/arm/neon-dp.decode
    M target/arm/neon-shared.decode
    M target/arm/op_helper.c
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/translate-vfp.c
    M target/arm/vec_helper.c
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c
    R target/i386/hvf/hvf-accel-ops.c
    R target/i386/hvf/hvf-accel-ops.h
    M target/i386/hvf/hvf-i386.h
    M target/i386/hvf/hvf.c
    M target/i386/hvf/meson.build
    M target/i386/hvf/vmx.h
    M target/i386/hvf/x86.c
    M target/i386/hvf/x86_descr.c
    M target/i386/hvf/x86_emu.c
    M target/i386/hvf/x86_mmu.c
    M target/i386/hvf/x86_task.c
    M target/i386/hvf/x86hvf.c
    M target/i386/hvf/x86hvf.h
    M tests/qtest/bios-tables-test.c
    M tests/qtest/e1000e-test.c
    M tests/qtest/hd-geo-test.c
    M tests/qtest/pflash-cfi02-test.c
    M tests/qtest/tpm-tests.c
    M tests/unit/test-vmstate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210603' 
into staging

target-arm queue:
 * Some not-yet-enabled preliminaries for M-profile MVE support
 * Consistently use "Cortex-Axx", not "Cortex Axx" in docs, comments
 * docs: Fix installation of man pages with Sphinx 4.x
 * Mark LDS{MIN,MAX} as signed operations
 * Fix missing syndrome value for DAIF and PAC check exceptions
 * Implement BFloat16 extensions
 * Refactoring of hvf accelerator code in preparation for aarch64 support
 * Fix some coverity nits in test code

# gpg: Signature made Thu 03 Jun 2021 16:58:02 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210603: (45 commits)
  tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed
  tests/qtest/tpm-tests: Remove unnecessary NULL checks
  tests/qtest/pflash-cfi02-test: Avoid potential integer overflow
  tests/qtest/hd-geo-test: Fix checks on mkstemp() return value
  tests/qtest/e1000e-test: Check qemu_recv() succeeded
  tests/qtest/bios-tables-test: Check for dup2() failure
  hvf: Simplify post reset/init/loadvm hooks
  hvf: Introduce hvf vcpu struct
  hvf: Remove hvf-accel-ops.h
  hvf: Make synchronize functions static
  hvf: Use cpu_synchronize_state()
  hvf: Split out common code on vcpu init and destroy
  hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t
  hvf: Make hvf_set_phys_mem() static
  hvf: Move hvf internal definitions into common header
  hvf: Move cpu functions into common directory
  hvf: Move vcpu thread functions into common directory
  hvf: Move assert_hvf_ok() into common directory
  target/arm: Enable BFloat16 extensions
  linux-user/aarch64: Enable hwcap bits for bfloat16
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a97978bcc2d1...453d9c61dd56
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