Re: geda/lepton schematics

[Felix Salfelder]

On Mon, Mar 28, 2022 at 12:05:58PM +0200, karl@aspodata.se wrote:
>  every sym file is a module
>  every sch file is a module

gEDA uses one file for one schematic, and one file for one symbol.
Perhaps it makes sense to stick with it.

Verilog does not allow top level components, but the standard has a
notion of "main". It looks C inspired, maybe it is.

A schematic file could be stored in a verilog file that contains a
single "main" module, and the main module contains the components (port
values represent connectivity) and maybe text or graphics.

Similar approach might work for symbols but you no longer need them to
see the circuit.

>  you only need to find out the implicit nets within the sch file
>   not for the whole system

Not necessarily, if you just want to store the schematic, which should
be the first step.

>From there, you can think about flattening. Perhaps gnucap-geda does it
"the wrong way", but it will adapt.

cheers
felix