Re: geda/lepton schematics

[karl]

Felix:
...
> Lepton people should store connectivity in their schematic files. Then,
> their schematic files would be much closer to structural Verilog (to an
> extent that they could just consider to use Verilog instead).
...

I don't think that that is possible in a design with subsheets (why is 
hierarchical so hard to spell, I need a better name for it).

If you only have nets and symbols, the full connectivity is contained
in just one file and could just as well be listed there.

But if you have a subsheet, say a dc-dc converter with a source symbol
that says
 pin  label
 1    Vin
 2    GND
 3    Vout
then that could refer to anything from a resistor+zener, 7805 to some
complex nonisolated switched power supply. So you can only get the 
full connectivity by scanning the full stack, since the user might
deside to change to another subsheet.

That is the beuty and complexity of subsheets.
The outside world only needs to know that this is a dc/dc conv., and
I can swap the implementation depending on spec.

Regards,
/Karl Hammar