Re: geda/lepton schematics

[Felix Salfelder]

On Fri, Mar 25, 2022 at 09:14:30PM +0100, karl@aspodata.se wrote:
> It seems it consists of a few non-connected branches.

Oh, if forgot. I once put some of it here [1] as standalone repos,
probably more of what you'd expect.

> > Connections in gEDA schematics are implicit, and port positions are
> > needed to infer them. For this, the symbol database is required. The gEDA
> > library has been used to look up the symbols.
> 
> Don't you get the connections from the netlist ?

Which netlist?

> > When I try to configure gnucap-geda, I get
> > [..]
> > checking for libgeda >= 20100214... no
> > configure: error: gEDA package not found
> 
>  ./bootstrap works fine here, but
>  ./configure gives:
> checking dynamic linker characteristics... (cached) GNU/Linux ld.so
> checking how to hardcode library paths into programs... immediate
> ./configure: 16616: GC_CPPFLAGS+= -I/usr/local/include/gnucap: not found

I have a line (17649) in my configure that seems related. but it reads
GC_CPPFLAGS+=" $(gnucap-conf$_program_suffix --cppflags)",
note the quotation marks. It is the same as line 35 in configure.ac.
Not sure what is going on. My configure starts with
# Generated by GNU Autoconf 2.71 for gnucap-geda 0.0.3-rc5.
And I am on commit 312cd3c3c26.

> checking l_dispatcher.h usability... no

This is just a consequence of the above if guess.

> I think something is not good enough with guile-2.0, and that the
> libgeda package should be updated for a newer guile version.
> Bug your distro about that.

I can try. Do you have a working libgeda-dev? which distro?

> Wouldn't it be best if geda/lepton supported gnucap instead of the 
> other way around ?

Not sure what you mean. One idea behind Gnucap is to read/write netlists
& schematics (and support models) from other projects.

It might be better if gEDA supported Verilog (and explicit connections)
to store schematics. Gnucap already reads structural Verilog for quite a
while.

> > Next steps are more technical, and I am happy to talk about it. Now
> > there is a translator "Qucs schematics" <=> "Verilog schematics", and I
> > can think of a way to do gEDA schematics properly...
> 
> Yes ?

I think it is desirable to eventually have Qucs <=> Verilog <=> gGEDA
roundtrips for schematics. (It doesn't have to be Verilog, but some
suitable standardised format for circuit models.)

cheers
felix

[1] https://codeberg.org/gnucap