Re: Implicit rule for linking multiple object files

[Paul Smith]

On Thu, 2022-08-11 at 01:58 +0800, ljh wrote:
> I have three c source files: x.c, y.c, z.c and I name x as the target
> on left. Can I put x.o in the prerequisites on the right too? Are
> they the same, with or without x.o in the prerequisites on the right?
>    
>     x: y.o z.o x.o  # with x.o

It is correct to do this.

These two rules do not behave exactly the same:

  x: y.o z.o

versus

  x: y.o z.o x.o

(you can see the difference for yourself by running "make" both ways)
but the result of both of these will give you the same working program.

> Is it correct for me to use patsubst function to include all object
> files?
>     x: $(patsubst %.c,%.o,$(wildcard *.c))

This is fine too.

> In my test the rule with patsubst works on most cases. But if my code
> uses C++20 modules, I need to omit x.o if I want to omit the recipe:
>     x: y.o z.o  # without x.o and recipe
> 
> if I include x.o, I can't omit the recipe:
>     ` x: y.o z.o x.o ` # with x.o 
>     `    $ (CXX) $ (LDFLAGS) $^ $(LDLIBS) -o $@ ` # with recipe

I don't know why you keep referring to C++20 modules.  Make doesn't
know anything about C++20 modules, it doesn't even know what version of
C++ the compiler is building with.  It barely even knows that there is
such a thing as C++: all it knows is "some source files end in .cpp or
.cc or .cxx and those should be built with a recipe that uses variables
CXX and CXXFLAGS".

In any event, I see no reason why an implicit rule without a recipe and
with x.o as a prerequisite wouldn't work.  In fact, it works fine for
me:

  $ ls
  Makefile  x.c  y.c  z.c

  $ cat Makefile
  x: $(patsubst %.c,%.o,$(wildcard *.c))

  $ make
  cc    -c -o x.o x.c
  cc    -c -o y.o y.c
  cc    -c -o z.o z.c
  cc   x.o y.o z.o   -o x