diff -ruN ../uisp-20020626/src/DAPA.C ./src/DAPA.C --- ../uisp-20020626/src/DAPA.C 2002-06-13 22:17:24.000000000 +0900 +++ ./src/DAPA.C 2002-08-18 15:02:11.000000000 +0900 @@ -280,6 +280,15 @@ #define MAXI_DIN PARPORT_STATUS_ACK #define MAXI_DOUT 0x01 +/* Xilinx JTAG download cable + RESET=TMS, SCK=TCK, MISO=TDO, MOSI=TDI +*/ +#define XIL_DOUT 0x01 /* D0: TDI */ +#define XIL_SCK 0x02 /* D1: TCK */ +#define XIL_RESET 0x04 /* D2: TMS */ +#define XIL_ENA 0x08 /* D3: ENABLE# */ +#define XIL_DIN PARPORT_STATUS_SELECT /* SLCT: TDO */ + /* Default value for minimum SCK high/low time in microseconds. */ #ifndef SCK_DELAY #define SCK_DELAY 5 @@ -445,6 +454,11 @@ ParportWriteData(); break; + case PAT_XIL: + if (b) par_data |= XIL_RESET; else par_data &= ~XIL_RESET; + ParportWriteData(); + break; + #ifdef TIOCMGET case PAT_DASA: SerialReadCtrl(); @@ -509,6 +523,11 @@ ParportWriteData(); break; + case PAT_XIL: + if (b) par_data |= XIL_SCK; else par_data &= ~XIL_SCK; + ParportWriteData(); + break; + #ifdef TIOCMGET case PAT_DASA: SerialReadCtrl(); @@ -613,6 +632,21 @@ } break; + case PAT_XIL: + if (b) { + ParportSetDir(0); + par_data &= ~XIL_ENA; + ParportWriteData(); + } else { + par_data |= XIL_ENA; + ParportWriteData(); + if (!no_ps2_hack) { + SckDelay(); + ParportSetDir(1); + } + } + break; + case PAT_DASA: case PAT_DASA2: break; @@ -638,6 +672,7 @@ case PAT_FBPRG: case PAT_DT006: case PAT_MAXI: + case PAT_XIL: case PAT_DASA: case PAT_DASA2: /* no separate enable for SCK nad MOSI */ @@ -711,6 +746,11 @@ ParportWriteData(); break; + case PAT_XIL: + if (b) par_data |= XIL_DOUT; else par_data &= ~XIL_DOUT; + ParportWriteData(); + break; + #ifdef TIOCMGET case PAT_DASA: ioctl(ppdev_fd, b ? TIOCSBRK : TIOCCBRK, 0); @@ -744,6 +784,10 @@ ParportReadStatus(); b = (par_status & PARPORT_STATUS_ACK); break; + case PAT_XIL: + ParportReadStatus(); + b = (par_status & PARPORT_STATUS_SELECT); + break; case PAT_DASA: case PAT_DASA2: #ifdef TIOCMGET @@ -801,6 +845,11 @@ par_data = 0xFF; break; + case PAT_XIL: + par_ctrl = 0; + par_data = 0xFF & ~(XIL_ENA | XIL_SCK | XIL_RESET); + break; + case PAT_DASA: case PAT_DASA2: break; @@ -894,6 +943,8 @@ pa_type = PAT_DT006; else if (val && strcmp(val, "maxi") == 0) pa_type = PAT_MAXI; + else if (val && strcmp(val, "xil") == 0) + pa_type = PAT_XIL; else if (val && strcmp(val, "dasa") == 0) pa_type = PAT_DASA; else if (val && strcmp(val, "dasa2") == 0) diff -ruN ../uisp-20020626/src/DAPA.h ./src/DAPA.h --- ../uisp-20020626/src/DAPA.h 2002-05-26 02:59:46.000000000 +0900 +++ ./src/DAPA.h 2002-08-18 14:38:45.000000000 +0900 @@ -44,7 +44,7 @@ class TDAPA { public: enum TPaType{ PAT_DAPA, PAT_STK200, PAT_ABB, PAT_AVRISP, PAT_BSD, - PAT_FBPRG, PAT_DT006, PAT_MAXI, + PAT_FBPRG, PAT_DT006, PAT_MAXI, PAT_XIL, PAT_DASA, PAT_DASA2 }; private: diff -ruN ../uisp-20020626/src/Main.C ./src/Main.C --- ../uisp-20020626/src/Main.C 2002-06-03 15:36:39.000000000 +0900 +++ ./src/Main.C 2002-08-18 15:30:09.000000000 +0900 @@ -85,7 +85,7 @@ " pavr http://avr.jpk.co.nz/pavr/pavr.html\n" " stk500 Atmel STK500\n" #ifndef NO_DAPA -" -dprog=dapa|stk200|abb|avrisp|bsd|fbprg|dt006|maxi|dasa|dasa2\n" +" -dprog=dapa|stk200|abb|avrisp|bsd|fbprg|dt006|maxi|xil|dasa|dasa2\n" " Programmer type:\n" " dapa Direct AVR Parallel Access\n" " stk200 Parallel Starter Kit STK200, STK300\n" @@ -95,6 +95,7 @@ " fbprg http://ln.com.ua/~real/avreal/adapters.html (parallel)\n" " dt006 http://www.dontronics.com/dt006.html (parallel)\n" " maxi Investment Technologies Maxi (parallel)\n" +" xil Xilinx HW-JTAG-PC Cable (parallel)\n" " dasa serial (RESET=RTS SCK=DTR MOSI=TXD MISO=CTS)\n" " dasa2 serial (RESET=!TXD SCK=RTS MOSI=DTR MISO=CTS)\n" "\n"