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[Tinycc-devel] Targeted Extensions on RISC-V64

From: Ziyao
Subject: [Tinycc-devel] Targeted Extensions on RISC-V64
Date: Tue, 28 Mar 2023 23:06:53 +0800

Hi list,

I am trying to make RISC-V 64 support more complete and noted that
there seems to be no 'c' extension support ('c' stands for "compressed",
which is similar to Thumb on ARM). I compiled a simple function which
simply returns 0, and got a object file containing 4-byte
instructions only.

0000000000000000 <foo>:
   0:   ff010113                addi    sp,sp,-16
   4:   00113423                sd      ra,8(sp)
   8:   00813023                sd      s0,0(sp)
   c:   01010413                addi    s0,sp,16
  10:   00000013                nop
  14:   0000051b                sext.w  a0,zero
  18:   00813083                ld      ra,8(sp)
  1c:   00013403                ld      s0,0(sp)
  20:   01010113                addi    sp,sp,16
  24:   00008067                ret

My question is: what combination of extensions does riscv64-tcc target?
For doubles, instruction fld is used, so I guess 'd' extension must be
included. A common used combination is rv64gc, is it what the original
author of RISC-V 64 backend has intended to support?


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