I spent a while trying to decipher riscv-gen, and it's actually not that bad. Very much inline with the cryptic TinyCC (ok, bit of a jab, but it's not that bad). It currently only supports RV64, vs the chip I'll be using supports RV32-IMC. Conveniently, most of the instructions implemented in riscv-gen are the 32-bit instructions, only a handful of RV64 instructions, which shouldn't be too difficult to avoid.
Is anyone else working in this area? Has anyone expressed any possibility at adding a few more comments to the riscv-gen code? Are there any landmines I may run into? How eager would people be to add a -m32 flag for RISC-V?
Charles