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Re: [Tinycc-devel] Huge swings in cache performance

From: grischka
Subject: Re: [Tinycc-devel] Huge swings in cache performance
Date: Sat, 07 Jan 2017 12:15:13 +0100
User-agent: Thunderbird (Windows/20090812)

David Mertens wrote:
Hello everyone,

I just pushed a commit that sets up 512-byte alignment for x86-64
architectures. It only uses 512 bytes for x86-64; for all others it sticks
with the default of 16 bytes.

L1/L2 cache line size is 64 bytes on x86-like processors, no matter
whether run in 32 or 64 bit mode.

However to make it work reliably the memory from malloc needs to be
aligned as well, like so:

    offset = 0, mem = (addr_t)ptr;
+    mem += -(int)mem & SECTION_ALIGNMENT;

and the possibly additional amount needs to be requested in advance:

    if (0 == mem)
-        return offset;
+        return offset + SECTION_ALIGNMENT;

I ran the tests on my BeagleBone Black with
the original alignment and saw no performance issues,

Obviously ARM don't automatically clear the instruction cache which is
why we have the explicit __clear_cache() call for ARM further down in

I am not sure if this quite follows the project practices. I define
SECTION_ALIGNMENT just prior to the function tcc_relocate_ex. If anybody
can think of a better place to put it, to keep useful things in one place,
please move it.

SECTION_ALIGNMENT seems too general as a name.  tccelf.c is full of
section_alignments of various kinds.  I'd suggest something prefixed
with RUN_xxxx  to indicate that it's used only in that specific place.

I would appreciate if anybody who had slowdowns could test again with this
latest commit. Also, do we have any other architectures with benchmarks
that might suggest different alignments for those?




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