Re: [Qemu-trivial] [PATCH v2] misc: don't use hwaddr as a type in trace events

[Philippe Mathieu-Daudé]

On 03/06/2018 10:43 AM, Daniel P. Berrangé wrote:
> Use types that are defined by QEMU in trace events caused build failures
> for the UST trace backend:
> 
>   In file included from trace-ust-all.c:13:0:
>   trace-ust-all.h:11844:206: error: unknown type name ‘hwaddr’
> 
> It only knows about C built-in types, and any types that are pulled in
> from includs of qemu-common.h and lttng/tracepoint.h. This does not
> include the 'hwaddr' type, so replace it with a uint64_t which is what
> exec/hwaddr.h defines 'hwaddr' as. This fixes the build failure
> introduced by
> 
>   commit 9eb8040c2d2b38e1a40bb6129b1b668fa178fcab
>   Author: Peter Maydell <address@hidden>
>   Date:   Fri Mar 2 10:45:39 2018 +0000
> 
>     hw/misc/tz-ppc: Model TrustZone peripheral protection controller
> 
> Signed-off-by: Daniel P. Berrangé <address@hidden>

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

> ---
>  hw/misc/trace-events | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index eb5ffcc0a8..562d9ed005 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -92,8 +92,8 @@ tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d"
>  tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d"
>  tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d"
>  tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d"
> -tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: 
> port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked"
> -tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: 
> port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked"
> +tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: 
> port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked"
> +tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ 
> PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked"
>  
>  # hw/misc/iotkit-secctl.c
>  iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit 
> SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u"
>