[Qemu-trivial] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Luc MICHEL]

This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor instruction
to the cortex-r5. As stated in the TRM, this instruction invalidates all the
data cache. This trivial patch implements it as NOP as cache operations are not
implemented in QEMU.

The documentation is here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html

Tested using this minimal program:
 .global _start
 
 .section .text
 _start:
   mcr p15, 0, r1, c15, c5, 0
 
 idle:
   wfi
   b idle

Before implementation:
 IN: 
 0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}

 Taking exception 1 [Undefined Instruction]
 ...from EL1 to EL1
 ...with ESR 0x0/0x2000000

After implementation:
 IN: 
 0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}
 0x00008004:  e320f003      wfi

Luc MICHEL (1):
  target/arm: add data cache invalidation cp15 instruction to cortex-r5

 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.12.2