Re: [Qemu-stable] [PATCH 4/6] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half

[Laurent Desnogues]

On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<address@hidden> wrote:
> We were using the wrong flush-to-zero bit for the non-half input.
>
> Fixes: 46d33d1e3c9
> Cc: address@hidden (3.0.1)
> Reported-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>

Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>

Laurent

> ---
>  target/arm/translate-sve.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 05ba0518c8..fe7aebdc19 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, 
> int pg,
>
>  static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
>  {
> -    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
> +    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
>  }
>
>  static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> @@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz 
> *a, uint32_t insn)
>
>  static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
>  {
> -    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
> +    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
>  }
>
>  static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> --
> 2.17.1
>