Re: [Qemu-stable] [PATCH 07/11] target/arm: Fix offset for LD1R instructions

[Laurent Desnogues]

On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson
<address@hidden> wrote:
> The immediate should be scaled by the size of the memory reference,
> not the size of the elements into which it is loaded.
>
> Cc: address@hidden (3.0.1)
> Reported-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>

Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>

Laurent

> ---
>  target/arm/translate-sve.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 9e63b5f8e5..f635822a61 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -4819,6 +4819,7 @@ static bool trans_LD1R_zpri(DisasContext *s, 
> arg_rpri_load *a, uint32_t insn)
>      unsigned vsz = vec_full_reg_size(s);
>      unsigned psz = pred_full_reg_size(s);
>      unsigned esz = dtype_esz[a->dtype];
> +    unsigned msz = dtype_msz(a->dtype);
>      TCGLabel *over = gen_new_label();
>      TCGv_i64 temp;
>
> @@ -4842,7 +4843,7 @@ static bool trans_LD1R_zpri(DisasContext *s, 
> arg_rpri_load *a, uint32_t insn)
>
>      /* Load the data.  */
>      temp = tcg_temp_new_i64();
> -    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
> +    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
>      tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
>                          s->be_data | dtype_mop[a->dtype]);
>
> --
> 2.17.1
>