[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs
From: |
Jim Shu |
Subject: |
[RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs |
Date: |
Wed, 12 Jun 2024 16:14:03 +0800 |
RISC-V WorldGuard will add 5-bit world_id (WID) to the each memory
transaction on the bus. The wgChecker in front of RAM or peripherals
MMIO could do the access control based on the WID. It is similar to ARM
TrustZone NS bit, but the WID is 5-bit.
The common implementation of WID is AXI4 AxUSER signal.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
include/exec/memattrs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..d00f3c5500 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -52,6 +52,11 @@ typedef struct MemTxAttrs {
unsigned int memory:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+
+ /*
+ * RISC-V WorldGuard: the 5-bit WID of memory access.
+ */
+ uint8_t world_id;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
--
2.17.1
- [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs, (continued)
- [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs, Jim Shu, 2024/06/12
- [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU, Jim Shu, 2024/06/12
- [RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers, Jim Shu, 2024/06/12
- [RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate, Jim Shu, 2024/06/12
- [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support, Jim Shu, 2024/06/12
- [RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks, Jim Shu, 2024/06/12
- [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs, Jim Shu, 2024/06/12
- [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension, Jim Shu, 2024/06/12
- [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions, Jim Shu, 2024/06/12
- [RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker, Jim Shu, 2024/06/12
- [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs,
Jim Shu <=
- [RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior, Jim Shu, 2024/06/12