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[PATCH v6 05/13] target/s390x: vxeh2: vector convert short/32b
From: |
David Hildenbrand |
Subject: |
[PATCH v6 05/13] target/s390x: vxeh2: vector convert short/32b |
Date: |
Thu, 28 Apr 2022 11:47:00 +0200 |
From: David Miller <dmiller423@gmail.com>
Signed-off-by: David Miller <dmiller423@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 4 +++
target/s390x/tcg/translate_vx.c.inc | 44 ++++++++++++++++++++++++++---
target/s390x/tcg/vec_fpu_helper.c | 31 ++++++++++++++++++++
3 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 69f69cf718..7cbcbd7f0b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -275,6 +275,10 @@ DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void,
ptr, cptr, cptr, env, i32
DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_5(gvec_vfche128_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdg32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdlg32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcgd32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vclgd32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
diff --git a/target/s390x/tcg/translate_vx.c.inc
b/target/s390x/tcg/translate_vx.c.inc
index b829ce0c7c..be9407d1ed 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -2720,23 +2720,59 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps
*o)
switch (s->fields.op2) {
case 0xc3:
- if (fpf == FPF_LONG) {
+ switch (fpf) {
+ case FPF_LONG:
fn = gen_helper_gvec_vcdg64;
+ break;
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
+ fn = gen_helper_gvec_vcdg32;
+ }
+ break;
+ default:
+ break;
}
break;
case 0xc1:
- if (fpf == FPF_LONG) {
+ switch (fpf) {
+ case FPF_LONG:
fn = gen_helper_gvec_vcdlg64;
+ break;
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
+ fn = gen_helper_gvec_vcdlg32;
+ }
+ break;
+ default:
+ break;
}
break;
case 0xc2:
- if (fpf == FPF_LONG) {
+ switch (fpf) {
+ case FPF_LONG:
fn = gen_helper_gvec_vcgd64;
+ break;
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
+ fn = gen_helper_gvec_vcgd32;
+ }
+ break;
+ default:
+ break;
}
break;
case 0xc0:
- if (fpf == FPF_LONG) {
+ switch (fpf) {
+ case FPF_LONG:
fn = gen_helper_gvec_vclgd64;
+ break;
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
+ fn = gen_helper_gvec_vclgd32;
+ }
+ break;
+ default:
+ break;
}
break;
case 0xc7:
diff --git a/target/s390x/tcg/vec_fpu_helper.c
b/target/s390x/tcg/vec_fpu_helper.c
index aa2cc8e4a6..2a618a1093 100644
--- a/target/s390x/tcg/vec_fpu_helper.c
+++ b/target/s390x/tcg/vec_fpu_helper.c
@@ -175,6 +175,30 @@ static void vop128_2(S390Vector *v1, const S390Vector *v2,
CPUS390XState *env,
*v1 = tmp;
}
+static float32 vcdg32(float32 a, float_status *s)
+{
+ return int32_to_float32(a, s);
+}
+
+static float32 vcdlg32(float32 a, float_status *s)
+{
+ return uint32_to_float32(a, s);
+}
+
+static float32 vcgd32(float32 a, float_status *s)
+{
+ const float32 tmp = float32_to_int32(a, s);
+
+ return float32_is_any_nan(a) ? INT32_MIN : tmp;
+}
+
+static float32 vclgd32(float32 a, float_status *s)
+{
+ const float32 tmp = float32_to_uint32(a, s);
+
+ return float32_is_any_nan(a) ? 0 : tmp;
+}
+
static float64 vcdg64(float64 a, float_status *s)
{
return int64_to_float64(a, s);
@@ -210,6 +234,9 @@ void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2,
CPUS390XState *env, \
vop##BITS##_2(v1, v2, env, se, XxC, erm, FN, GETPC());
\
}
+#define DEF_GVEC_VOP2_32(NAME)
\
+DEF_GVEC_VOP2_FN(NAME, NAME##32, 32)
+
#define DEF_GVEC_VOP2_64(NAME)
\
DEF_GVEC_VOP2_FN(NAME, NAME##64, 64)
@@ -218,6 +245,10 @@ DEF_GVEC_VOP2_FN(NAME, float32_##OP, 32)
\
DEF_GVEC_VOP2_FN(NAME, float64_##OP, 64)
\
DEF_GVEC_VOP2_FN(NAME, float128_##OP, 128)
+DEF_GVEC_VOP2_32(vcdg)
+DEF_GVEC_VOP2_32(vcdlg)
+DEF_GVEC_VOP2_32(vcgd)
+DEF_GVEC_VOP2_32(vclgd)
DEF_GVEC_VOP2_64(vcdg)
DEF_GVEC_VOP2_64(vcdlg)
DEF_GVEC_VOP2_64(vcgd)
--
2.35.1
- [PATCH v6 00/13] s390x/tcg: Implement Vector-Enhancements Facility 2, David Hildenbrand, 2022/04/28
- [PATCH v6 04/13] tcg: Implement tcg_gen_{h,w}swap_{i32,i64}, David Hildenbrand, 2022/04/28
- [PATCH v6 07/13] target/s390x: vxeh2: Update for changes to vector shifts, David Hildenbrand, 2022/04/28
- [PATCH v6 02/13] s390x/cpu_models: drop "msa5" from the TCG "max" model, David Hildenbrand, 2022/04/28
- [PATCH v6 01/13] target/s390x: Fix writeback to v1 in helper_vstl, David Hildenbrand, 2022/04/28
- [PATCH v6 05/13] target/s390x: vxeh2: vector convert short/32b,
David Hildenbrand <=
- [PATCH v6 06/13] target/s390x: vxeh2: vector string search, David Hildenbrand, 2022/04/28
- [PATCH v6 03/13] s390x/cpu_models: make "max" match the unmodified "qemu" CPU model under TCG, David Hildenbrand, 2022/04/28
- [PATCH v6 12/13] target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model, David Hildenbrand, 2022/04/28
- [PATCH v6 08/13] target/s390x: vxeh2: vector shift double by bit, David Hildenbrand, 2022/04/28
- [PATCH v6 09/13] target/s390x: vxeh2: vector {load, store} elements reversed, David Hildenbrand, 2022/04/28
- [PATCH v6 10/13] target/s390x: vxeh2: vector {load, store} byte reversed elements, David Hildenbrand, 2022/04/28
- [PATCH v6 11/13] target/s390x: vxeh2: vector {load, store} byte reversed element, David Hildenbrand, 2022/04/28
- [PATCH v6 13/13] tests/tcg/s390x: Tests for Vector Enhancements Facility 2, David Hildenbrand, 2022/04/28