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[qemu-s390x] [PULL 4/7] s390x/tcg: Rework MMU selection for instruction
From: |
Cornelia Huck |
Subject: |
[qemu-s390x] [PULL 4/7] s390x/tcg: Rework MMU selection for instruction fetches |
Date: |
Thu, 22 Aug 2019 15:58:36 +0200 |
From: David Hildenbrand <address@hidden>
Instructions are always fetched from primary address space, except when
in home address mode. Perform the selection directly in cpu_mmu_index().
get_mem_index() is only used to perform data access, instructions are
fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true).
We don't care about restricting the access permissions of the TLB
entries anymore, as we no longer enter PRIMARY entries into the
SECONDARY MMU. Cleanup related code a bit.
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
target/s390x/cpu.h | 7 +++++++
target/s390x/mmu_helper.c | 38 +++++++++++++++-----------------------
2 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 3d9de25f7ce3..79202c098096 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool
ifetch)
return MMU_REAL_IDX;
}
+ if (ifetch) {
+ if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
+ return MMU_HOME_IDX;
+ }
+ return MMU_PRIMARY_IDX;
+ }
+
switch (env->psw.mask & PSW_MASK_ASC) {
case PSW_ASC_PRIMARY:
return MMU_PRIMARY_IDX;
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index 6cf74502ef1e..40b6c1fc36a9 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -350,8 +350,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr,
int rw, uint64_t asc,
{
static S390SKeysState *ss;
static S390SKeysClass *skeyclass;
- int r = -1;
+ uint64_t asce;
uint8_t key;
+ int r;
if (unlikely(!ss)) {
ss = s390_get_skeys_device();
@@ -381,36 +382,21 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr,
int rw, uint64_t asc,
if (!(env->psw.mask & PSW_MASK_DAT)) {
*raddr = vaddr;
- r = 0;
- goto out;
+ goto nodat;
}
switch (asc) {
case PSW_ASC_PRIMARY:
PTE_DPRINTF("%s: asc=primary\n", __func__);
- r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
- rw, exc);
+ asce = env->cregs[1];
break;
case PSW_ASC_HOME:
PTE_DPRINTF("%s: asc=home\n", __func__);
- r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
- rw, exc);
+ asce = env->cregs[13];
break;
case PSW_ASC_SECONDARY:
PTE_DPRINTF("%s: asc=secondary\n", __func__);
- /*
- * Instruction: Primary
- * Data: Secondary
- */
- if (rw == MMU_INST_FETCH) {
- r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
- raddr, flags, rw, exc);
- *flags &= ~(PAGE_READ | PAGE_WRITE);
- } else {
- r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY,
env->cregs[7],
- raddr, flags, rw, exc);
- *flags &= ~(PAGE_EXEC);
- }
+ asce = env->cregs[7];
break;
case PSW_ASC_ACCREG:
default:
@@ -418,11 +404,17 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr,
int rw, uint64_t asc,
break;
}
- out:
+ /* perform the DAT translation */
+ r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc);
+ if (r) {
+ return r;
+ }
+
+nodat:
/* Convert real address -> absolute address */
*raddr = mmu_real2abs(env, *raddr);
- if (r == 0 && *raddr < ram_size) {
+ if (*raddr < ram_size) {
r = skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
if (r) {
trace_get_skeys_nonzero(r);
@@ -444,7 +436,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr,
int rw, uint64_t asc,
}
}
- return r;
+ return 0;
}
/**
--
2.20.1
- [qemu-s390x] [PULL 0/7] First batch of s390x changes for 4.2, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PATCH for-4.1?] compat: disable edid on virtio-gpu base device, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 1/7] s390x/tcg: Fix VERIM with 32/64 bit elements, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 2/7] s390x/mmu: Trace the right value if setting/getting the storage key fails, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 3/7] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug(), Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 4/7] s390x/tcg: Rework MMU selection for instruction fetches,
Cornelia Huck <=
- [qemu-s390x] [PULL 5/7] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 6/7] s390x/mmu: Better storage key reference and change bit handling, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 7/7] s390x/mmu: Factor out storage key handling, Cornelia Huck, 2019/08/22
- Re: [qemu-s390x] [PULL 0/7] First batch of s390x changes for 4.2, Peter Maydell, 2019/08/23