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Re: [qemu-s390x] [PATCH v3 4/6] s390x/tcg: Flush the TLB of all CPUs on
From: |
Alex Bennée |
Subject: |
Re: [qemu-s390x] [PATCH v3 4/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE |
Date: |
Mon, 19 Aug 2019 12:06:19 +0100 |
User-agent: |
mu4e 1.3.4; emacs 27.0.50 |
David Hildenbrand <address@hidden> writes:
> Whenever we modify a storage key, we should flush the TLBs of all CPUs,
> so the MMU fault handling code can properly consider the changed storage
> key (to e.g., properly set the reference and change bit on the next
> accesses).
>
> These functions are barely used in modern Linux guests, so the performance
> implications are neglectable for now.
>
> This is a preparation for better reference and change bit handling for
> TCG, which will require more MMU changes.
>
> Reviewed-by: Cornelia Huck <address@hidden>
> Signed-off-by: David Hildenbrand <address@hidden>
Acked-by: Alex Bennée <address@hidden>
> ---
> target/s390x/mem_helper.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index 29d9eaa5b7..91ba2e03d9 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -1815,6 +1815,11 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1,
> uint64_t r2)
>
> key = (uint8_t) r1;
> skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
> + /*
> + * As we can only flush by virtual address and not all the entries
> + * that point to a physical address we have to flush the whole TLB.
> + */
> + tlb_flush_all_cpus_synced(env_cpu(env));
> }
>
> /* reset reference bit extended */
> @@ -1843,6 +1848,11 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
> if (skeyclass->set_skeys(ss, r2 / TARGET_PAGE_SIZE, 1, &key)) {
> return 0;
> }
> + /*
> + * As we can only flush by virtual address and not all the entries
> + * that point to a physical address we have to flush the whole TLB.
> + */
> + tlb_flush_all_cpus_synced(env_cpu(env));
>
> /*
> * cc
--
Alex Bennée
- [qemu-s390x] [PATCH v3 0/6] s390x/mmu: Storage key reference and change bit handling, David Hildenbrand, 2019/08/16
- [qemu-s390x] [PATCH v3 1/6] s390x/mmu: Trace the right value if setting/getting the storage key fails, David Hildenbrand, 2019/08/16
- [qemu-s390x] [PATCH v3 2/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug(), David Hildenbrand, 2019/08/16
- [qemu-s390x] [PATCH v3 3/6] s390x/tcg: Rework MMU selection for instruction fetches, David Hildenbrand, 2019/08/16
- [qemu-s390x] [PATCH v3 4/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE, David Hildenbrand, 2019/08/16
- Re: [qemu-s390x] [PATCH v3 4/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE,
Alex Bennée <=
- [qemu-s390x] [PATCH v3 5/6] s390x/mmu: Better storage key reference and change bit handling, David Hildenbrand, 2019/08/16
- [qemu-s390x] [PATCH v3 6/6] s390x/mmu: Factor out storage key handling, David Hildenbrand, 2019/08/16
- Re: [qemu-s390x] [PATCH v3 0/6] s390x/mmu: Storage key reference and change bit handling, Cornelia Huck, 2019/08/19
- Re: [qemu-s390x] [PATCH v3 0/6] s390x/mmu: Storage key reference and change bit handling, Cornelia Huck, 2019/08/19