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[qemu-s390x] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_excep
From: |
David Hildenbrand |
Subject: |
[qemu-s390x] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception() |
Date: |
Mon, 3 Jun 2019 11:06:15 +0200 |
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are stored at loca-
tions 144-146. The VXC is also placed in the DXC
field of the floating-point-control (FPC) register if bit
45 of control register 0 is one. When bit 45 of control
register 0 is zero and bit 46 of control register 0 is
one, the DXC field of the FPC register and the con-
tents of storage at location 147 are unpredictable.
Signed-off-by: David Hildenbrand <address@hidden>
---
target/s390x/cpu.h | 1 +
target/s390x/excp_helper.c | 15 +++++++++++++++
target/s390x/tcg_s390x.h | 2 ++
3 files changed, 18 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 317a1377e6..4fc08a2c88 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -215,6 +215,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#define PGM_SPECIAL_OP 0x0013
#define PGM_OPERAND 0x0015
#define PGM_TRACE_TABLE 0x0016
+#define PGM_VECTOR_PROCESSING 0x001b
#define PGM_SPACE_SWITCH 0x001c
#define PGM_HFP_SQRT 0x001d
#define PGM_PC_TRANS_SPEC 0x001f
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 85223d00c0..f21bcf79ae 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -62,6 +62,21 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState
*env, uint32_t dxc,
tcg_s390_program_interrupt(env, PGM_DATA, ILEN_AUTO, ra);
}
+void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra)
+{
+ g_assert(vxc <= 0xff);
+#if !defined(CONFIG_USER_ONLY)
+ /* Always store the VXC into the lowcore, without AFP it is undefined */
+ stl_phys(CPU(s390_env_get_cpu(env))->as,
+ env->psa + offsetof(LowCore, data_exc_code), vxc);
+#endif
+
+ /* Always store the VXC into the FPC, without AFP it is undefined */
+ env->fpc = deposit32(env->fpc, 8, 8, vxc);
+ tcg_s390_program_interrupt(env, PGM_VECTOR_PROCESSING, ILEN_AUTO, ra);
+}
+
void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
{
tcg_s390_data_exception(env, dxc, GETPC());
diff --git a/target/s390x/tcg_s390x.h b/target/s390x/tcg_s390x.h
index ab2c4ba703..2813f9d48e 100644
--- a/target/s390x/tcg_s390x.h
+++ b/target/s390x/tcg_s390x.h
@@ -18,5 +18,7 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState
*env, uint32_t code,
int ilen, uintptr_t ra);
void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
uintptr_t ra);
+void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra);
#endif /* TCG_S390X_H */
--
2.21.0
- [qemu-s390x] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception(),
David Hildenbrand <=
- [qemu-s390x] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask(), David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT, David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL), David Hildenbrand, 2019/06/03
- [qemu-s390x] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT, David Hildenbrand, 2019/06/03