Re: [qemu-s390x] [Qemu-devel] [PATCH v1 01/33] s390x/tcg: Define vector instruction formats

[Richard Henderson]

On 2/26/19 3:38 AM, David Hildenbrand wrote:
> These are the new instruction formats related to vector instructions as
> up to the z14 (a.k.a. latest PoP).
> 
> As v2 appeares (like x2 in VRX) with d2/b2 in VRV, we have to assign it a
> higher field number to avoid collisions.
> 
> Properly take care of the MSB (to be able to address 32 registers) for
> each vector register field stored in the RXB field (Bit 36 - 30  for all
> vector instructions). As we have 32 bit vector registers and the
> "v" fields are only 4 bit in size, the 5th bit is stored in the RXB.
> We use a new type to indicate that the MSB has to be fetched from the
> RXB.
> 
> Signed-off-by: David Hildenbrand <address@hidden>
> ---
>  target/s390x/insn-format.def | 25 +++++++++++++++++++++++
>  target/s390x/translate.c     | 39 +++++++++++++++++++++++++++++++++++-
>  2 files changed, 63 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <address@hidden>


r~