Re: [PATCH v3 0/4] Several sstc extension fixes

[Alistair Francis]

On Tue, May 20, 2025 at 12:36 AM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
>     timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> (3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
>     which should update the timer and IRQ pending bits.
>
> Changed in v3:
> - Rebase to riscv-to-apply.next
>
> Changed in v2:
> - Remove duplicated code in riscv_timer_stce_changed() function
> - Add sstc spec description in the commit log
>
> Jim Shu (4):
>   target/riscv: Add the checking into stimecmp write function.
>   hw/intc: riscv_aclint: Fix mtime write for sstc extension
>   target/riscv: Fix VSTIP bit in sstc extension.
>   target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/intc/riscv_aclint.c     |  5 +++
>  target/riscv/csr.c         | 55 +++++++++++++++++++++++++++++++-
>  target/riscv/time_helper.c | 65 ++++++++++++++++++++++++++++++++++++--
>  target/riscv/time_helper.h |  1 +
>  4 files changed, 123 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>
>