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qemu-riscv (date)
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Last Modified: Wed Apr 30 2025 20:34:03 -0400
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April 30, 2025
Re: [PATCH v2 0/9] hw/riscv/virt.c: memmap usage cleanup
,
Alistair Francis
,
20:34
Re: [PATCH v2 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Alistair Francis
,
20:14
Re: [PATCH v2 8/9] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
,
Alistair Francis
,
20:13
Re: [PATCH v2 7/9] hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
,
Alistair Francis
,
20:12
Re: [PATCH v2 6/9] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
,
Alistair Francis
,
20:11
Re: [PATCH v2 5/9] hw/riscv/virt.c: use s->memmap in create_fdt() path
,
Alistair Francis
,
20:09
Re: [PATCH v2 4/9] hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
,
Alistair Francis
,
20:03
Re: [PATCH v2 3/9] hw/riscv/virt.c: use s->memmap in virt_machine_done()
,
Alistair Francis
,
20:03
Re: [PATCH v2 2/9] hw/riscv/virt.c: remove trivial virt_memmap references
,
Alistair Francis
,
20:00
Re: [PATCH] target/riscv: Fix fcvt.s.bf16 NaN box checking
,
Alistair Francis
,
19:58
Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc
,
Alistair Francis
,
18:45
Re: [PATCH qemu v2 1/2] accel/tcg: Fixed cross-page overflow for 32 bit guest
,
Richard Henderson
,
15:38
Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint
,
Joel Stanley
,
07:36
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Joel Stanley
,
07:28
[PATCH] target/riscv: Fix fcvt.s.bf16 NaN box checking
,
Anton Blanchard
,
04:22
April 29, 2025
Re: [RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Nicholas Piggin
,
20:07
Re: [PATCH 00/13] hw/riscv/virt: device tree reg cleanups
,
Alistair Francis
,
19:46
Re: [PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie
,
Daniel Henrique Barboza
,
13:25
Re: [PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu
,
Daniel Henrique Barboza
,
13:24
Re: [PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc
,
Daniel Henrique Barboza
,
13:24
Re: [PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart
,
Daniel Henrique Barboza
,
13:24
Re: [PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset
,
Daniel Henrique Barboza
,
13:24
Re: [PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio
,
Daniel Henrique Barboza
,
13:23
Re: [PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic
,
Daniel Henrique Barboza
,
13:23
Re: [PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint
,
Daniel Henrique Barboza
,
13:23
Re: [PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic
,
Daniel Henrique Barboza
,
13:22
Re: [PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory
,
Daniel Henrique Barboza
,
13:22
Re: [PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint
,
Daniel Henrique Barboza
,
13:22
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Daniel Henrique Barboza
,
13:11
Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
10:33
Re: [PATCH 01/13] hw/riscv/virt: Fix clint base address type
,
Daniel Henrique Barboza
,
08:59
[PATCH v2 8/9] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 7/9] hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 6/9] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 5/9] hw/riscv/virt.c: use s->memmap in create_fdt() path
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 4/9] hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 3/9] hw/riscv/virt.c: use s->memmap in virt_machine_done()
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 2/9] hw/riscv/virt.c: remove trivial virt_memmap references
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Daniel Henrique Barboza
,
08:58
[PATCH v2 0/9] hw/riscv/virt.c: memmap usage cleanup
,
Daniel Henrique Barboza
,
08:58
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Daniel Henrique Barboza
,
08:41
Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint
,
Daniel Henrique Barboza
,
08:26
Re: [PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size
,
Daniel Henrique Barboza
,
06:39
Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Conor Dooley
,
06:29
Re: [PATCH v4 0/9] target/riscv/kvm: CSR related fixes
,
Andrew Jones
,
05:03
Re: [PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size
,
Andrew Jones
,
05:02
[PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie
,
Joel Stanley
,
02:13
[PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc
,
Joel Stanley
,
02:13
[PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart
,
Joel Stanley
,
02:13
[PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio
,
Joel Stanley
,
02:13
[PATCH 13/13] NOMERGE: virt: Adjust devices so everything is > 4G
,
Joel Stanley
,
02:13
[PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu
,
Joel Stanley
,
02:13
[PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset
,
Joel Stanley
,
02:13
[PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic
,
Joel Stanley
,
02:13
[PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint
,
Joel Stanley
,
02:13
[PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic
,
Joel Stanley
,
02:13
[PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory
,
Joel Stanley
,
02:13
[PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint
,
Joel Stanley
,
02:13
[PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint
,
Joel Stanley
,
02:13
[PATCH 01/13] hw/riscv/virt: Fix clint base address type
,
Joel Stanley
,
02:13
[PATCH 00/13] hw/riscv/virt: device tree reg cleanups
,
Joel Stanley
,
02:13
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Joel Stanley
,
01:26
Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Joel Stanley
,
01:26
April 28, 2025
Re: [PATCH v2 0/4] Several sstc extension fixes
,
Jim Shu
,
22:27
Re: [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc
,
Alistair Francis
,
18:47
Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc
,
Alistair Francis
,
18:40
Re: [PATCH 6/7] target/riscv: Move insn_len to internals.h
,
Alistair Francis
,
18:38
Re: [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128
,
Alistair Francis
,
18:37
Re: [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw
,
Alistair Francis
,
18:36
Re: [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128
,
Alistair Francis
,
18:35
Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
,
Alistair Francis
,
18:34
Re: [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn
,
Alistair Francis
,
18:34
[PATCH v4 9/9] target/riscv/kvm: add scounteren CSR
,
Daniel Henrique Barboza
,
15:24
[PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size
,
Daniel Henrique Barboza
,
15:24
[PATCH v4 7/9] target/riscv/kvm: add senvcfg CSR
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 6/9] target/riscv/kvm: do not read unavailable CSRs
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 1/9] target/riscv/kvm: minor fixes/tweaks
,
Daniel Henrique Barboza
,
15:23
[PATCH v4 0/9] target/riscv/kvm: CSR related fixes
,
Daniel Henrique Barboza
,
15:23
Re: [PATCH] target/riscv: add satp mode for kvm host cpu
,
Andrew Jones
,
11:37
Re: [PATCH] target/riscv: add satp mode for kvm host cpu
,
Radim Krčmář
,
09:45
Re: [PATCH] target/riscv: add satp mode for kvm host cpu
,
Radim Krčmář
,
09:45
Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
,
Daniel Henrique Barboza
,
08:27
Re: [PATCH] target/riscv: add satp mode for kvm host cpu
,
Andrew Jones
,
08:09
Re: [PATCH v3 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
,
Alistair Francis
,
07:44
Re: [PATCH v3 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
,
Alistair Francis
,
07:42
Re: [PATCH v3 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros
,
Alistair Francis
,
07:37
Re: [PATCH v3 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
,
Alistair Francis
,
07:36
Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
,
Daniel Henrique Barboza
,
07:34
Re: [PATCH v3 1/9] target/riscv/kvm: minor fixes/tweaks
,
Alistair Francis
,
07:34
[PATCH v2] target/riscv/kvm: add satp mode for host cpu
,
Meng Zhuo
,
04:57
Re: [PATCH] target/riscv: add satp mode for kvm host cpu
,
Andrew Jones
,
03:01
April 27, 2025
[PATCH] target/riscv: add satp mode for kvm host cpu
,
Meng Zhuo
,
11:27
Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
,
Andrew Jones
,
01:59
April 26, 2025
Re: [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
10:12
Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc
,
Daniel Henrique Barboza
,
04:30
Re: [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc
,
Daniel Henrique Barboza
,
04:25
April 25, 2025
Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc
,
Philippe Mathieu-Daudé
,
18:36
Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc
,
Philippe Mathieu-Daudé
,
18:33
Re: [PATCH 6/7] target/riscv: Move insn_len to internals.h
,
Philippe Mathieu-Daudé
,
18:33
Re: [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128
,
Philippe Mathieu-Daudé
,
18:32
Re: [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw
,
Philippe Mathieu-Daudé
,
18:32
Re: [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128
,
Philippe Mathieu-Daudé
,
18:29
Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
,
Philippe Mathieu-Daudé
,
18:29
Re: [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn
,
Philippe Mathieu-Daudé
,
18:29
Re: [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc
,
Daniel Henrique Barboza
,
18:21
Re: [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw
,
Daniel Henrique Barboza
,
18:04
[PATCH v5 06/10] target/i386/kvm: rename architectural PMU variables
,
Dongli Zhang
,
17:34
[PATCH v5 02/10] target/i386: disable PERFCORE when "-pmu" is configured
,
Dongli Zhang
,
17:34
[PATCH v5 10/10] target/i386/kvm: don't stop Intel PMU counters
,
Dongli Zhang
,
17:33
[PATCH v5 07/10] target/i386/kvm: query kvm.enable_pmu parameter
,
Dongli Zhang
,
17:33
[PATCH v5 08/10] target/i386/kvm: reset AMD PMU registers during VM reset
,
Dongli Zhang
,
17:33
[PATCH v5 05/10] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid()
,
Dongli Zhang
,
17:33
[PATCH v5 04/10] target/i386/kvm: set KVM_PMU_CAP_DISABLE if "-pmu" is configured
,
Dongli Zhang
,
17:33
[PATCH v5 09/10] target/i386/kvm: support perfmon-v2 for reset
,
Dongli Zhang
,
17:33
[PATCH v5 00/10] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup
,
Dongli Zhang
,
17:32
[PATCH v5 01/10] target/i386: disable PerfMonV2 when PERFCORE unavailable
,
Dongli Zhang
,
17:32
[PATCH v5 03/10] kvm: Introduce kvm_arch_pre_create_vcpu()
,
Dongli Zhang
,
17:32
[PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
12:51
[PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw
,
Richard Henderson
,
12:51
[PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
12:51
Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
,
Andrew Jones
,
12:43
[PATCH v3 8/9] target/riscv: widen scounteren to target_ulong
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 9/9] target/riscv/kvm: add scounteren CSR
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 7/9] target/riscv/kvm: add senvcfg CSR
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 1/9] target/riscv/kvm: minor fixes/tweaks
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 0/9] target/riscv/kvm: CSR related fixes
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 6/9] target/riscv/kvm: do not read unavailable CSRs
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
,
Daniel Henrique Barboza
,
12:02
[PATCH v3 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
,
Daniel Henrique Barboza
,
12:02
Re: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper to get Host's vendor
,
Dongli Zhang
,
11:46
[PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
11:23
[PATCH 6/7] target/riscv: Move insn_len to internals.h
,
Richard Henderson
,
11:23
[PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128
,
Richard Henderson
,
11:23
[PATCH 4/7] target/riscv: Pass ra to riscv_csrrw
,
Richard Henderson
,
11:23
[PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn
,
Richard Henderson
,
11:23
[PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128
,
Richard Henderson
,
11:23
[PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
,
Richard Henderson
,
11:23
[PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc
,
Richard Henderson
,
11:23
[PATCH v4 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
,
Ran Wang
,
10:05
[PATCH v4 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Ran Wang
,
10:05
[PATCH v4 0/2] riscv: Add Kunminghu CPU and platform
,
Ran Wang
,
10:05
Re: [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong
,
Daniel Henrique Barboza
,
09:10
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Daniel Henrique Barboza
,
08:33
Re: [PATCH v2 9/9] target/riscv/kvm: add scounteren CSR
,
Andrew Jones
,
08:12
Re: [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong
,
Andrew Jones
,
08:11
Re: [PATCH v2 7/9] target/riscv/kvm: add senvcfg CSR
,
Andrew Jones
,
08:04
Re: [PATCH v2 6/9] target/riscv/kvm: do not read unavailable CSRs
,
Andrew Jones
,
08:03
Re: [PATCH v2 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
,
Andrew Jones
,
07:59
Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Daniel Henrique Barboza
,
07:53
Re: [PATCH v2 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro
,
Andrew Jones
,
07:48
Re: [PATCH v2 3/9] target/riscv/kvm: turn u32/u64 reg functions in macros
,
Andrew Jones
,
07:46
Re: [PATCH v4 09/11] target/i386/kvm: reset AMD PMU registers during VM reset
,
Sandipan Das
,
07:45
Re: [PATCH v4 10/11] target/i386/kvm: support perfmon-v2 for reset
,
Sandipan Das
,
07:45
Re: [PATCH v4 03/11] target/i386: disable PERFCORE when "-pmu" is configured
,
Sandipan Das
,
07:45
Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Ran Wang
,
07:45
Re: [PATCH v2 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
,
Andrew Jones
,
07:44
Re: [PATCH v2 1/9] target/riscv/kvm: minor fixes/tweaks
,
Andrew Jones
,
07:44
[PATCH v2 9/9] target/riscv/kvm: add scounteren CSR
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 7/9] target/riscv/kvm: add senvcfg CSR
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 6/9] target/riscv/kvm: do not read unavailable CSRs
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 5/9] target/riscv/kvm: add kvm_csr_cfgs[]
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 3/9] target/riscv/kvm: turn u32/u64 reg functions in macros
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 1/9] target/riscv/kvm: minor fixes/tweaks
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 0/9] target/riscv/kvm: CSR related fixes
,
Daniel Henrique Barboza
,
07:37
[PATCH v2 2/2] target/riscv: Make PMP region count configurable
,
Jay Chang
,
05:45
[PATCH v2 1/2] target/riscv: Extend PMP region up to 64
,
Jay Chang
,
05:45
[PATCH v2 0/2] Extend and configure PMP region count
,
Jay Chang
,
05:45
Re: [PATCH 2/2] target/riscv: Make PMP region count configurable
,
Jay Chang
,
05:44
Re: [PATCH v4 09/11] target/i386/kvm: reset AMD PMU registers during VM reset
,
Zhao Liu
,
04:57
Re: [PATCH v4 08/11] target/i386/kvm: query kvm.enable_pmu parameter
,
Zhao Liu
,
04:35
Re: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper to get Host's vendor
,
Zhao Liu
,
04:08
April 24, 2025
Re: [PATCH v2 07/13] target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
,
Richard Henderson
,
17:01
Re: [PATCH v2 07/13] target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
,
Philippe Mathieu-Daudé
,
16:13
Re: [PATCH 3/3] target/riscv: vadc and vsbc are vm=0 instructions
,
Max Chou
,
10:08
Re: [PATCH 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
,
Max Chou
,
10:08
Re: [PATCH 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions
,
Max Chou
,
10:04
Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Joel Stanley
,
08:58
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Joel Stanley
,
08:58
Re: [PATCH 5/7] target/riscv/kvm: do not read unavailable CSRs
,
Daniel Henrique Barboza
,
08:37
Re: [PATCH 2/2] target/riscv: Make PMP region count configurable
,
Alistair Francis
,
06:55
Re: [PATCH 1/2] target/riscv: Extend PMP region up to 64
,
Alistair Francis
,
06:54
Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Alistair Francis
,
06:50
Re: [PATCH] MAINTAINERS: Add common-user/host/riscv to RISC-V section
,
Alistair Francis
,
06:47
Re: [PATCH] target/riscv: Fix vslidedown with rvv_ta_all_1s
,
Alistair Francis
,
06:46
Re: [PATCH] target/riscv: Fix vslidedown with rvv_ta_all_1s
,
Alistair Francis
,
06:44
Re: [PATCH v3 00/10] Fix RVV encoding corner cases
,
Alistair Francis
,
06:43
Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Alistair Francis
,
06:40
Re: [PATCH v2 07/13] target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
,
Philippe Mathieu-Daudé
,
05:50
Re: [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val
,
Daniel Henrique Barboza
,
05:08
Re: [PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max'
,
Andrew Jones
,
04:21
Re: [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]
,
Andrew Jones
,
04:19
Re: [PATCH 1/3] include/hw/pci: Attach BDF to Memory Attributes
,
Jason Chien
,
03:57
April 23, 2025
Re: [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]
,
Daniel Henrique Barboza
,
15:45
Re: [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val
,
Daniel Henrique Barboza
,
14:46
Re: [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val
,
Andrea Bolognani
,
14:06
Re: [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val
,
Andrew Jones
,
11:46
Re: [PATCH 6/7] target/riscv/kvm: add missing KVM CSRs
,
Andrew Jones
,
11:28
Re: [PATCH 5/7] target/riscv/kvm: do not read unavailable CSRs
,
Andrew Jones
,
11:25
Re: [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]
,
Andrew Jones
,
11:16
Re: [RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Paolo Bonzini
,
10:02
Re: [RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Ben Dooks
,
09:55
Re: [RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Ben Dooks
,
09:10
Re: [RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Paolo Bonzini
,
09:08
Re: [PATCH 2/2] target/riscv: Make PMP region count configurable
,
Daniel Henrique Barboza
,
07:31
Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Philippe Mathieu-Daudé
,
07:27
Re: [PATCH 1/2] target/riscv: Extend PMP region up to 64
,
Daniel Henrique Barboza
,
07:22
[PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings
,
Daniel Henrique Barboza
,
07:07
[PATCH 8/9] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
,
Daniel Henrique Barboza
,
07:07
[PATCH 7/9] hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
,
Daniel Henrique Barboza
,
07:07
[PATCH 3/9] hw/riscv/virt.c: use s->memmap in virt_machine_done()
,
Daniel Henrique Barboza
,
07:07
[PATCH 6/9] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
,
Daniel Henrique Barboza
,
07:07
[PATCH 4/9] hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
,
Daniel Henrique Barboza
,
07:07
[PATCH 5/9] hw/riscv/virt.c: use s->memmap in create_fdt() path
,
Daniel Henrique Barboza
,
07:07
[PATCH 2/9] hw/riscv/virt.c: remove trivial virt_memmap references
,
Daniel Henrique Barboza
,
07:07
[PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()
,
Daniel Henrique Barboza
,
07:06
[PATCH 0/9] hw/riscv/virt.c: memmap usage cleanup
,
Daniel Henrique Barboza
,
07:06
[RFC PATCH] tcg: allow tb_flags to be larger than 32bit
,
Ben Dooks
,
06:40
Re: [PATCH V2 0/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
05:17
Re: [PATCH V2 0/3] acpi: Add machine option to disable SPCR table
,
bibo mao
,
04:50
Re: [PATCH V2 0/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
04:37
Re: [PATCH V2 1/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
04:28
Re: [PATCH V2 0/3] acpi: Add machine option to disable SPCR table
,
bibo mao
,
02:29
April 22, 2025
Re: [PATCH V2 1/3] acpi: Add machine option to disable SPCR table
,
Gavin Shan
,
20:13
Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
,
Deepak Gupta
,
18:35
Re: [PATCH V2 1/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
11:26
Re: [PATCH V2 1/3] acpi: Add machine option to disable SPCR table
,
Philippe Mathieu-Daudé
,
09:19
[PATCH V2 2/3] tests/qtest/bios-tables-test: Add test for disabling SPCR on AArch64
,
Li Chen
,
09:07
[PATCH V2 1/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
09:07
[PATCH V2 0/3] acpi: Add machine option to disable SPCR table
,
Li Chen
,
09:07
Re: [PATCH] acpi: Add machine option to disable SPCR table
,
Li Chen
,
09:07
[PATCH] acpi: Add machine option to disable SPCR table
,
Li Chen
,
09:07
[PATCH V2 3/3] tests/qtest/bios-tables-test: Add test for disabling SPCR on RISC-V
,
Li Chen
,
09:07
Re: [PATCH] acpi: Add machine option to disable SPCR table
,
bibo mao
,
07:33
Re: [PATCH] acpi: Add machine option to disable SPCR table
,
Michael S. Tsirkin
,
07:19
Re: [PATCH] acpi: Add machine option to disable SPCR table
,
Philippe Mathieu-Daudé
,
04:00
Re: [PATCH] MAINTAINERS: Add common-user/host/riscv to RISC-V section
,
Philippe Mathieu-Daudé
,
03:12
April 21, 2025
Re: [PATCH] common-user/host/riscv: use tail pseudoinstruction for calling tail
,
Alistair Francis
,
22:49
[PATCH] MAINTAINERS: Add common-user/host/riscv to RISC-V section
,
Alistair Francis
,
22:48
[PATCH 2/2] target/riscv: Make PMP region count configurable
,
Jay Chang
,
05:47
[PATCH 1/2] target/riscv: Extend PMP region up to 64
,
Jay Chang
,
05:47
[PATCH 0/2] Extend and configure PMP region count
,
Jay Chang
,
05:47
April 18, 2025
Re: [PATCH] common-user/host/riscv: use tail pseudoinstruction for calling tail
,
Richard Henderson
,
18:04
April 17, 2025
[PATCH] common-user/host/riscv: use tail pseudoinstruction for calling tail
,
Icenowy Zheng
,
08:53
[PATCH 3/7] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro
,
Daniel Henrique Barboza
,
08:49
[PATCH 6/7] target/riscv/kvm: add missing KVM CSRs
,
Daniel Henrique Barboza
,
08:49
[PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val
,
Daniel Henrique Barboza
,
08:49
[PATCH 5/7] target/riscv/kvm: do not read unavailable CSRs
,
Daniel Henrique Barboza
,
08:49
[PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[]
,
Daniel Henrique Barboza
,
08:49
[PATCH 2/7] target/riscv/kvm: turn u32/u64 reg functions in macros
,
Daniel Henrique Barboza
,
08:49
[PATCH 0/7] target/riscv/kvm: CSR related fixes
,
Daniel Henrique Barboza
,
08:49
[PATCH 1/7] target/riscv/kvm: minor fixes/tweaks
,
Daniel Henrique Barboza
,
08:49
[PATCH v2 18/18] hw/riscv: virt: Add WorldGuard support
,
Jim Shu
,
06:54
[PATCH v2 17/18] hw/misc: riscv_wgchecker: Check the slot settings in translate
,
Jim Shu
,
06:54
[PATCH v2 16/18] hw/misc: riscv_wgchecker: Implement correct block-access behavior
,
Jim Shu
,
06:54
[PATCH v2 15/18] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
,
Jim Shu
,
06:54
[PATCH v2 14/18] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
,
Jim Shu
,
06:54
[PATCH v2 12/18] target/riscv: Expose CPU options of WorldGuard
,
Jim Shu
,
06:54
[PATCH v2 13/18] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
,
Jim Shu
,
06:54
[PATCH v2 11/18] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
,
Jim Shu
,
06:54
[PATCH v2 10/18] target/riscv: Implement WorldGuard CSRs
,
Jim Shu
,
06:54
[PATCH v2 09/18] target/riscv: Allow global WG config to set WG CPU callbacks
,
Jim Shu
,
06:54
[PATCH v2 08/18] target/riscv: Add defines for WorldGuard CSRs
,
Jim Shu
,
06:53
[PATCH v2 07/18] target/riscv: Add hard-coded CPU state of WG extension
,
Jim Shu
,
06:53
[PATCH v2 06/18] target/riscv: Add CPU options of WorldGuard CPU extension
,
Jim Shu
,
06:53
[PATCH v2 05/18] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
,
Jim Shu
,
06:53
[PATCH v2 03/18] accel/tcg: memory access from CPU will pass access_type to IOMMU
,
Jim Shu
,
06:53
[PATCH v2 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs
,
Jim Shu
,
06:53
[PATCH v2 02/18] system/physmem: Remove the assertion of page-aligned section number
,
Jim Shu
,
06:53
[PATCH v2 01/18] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Jim Shu
,
06:53
[PATCH v2 00/18] Implements RISC-V WorldGuard extension v0.4
,
Jim Shu
,
06:53
April 16, 2025
[PATCH v4 09/11] target/i386/kvm: reset AMD PMU registers during VM reset
,
Dongli Zhang
,
17:58
[PATCH v4 10/11] target/i386/kvm: support perfmon-v2 for reset
,
Dongli Zhang
,
17:58
[PATCH v4 07/11] target/i386/kvm: rename architectural PMU variables
,
Dongli Zhang
,
17:58
[PATCH v4 11/11] target/i386/kvm: don't stop Intel PMU counters
,
Dongli Zhang
,
17:58
[PATCH v4 06/11] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid()
,
Dongli Zhang
,
17:58
[PATCH v4 00/11] target/i386/kvm/pmu: PMU Enhancement, Bugfix and Cleanup
,
Dongli Zhang
,
17:57
[PATCH v4 08/11] target/i386/kvm: query kvm.enable_pmu parameter
,
Dongli Zhang
,
17:57
[PATCH v4 04/11] kvm: Introduce kvm_arch_pre_create_vcpu()
,
Dongli Zhang
,
17:57
[PATCH v4 05/11] target/i386/kvm: set KVM_PMU_CAP_DISABLE if "-pmu" is configured
,
Dongli Zhang
,
17:57
[PATCH v4 03/11] target/i386: disable PERFCORE when "-pmu" is configured
,
Dongli Zhang
,
17:57
[PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper to get Host's vendor
,
Dongli Zhang
,
17:57
[PATCH v4 02/11] target/i386: disable PerfMonV2 when PERFCORE unavailable
,
Dongli Zhang
,
17:57
Re: [PATCH 0/3] Fix some more RVV source overlap issues
,
Max Chou
,
04:29
Re: [PATCH v3 07/10] target/i386/kvm: query kvm.enable_pmu parameter
,
Dongli Zhang
,
03:49
[PATCH v3 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly
,
Chao Liu
,
01:20
[PATCH v3 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState
,
Chao Liu
,
01:20
[PATCH v2 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly
,
Chao Liu
,
00:57
[PATCH v2 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState
,
Chao Liu
,
00:57
April 15, 2025
Re: [PATCH 01/17] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Jim Shu
,
12:39
Re: [PATCH 17/17] hw/riscv: virt: Add WorldGuard support
,
Jim Shu
,
10:47
Re: [PATCH 17/17] hw/riscv: virt: Add WorldGuard support
,
Daniel Henrique Barboza
,
09:21
Re: [PATCH v1 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly
,
Philippe Mathieu-Daudé
,
07:41
Re: [PATCH v1 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly
,
Philippe Mathieu-Daudé
,
06:48
[PATCH v0 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly
,
Chao Liu
,
05:56
[PATCH v0 0/1] fix the way riscv_plic_hart_config_string()
,
Chao Liu
,
05:56
Re: [PATCH 01/17] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Ilya Leoshkevich
,
05:13
[PATCH 15/17] hw/misc: riscv_wgchecker: Implement correct block-access behavior
,
Jim Shu
,
04:14
[PATCH 16/17] hw/misc: riscv_wgchecker: Check the slot settings in translate
,
Jim Shu
,
04:14
[PATCH 17/17] hw/riscv: virt: Add WorldGuard support
,
Jim Shu
,
04:14
[PATCH 11/17] target/riscv: Expose CPU options of WorldGuard
,
Jim Shu
,
04:14
[PATCH 13/17] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
,
Jim Shu
,
04:14
[PATCH 14/17] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
,
Jim Shu
,
04:14
[PATCH 12/17] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
,
Jim Shu
,
04:14
[PATCH 10/17] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
,
Jim Shu
,
04:14
[PATCH 09/17] target/riscv: Implement WorldGuard CSRs
,
Jim Shu
,
04:14
[PATCH 08/17] target/riscv: Allow global WG config to set WG CPU callbacks
,
Jim Shu
,
04:14
[PATCH 07/17] target/riscv: Add defines for WorldGuard CSRs
,
Jim Shu
,
04:13
[PATCH 05/17] target/riscv: Add CPU options of WorldGuard CPU extension
,
Jim Shu
,
04:13
[PATCH 06/17] target/riscv: Add hard-coded CPU state of WG extension
,
Jim Shu
,
04:13
[PATCH 04/17] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
,
Jim Shu
,
04:13
[PATCH 03/17] exec: Add RISC-V WorldGuard WID to MemTxAttrs
,
Jim Shu
,
04:13
[PATCH 02/17] accel/tcg: memory access from CPU will pass access_type to IOMMU
,
Jim Shu
,
04:13
[PATCH 01/17] accel/tcg: Store section pointer in CPUTLBEntryFull
,
Jim Shu
,
04:12
[PATCH 00/17] Implements RISC-V WorldGuard extension v0.4
,
Jim Shu
,
04:12
[PATCH 3/3] target/riscv: vadc and vsbc are vm=0 instructions
,
Anton Blanchard
,
00:32
[PATCH 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
,
Anton Blanchard
,
00:32
[PATCH 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions
,
Anton Blanchard
,
00:32
[PATCH 0/3] Fix some more RVV source overlap issues
,
Anton Blanchard
,
00:32
April 14, 2025
[PATCH] target/riscv: Fix vslidedown with rvv_ta_all_1s
,
Anton Blanchard
,
17:30
Re: [PATCH 1/3] include/hw/pci: Attach BDF to Memory Attributes
,
Michael S. Tsirkin
,
11:29
Re: [PATCH 1/3] include/hw/pci: Attach BDF to Memory Attributes
,
Jason Chien
,
11:11
Re: [PATCH] target/riscv: support atomic instruction fetch (Ziccif)
,
Jim Shu
,
03:00
Re: [PATCH] hw/riscv: Fix type conflict of GLib function pointers
,
Alistair Francis
,
00:49
April 13, 2025
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Kohei Tokunaga
,
04:12
April 12, 2025
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Christian Schoenebeck
,
06:38
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Christian Schoenebeck
,
06:22
Re: [PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Kohei Tokunaga
,
05:13
Re: [PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Kohei Tokunaga
,
05:04
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Christian Schoenebeck
,
04:22
April 11, 2025
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Pierrick Bouvier
,
11:28
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
11:18
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
10:42
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
10:36
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Kohei Tokunaga
,
10:03
Re: [PATCH 05/10] meson: Add wasm build in build scripts
,
Kohei Tokunaga
,
07:23
Re: [PATCH 02/10] various: Define macros for dependencies on emscripten
,
Kohei Tokunaga
,
07:00
Re: [PATCH 01/10] various: Fix type conflict of GLib function pointers
,
Kohei Tokunaga
,
06:56
Re: [PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Philippe Mathieu-Daudé
,
06:51
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Kohei Tokunaga
,
06:47
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Daniel P . Berrangé
,
06:35
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Paolo Bonzini
,
05:08
April 10, 2025
Re: [PATCH] hw/riscv: Fix type conflict of GLib function pointers
,
Alistair Francis
,
21:33
Re: [PATCH v3 10/10] target/i386/kvm: don't stop Intel PMU counters
,
Dongli Zhang
,
18:26
Re: [PATCH v3 08/10] target/i386/kvm: reset AMD PMU registers during VM reset
,
Dongli Zhang
,
17:22
Re: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
,
Dongli Zhang
,
17:20
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Pierrick Bouvier
,
17:17
Re: [PATCH v3 07/10] target/i386/kvm: query kvm.enable_pmu parameter
,
Dongli Zhang
,
16:17
Re: [PATCH] hw/riscv: Fix type conflict of GLib function pointers
,
Philippe Mathieu-Daudé
,
12:53
Re: [PATCH] hw/riscv: Fix type conflict of GLib function pointers
,
Kohei Tokunaga
,
12:47
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Paolo Bonzini
,
12:29
[PATCH] hw/riscv: Fix type conflict of GLib function pointers
,
Paolo Bonzini
,
12:18
Re: [PATCH 01/10] various: Fix type conflict of GLib function pointers
,
Paolo Bonzini
,
11:59
Re: [PATCH 02/10] various: Define macros for dependencies on emscripten
,
Paolo Bonzini
,
11:54
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
09:14
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
09:12
Re: [PATCH 05/10] meson: Add wasm build in build scripts
,
Paolo Bonzini
,
08:55
Re: [PATCH 05/10] meson: Add wasm build in build scripts
,
Kohei Tokunaga
,
08:24
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Philippe Mathieu-Daudé
,
08:20
Re: [PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Christian Schoenebeck
,
07:27
Re: [PATCH v3 10/10] target/i386/kvm: don't stop Intel PMU counters
,
Zhao Liu
,
05:25
Re: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
,
Zhao Liu
,
04:01
Re: [PATCH v3 08/10] target/i386/kvm: reset AMD PMU registers during VM reset
,
Zhao Liu
,
03:23
Re: [PATCH v3 07/10] target/i386/kvm: query kvm.enable_pmu parameter
,
Zhao Liu
,
00:44
April 09, 2025
Re: [PATCH v3 05/10] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid()
,
Zhao Liu
,
22:20
Re: [PATCH 00/10] Enable QEMU to run on browsers
,
Stefan Hajnoczi
,
15:21
Re: [PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Kohei Tokunaga
,
09:53
Re: [PATCH 01/10] various: Fix type conflict of GLib function pointers
,
Kohei Tokunaga
,
09:44
Re: [PATCH 05/10] meson: Add wasm build in build scripts
,
Paolo Bonzini
,
09:35
Re: [PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Philippe Mathieu-Daudé
,
06:58
Re: [PATCH 05/10] meson: Add wasm build in build scripts
,
Philippe Mathieu-Daudé
,
06:55
Re: [PATCH 01/10] various: Fix type conflict of GLib function pointers
,
Philippe Mathieu-Daudé
,
06:55
April 08, 2025
Re: [PATCH v2 0/4] Several sstc extension fixes
,
Jim Shu
,
22:58
[PATCH v2 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
,
Jim Shu
,
22:52
[PATCH v2 3/4] target/riscv: Fix VSTIP bit in sstc extension.
,
Jim Shu
,
22:52
[PATCH v2 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension
,
Jim Shu
,
22:51
[PATCH v2 1/4] target/riscv: Add the checking into stimecmp write function.
,
Jim Shu
,
22:51
[PATCH v2 0/4] Several sstc extension fixes
,
Jim Shu
,
22:51
Re: [PATCH v3 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
,
Daniel Henrique Barboza
,
08:49
Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Daniel Henrique Barboza
,
08:47
[PATCH v3 06/10] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
,
Max Chou
,
06:40
[PATCH v3 09/10] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
,
Max Chou
,
06:40
[PATCH v3 05/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
,
Max Chou
,
06:40
[PATCH v3 03/10] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint
,
Max Chou
,
06:40
[PATCH v3 02/10] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
,
Max Chou
,
06:40
[PATCH v3 10/10] target/riscv: Fix the rvv reserved encoding of unmasked instructions
,
Max Chou
,
06:40
[PATCH v3 08/10] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions
,
Max Chou
,
06:40
[PATCH v3 07/10] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)
,
Max Chou
,
06:40
[PATCH v3 04/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
,
Max Chou
,
06:40
[PATCH v3 00/10] Fix RVV encoding corner cases
,
Max Chou
,
06:40
[PATCH v3 01/10] target/riscv: rvv: Source vector registers cannot overlap mask register
,
Max Chou
,
06:40
April 07, 2025
[PATCH v3 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
,
Huang Borong
,
22:26
[PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Huang Borong
,
22:22
[PATCH 06/10] include/exec: Allow using 64bit guest addresses on emscripten
,
Kohei Tokunaga
,
11:16
[PATCH 05/10] meson: Add wasm build in build scripts
,
Kohei Tokunaga
,
11:16
[PATCH 08/10] hw/9pfs: Allow using hw/9pfs with emscripten
,
Kohei Tokunaga
,
11:15
[PATCH 07/10] tcg: Add a TCG backend for WebAssembly
,
Kohei Tokunaga
,
11:15
[PATCH 10/10] MAINTAINERS: Update MAINTAINERS file for wasm-related files
,
Kohei Tokunaga
,
11:15
[PATCH 01/10] various: Fix type conflict of GLib function pointers
,
Kohei Tokunaga
,
11:15
[PATCH 09/10] gitlab: Enable CI for wasm build
,
Kohei Tokunaga
,
11:15
[PATCH 03/10] util/mmap-alloc: Add qemu_ram_mmap implementation for emscripten
,
Kohei Tokunaga
,
11:15
[PATCH 00/10] Enable QEMU to run on browsers
,
Kohei Tokunaga
,
11:15
[PATCH 04/10] util: Add coroutine backend for emscripten
,
Kohei Tokunaga
,
11:15
[PATCH 02/10] various: Define macros for dependencies on emscripten
,
Kohei Tokunaga
,
11:14
Re: [PATCH v2 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
,
Daniel Henrique Barboza
,
10:04
Re: [PATCH v2 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Daniel Henrique Barboza
,
09:57
Re: [PATCH 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension
,
Jim Shu
,
06:06
Re: [PATCH 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
,
Jim Shu
,
05:43
[PATCH v2 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
,
Huang Borong
,
05:22
[PATCH v2 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
,
Huang Borong
,
05:19
Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
,
Max Chou
,
04:36
Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
,
Max Chou
,
04:34
Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint
,
Max Chou
,
04:32
April 06, 2025
Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option
,
Alistair Francis
,
19:33
Re: [PATCH 1/2] target/riscv/tcg: make 'max' cpu rva23s64 compliant
,
Alistair Francis
,
19:27
Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
19:26
Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option
,
Alistair Francis
,
19:23
Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
14:24
April 05, 2025
Re: [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions
,
Daniel Henrique Barboza
,
05:21
Re: [PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
,
Daniel Henrique Barboza
,
05:20
Re: [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions
,
Daniel Henrique Barboza
,
05:20
Re: [PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)
,
Daniel Henrique Barboza
,
05:20
Re: [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)
,
Daniel Henrique Barboza
,
05:18
Re: [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
,
Daniel Henrique Barboza
,
05:18
Re: [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
,
Daniel Henrique Barboza
,
05:18
Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
,
Daniel Henrique Barboza
,
05:17
Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
,
Daniel Henrique Barboza
,
05:14
Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint
,
Daniel Henrique Barboza
,
05:09
Re: [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
,
Daniel Henrique Barboza
,
04:59
Re: [PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register
,
Daniel Henrique Barboza
,
04:58
April 04, 2025
[PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max'
,
Daniel Henrique Barboza
,
11:28
[PATCH 1/2] target/riscv/tcg: make 'max' cpu rva23s64 compliant
,
Daniel Henrique Barboza
,
11:28
[PATCH 0/2] hw/riscv/virt.c: change default CPU to 'max'
,
Daniel Henrique Barboza
,
11:28
Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option
,
Daniel Henrique Barboza
,
09:15
Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option
,
Philippe Mathieu-Daudé
,
09:08
Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default
,
Andrew Jones
,
09:01
Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default
,
Philippe Mathieu-Daudé
,
08:37
[PATCH for-10.0] docs: deprecate RISC-V default machine option
,
Daniel Henrique Barboza
,
08:29
Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default
,
Daniel Henrique Barboza
,
07:30
Re: [PATCH 0/1 v2] [RISC-V/RVV] use a single function to probe memory.
,
Alistair Francis
,
02:07
Re: [PATCH 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
,
Alistair Francis
,
02:03
Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default
,
Alistair Francis
,
01:50
Re: [PATCH] target/riscv: support atomic instruction fetch (Ziccif)
,
Alistair Francis
,
00:41
April 03, 2025
Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
23:26
Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
,
Alistair Francis
,
23:22
Re: [PATCH 3/4] target/riscv: Fix VSTIP bit in sstc extension.
,
Alistair Francis
,
23:13
Re: [PATCH 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension
,
Alistair Francis
,
23:12
Re: [PATCH 1/4] target/riscv: Add the checking into stimecmp write function.
,
Alistair Francis
,
23:05
Re: [PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.
,
Alistair Francis
,
23:02
Re: [PATCH v3 0/6] Improve Microchip Polarfire SoC customization
,
Alistair Francis
,
22:33
Re: [PATCH v3 6/6] hw/riscv: microchip_pfsoc: Rework documentation
,
Alistair Francis
,
22:26
Re: [PATCH v3 5/6] hw/riscv: Configurable MPFS CLINT timebase freq
,
Alistair Francis
,
22:12
Re: [PATCH v3 4/6] hw/riscv: Allow direct start of kernel for MPFS
,
Alistair Francis
,
22:01
Re: [PATCH v3 3/6] hw/riscv: Make FDT optional for MPFS
,
Alistair Francis
,
21:52
Re: [PATCH v3 1/6] hw/misc: Add MPFS system reset support
,
Alistair Francis
,
21:49
Re: [PATCH 0/1 v2] [RISCV/RVV] Generate strided vector loads/stores with tcg nodes.
,
Alistair Francis
,
21:47
Re: [PATCH 3/3] hw/riscv/riscv_iommu: Remove the "bus" property
,
Alistair Francis
,
21:43
Re: [PATCH v2 0/5] target/riscv: Smepmp fixes to match specification
,
Alistair Francis
,
21:23
Re: [PATCH v2 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked
,
Alistair Francis
,
21:06
Re: [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed
,
Alistair Francis
,
21:05
Re: [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function
,
Alistair Francis
,
21:02
Re: [PATCH v2 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges
,
Alistair Francis
,
21:01
Re: [PATCH v2 2/2] target/riscv: Restrict midelegh access to S-mode harts
,
Alistair Francis
,
19:40
Re: [PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
,
Alistair Francis
,
19:35
April 02, 2025
Re: [PATCH-for-10.0?] target/riscv: Do not expose rv128 CPU on user mode emulation
,
Philippe Mathieu-Daudé
,
17:25
Re: [PATCH-for-10.0?] target/riscv: Do not expose rv128 CPU on user mode emulation
,
Daniel Henrique Barboza
,
17:22
[PATCH-for-10.0?] target/riscv: Do not expose rv128 CPU on user mode emulation
,
Philippe Mathieu-Daudé
,
16:52
Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
,
Philippe Mathieu-Daudé
,
10:40
Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
,
Philippe Mathieu-Daudé
,
10:25
April 01, 2025
Re: [PATCH 0/4] Several sstc extension fixes
,
Jim Shu
,
22:36
[PATCH v2 2/2] target/riscv: Restrict midelegh access to S-mode harts
,
Jay Chang
,
06:34
[PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
,
Jay Chang
,
06:34
Re: [PATCH v2 11/42] accel/tcg: Perform aligned atomic reads in translator_ld
,
Philippe Mathieu-Daudé
,
02:18
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