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[PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA
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From: |
Yong-Xuan Wang |
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Subject: |
[PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA |
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Date: |
Mon, 17 Feb 2025 16:17:22 +0800 |
Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA
extension in VS mode.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
target/riscv/kvm/kvm-cpu.c | 45 ++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index e315fea46973..e74c1d7cdcee 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -132,6 +132,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu,
#define RISCV_GENERAL_CSR_REG(name) \
(KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name))
+#define RISCV_AIA_CSR_REG(name) \
+ (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name))
+
#define KVM_RISCV_GET_CSR(cs, env, idx, reg) \
do { \
int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \
@@ -641,9 +644,50 @@ static int kvm_riscv_put_regs_general_csr(CPUState *cs)
return 0;
}
+static int kvm_riscv_get_regs_aia_csr(CPUState *cs)
+{
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+ uint64_t mask = MAKE_64BIT_MASK(32, 32);
+ uint64_t val;
+
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect);
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]);
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]);
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]);
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]);
+
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val);
+ env->sie = set_field(env->sie, mask, val);
+ KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val);
+ riscv_cpu_update_mip(env, mask, val);
+
+ return 0;
+}
+
+static int kvm_riscv_put_regs_aia_csr(CPUState *cs)
+{
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+ uint64_t mask = MAKE_64BIT_MASK(32, 32);
+ uint64_t val;
+
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]);
+
+ val = get_field(env->sie, mask);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val);
+ val = get_field(env->mip, mask);
+ KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val);
+
+ return 0;
+}
+
static int kvm_riscv_get_regs_csr(CPUState *cs)
{
kvm_riscv_get_regs_general_csr(cs);
+ kvm_riscv_get_regs_aia_csr(cs);
return 0;
}
@@ -651,6 +695,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
static int kvm_riscv_put_regs_csr(CPUState *cs)
{
kvm_riscv_put_regs_general_csr(cs);
+ kvm_riscv_put_regs_aia_csr(cs);
return 0;
}
--
2.17.1
- [PATCH 0/8] riscv: AIA: kernel-irqchip=off support, Yong-Xuan Wang, 2025/02/17
- [PATCH 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR, Yong-Xuan Wang, 2025/02/17
- [PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA,
Yong-Xuan Wang <=
- [PATCH 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN, Yong-Xuan Wang, 2025/02/17
- [PATCH 4/8] target/riscv: add helper to get CSR name, Yong-Xuan Wang, 2025/02/17
- [PATCH 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr, Yong-Xuan Wang, 2025/02/17
- [PATCH 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation, Yong-Xuan Wang, 2025/02/17
- [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic, Yong-Xuan Wang, 2025/02/17
- [PATCH 8/8] docs: update the description about RISC-V AIA, Yong-Xuan Wang, 2025/02/17