Re: [PATCH v5 7/7] target/riscv: machine: Add Control Transfer Record state description

[Alistair Francis]

On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> Add a subsection to machine.c to migrate CTR CSR state
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/machine.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 
> e1bdc31c7c53a8a4f539113d501c8e46f7a914e9..b67e660ef03b6053fa00d5a79e2ab20ecf3331b8
>  100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -311,6 +311,30 @@ static const VMStateDescription vmstate_envcfg = {
>      }
>  };
>
> +static bool ctr_needed(void *opaque)
> +{
> +    RISCVCPU *cpu = opaque;
> +
> +    return cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr;
> +}
> +
> +static const VMStateDescription vmstate_ctr = {
> +    .name = "cpu/ctr",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = ctr_needed,
> +    .fields = (const VMStateField[]) {
> +        VMSTATE_UINT64(env.mctrctl, RISCVCPU),
> +        VMSTATE_UINT32(env.sctrdepth, RISCVCPU),
> +        VMSTATE_UINT32(env.sctrstatus, RISCVCPU),
> +        VMSTATE_UINT64(env.vsctrctl, RISCVCPU),
> +        VMSTATE_UINT64_ARRAY(env.ctr_src, RISCVCPU, 16 << SCTRDEPTH_MAX),
> +        VMSTATE_UINT64_ARRAY(env.ctr_dst, RISCVCPU, 16 << SCTRDEPTH_MAX),
> +        VMSTATE_UINT64_ARRAY(env.ctr_data, RISCVCPU, 16 << SCTRDEPTH_MAX),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
>  static bool pmu_needed(void *opaque)
>  {
>      RISCVCPU *cpu = opaque;
> @@ -461,6 +485,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>          &vmstate_jvt,
>          &vmstate_elp,
>          &vmstate_ssp,
> +        &vmstate_ctr,
>          NULL
>      }
>  };
>
> --
> 2.34.1
>
>