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Re: [PATCH v3 1/5] target/riscv: Add svukte extension capability variabl
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 1/5] target/riscv: Add svukte extension capability variable |
Date: |
Tue, 19 Nov 2024 13:22:00 +1000 |
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Refer to the draft of svukte extension from:
> https://github.com/riscv/riscv-isa-manual/pull/1564
>
> Svukte provides a means to make user-mode accesses to supervisor memory
> raise page faults in constant time, mitigating attacks that attempt to
> discover the supervisor software's address-space layout.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_cfg.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 59d6fc445d..d8771ca641 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -84,6 +84,7 @@ struct RISCVCPUConfig {
> bool ext_svnapot;
> bool ext_svpbmt;
> bool ext_svvptc;
> + bool ext_svukte;
> bool ext_zdinx;
> bool ext_zaamo;
> bool ext_zacas;
> --
> 2.34.1
>
>
- [PATCH v3 0/5] Introduce svukte ISA extension, Fea.Wang, 2024/11/12
- [PATCH v3 1/5] target/riscv: Add svukte extension capability variable, Fea.Wang, 2024/11/12
- Re: [PATCH v3 1/5] target/riscv: Add svukte extension capability variable,
Alistair Francis <=
- [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Fea.Wang, 2024/11/12
- [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Fea.Wang, 2024/11/12
- [PATCH v3 5/5] target/riscv: Expose svukte ISA extension, Fea.Wang, 2024/11/12
- [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule, Fea.Wang, 2024/11/12