diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fda54671d5..f10871d352 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -273,6 +273,35 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU
*cpu)
}
}
+static void riscv_cpu_validate_b(RISCVCPU *cpu)
+{
+ const char *warn_msg = "RVB mandates disabled extension %s";
+
+ if (!cpu->cfg.ext_zba) {
+ if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) {
+ cpu->cfg.ext_zba = true;
+ } else {
+ warn_report(warn_msg, "zba");
+ }
+ }
+
+ if (!cpu->cfg.ext_zbb) {
+ if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) {
+ cpu->cfg.ext_zbb = true;
+ } else {
+ warn_report(warn_msg, "zbb");
+ }
+ }
+
+ if (!cpu->cfg.ext_zbs) {
+ if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) {
+ cpu->cfg.ext_zbs = true;
+ } else {
+ warn_report(warn_msg, "zbs");
+ }
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -309,6 +338,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
}
+ if (riscv_has_ext(env, RVB)) {
+ riscv_cpu_validate_b(cpu);
+ }
+
if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
error_setg(errp,
"I and E extensions are incompatible");