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[PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext
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From: |
Weiwei Li |
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Subject: |
[PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext |
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Date: |
Tue, 23 May 2023 21:59:34 +0800 |
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1c9a667653..d756866925 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,6 +59,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong cur_insn_len;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
@@ -1114,8 +1115,9 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
};
ctx->virt_inst_excp = false;
+ ctx->cur_insn_len = insn_len(opcode);
/* Check for compressed insn */
- if (insn_len(opcode) == 2) {
+ if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
--
2.25.1
- [PATCH v2 1/7] target/riscv: Fix target address to update badaddr, (continued)
- [PATCH v2 1/7] target/riscv: Fix target address to update badaddr, Weiwei Li, 2023/05/23
- [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext, Weiwei Li, 2023/05/23
- [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff, Weiwei Li, 2023/05/23
- [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements, Weiwei Li, 2023/05/23
- [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext,
Weiwei Li <=
- [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc, Weiwei Li, 2023/05/23
- Re: [PATCH v2 0/7] target/riscv: Add support for PC-relative translation, Alistair Francis, 2023/05/25