Re: [PATCH v9 00/11] target/riscv: rework CPU extension validation

[Alistair Francis]

On Wed, May 17, 2023 at 11:59 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this version we have a change in patch 11. We're now firing a
> GUEST_ERROR if write_misa() fails and we need to rollback (i.e. not
> change MISA ext).
>
> No other changes made.
>
> Changes from v8:
> - patch 11:
>   - log a GUEST_ERROR if we decided to keep the current env->misa_ext
>     value because the user value failed our validation
> - v8 link: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg03584.html
>
>
> Daniel Henrique Barboza (9):
>   target/riscv/cpu.c: add riscv_cpu_validate_v()
>   target/riscv/cpu.c: remove set_vext_version()
>   target/riscv/cpu.c: remove set_priv_version()
>   target/riscv: add PRIV_VERSION_LATEST
>   target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
>   target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
>   target/riscv/cpu.c: validate extensions before riscv_timer_init()
>   target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
>   target/riscv: rework write_misa()

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> Weiwei Li (2):
>   target/riscv: Mask the implicitly enabled extensions in isa_string
>     based on priv version
>   target/riscv: Update check for Zca/Zcf/Zcd
>
>  target/riscv/cpu.c                      | 333 ++++++++++++++----------
>  target/riscv/cpu.h                      |   3 +
>  target/riscv/csr.c                      |  51 ++--
>  target/riscv/insn_trans/trans_rvd.c.inc |  12 +-
>  target/riscv/insn_trans/trans_rvf.c.inc |  14 +-
>  target/riscv/insn_trans/trans_rvi.c.inc |   5 +-
>  target/riscv/translate.c                |   5 +-
>  7 files changed, 248 insertions(+), 175 deletions(-)
>
> --
> 2.40.1
>
>