[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are chang
|
From: |
Weiwei Li |
|
Subject: |
[PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed |
|
Date: |
Wed, 17 May 2023 17:15:14 +0800 |
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 666fbb74b9..8cb8519b0c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
if (riscv_cpu_cfg(env)->epmp) {
/* Sticky bits */
val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+ tlb_flush(env_cpu(env));
+ }
} else {
val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
}
--
2.25.1
- [PATCH v6 00/12] target/riscv: Fix PMP related problem, Weiwei Li, 2023/05/17
- [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/05/17
- [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/05/17
- [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed,
Weiwei Li <=
- [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/05/17
- [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/05/17
- [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Weiwei Li, 2023/05/17
- [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/05/17
- [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Weiwei Li, 2023/05/17
- [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/05/17
- [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/05/17
- [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry, Weiwei Li, 2023/05/17
- [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/05/17
- Re: [PATCH v6 00/12] target/riscv: Fix PMP related problem, Alistair Francis, 2023/05/18