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[PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j |
Date: |
Mon, 27 Mar 2023 19:49:29 -0300 |
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 6 +++---
target/riscv/cpu.h | 1 -
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9fa7104801..e02d6f06e8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1119,7 +1119,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_v) {
ext |= RVV;
}
- if (riscv_cpu_cfg(env)->ext_j) {
+ if (riscv_has_ext(env, RVJ)) {
ext |= RVJ;
}
@@ -1452,6 +1452,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVU, .enabled = true},
{.name = "h", .description = "Hypervisor",
.misa_bit = RVH, .enabled = true},
+ {.name = "x-j", .description = "Dynamic translated languages",
+ .misa_bit = RVJ, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1548,7 +1550,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
@@ -1580,7 +1581,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_j = misa_ext & RVJ;
/*
* We don't want to set the default riscv_cpu_extensions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f3cb28443c..43a40ba950 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
--
2.39.2
- [PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a, (continued)
- [PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 06/19] target/riscv: remove cpu->cfg.ext_d, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 07/19] target/riscv: remove cpu->cfg.ext_f, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 09/19] target/riscv: remove cpu->cfg.ext_e, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 08/19] target/riscv: remove cpu->cfg.ext_i, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 11/19] target/riscv: remove cpu->cfg.ext_s, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 12/19] target/riscv: remove cpu->cfg.ext_u, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j,
Daniel Henrique Barboza <=
- [PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 19/19] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/27