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[PATCH 10/19] target/riscv: remove cpu->cfg.ext_m
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 10/19] target/riscv: remove cpu->cfg.ext_m |
Date: |
Mon, 27 Mar 2023 09:42:38 -0300 |
Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 10 +++++-----
target/riscv/cpu.h | 1 -
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 65e4a76bae..9f4d8fe7e8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -811,13 +811,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m &&
+ if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
+ riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_m = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -1094,7 +1094,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVE)) {
ext |= RVE;
}
- if (riscv_cpu_cfg(env)->ext_m) {
+ if (riscv_has_ext(env, RVM)) {
ext |= RVM;
}
if (riscv_has_ext(env, RVA)) {
@@ -1446,6 +1446,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVI, .enabled = true},
{.name = "e", .description = "Base integer instruction set (embedded)",
.misa_bit = RVE, .enabled = false},
+ {.name = "m", .description = "Integer multiplication and division",
+ .misa_bit = RVM, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1469,7 +1471,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cc0b9e73ac..7a42c80b7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_m;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.39.2
- Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties(), (continued)
[PATCH 04/19] target/riscv: remove cpu->cfg.ext_a, Daniel Henrique Barboza, 2023/03/27
[PATCH 05/19] target/riscv: remove cpu->cfg.ext_c, Daniel Henrique Barboza, 2023/03/27
[PATCH 06/19] target/riscv: remove cpu->cfg.ext_d, Daniel Henrique Barboza, 2023/03/27
[PATCH 07/19] target/riscv: remove cpu->cfg.ext_f, Daniel Henrique Barboza, 2023/03/27
[PATCH 08/19] target/riscv: remove cpu->cfg.ext_i, Daniel Henrique Barboza, 2023/03/27
[PATCH 09/19] target/riscv: remove cpu->cfg.ext_e, Daniel Henrique Barboza, 2023/03/27
[PATCH 10/19] target/riscv: remove cpu->cfg.ext_m,
Daniel Henrique Barboza <=
[PATCH 11/19] target/riscv: remove cpu->cfg.ext_s, Daniel Henrique Barboza, 2023/03/27
[PATCH 12/19] target/riscv: remove cpu->cfg.ext_u, Daniel Henrique Barboza, 2023/03/27
[PATCH 13/19] target/riscv: remove cpu->cfg.ext_h, Daniel Henrique Barboza, 2023/03/27
[PATCH 14/19] target/riscv: remove cpu->cfg.ext_j, Daniel Henrique Barboza, 2023/03/27
[PATCH 15/19] target/riscv: remove cpu->cfg.ext_v, Daniel Henrique Barboza, 2023/03/27
[PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg(), Daniel Henrique Barboza, 2023/03/27
[PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Daniel Henrique Barboza, 2023/03/27
[PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g, Daniel Henrique Barboza, 2023/03/27
[PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/27