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[PATCH v6 13/25] target/riscv: Introduce mmuidx_priv
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From: |
Richard Henderson |
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Subject: |
[PATCH v6 13/25] target/riscv: Introduce mmuidx_priv |
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Date: |
Sat, 25 Mar 2023 03:54:17 -0700 |
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/internals.h | 9 +++++++++
target/riscv/cpu_helper.c | 6 +-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 0b61f337dd..4aa1cb409f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@
#define MMUIdx_M 3
#define MMU_2STAGE_BIT (1 << 2)
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
static inline bool mmuidx_sum(int mmu_idx)
{
return (mmu_idx & 3) == MMUIdx_S_SUM;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7e6cd8e0fd..cb260b88ea 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -771,7 +771,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- int mode = env->priv;
+ int mode = mmuidx_priv(mmu_idx);
bool use_background = false;
hwaddr ppn;
RISCVCPU *cpu = env_archcpu(env);
@@ -793,10 +793,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
instructions, HLV, HLVX, and HSV. */
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
- } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
- }
}
if (first_stage == false) {
--
2.34.1
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, (continued)
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/03/25
- [PATCH v6 12/25] target/riscv: Introduce mmuidx_sum, Richard Henderson, 2023/03/25
- [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/03/25
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/03/25
- [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop, Richard Henderson, 2023/03/25
- [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/03/25
- [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/03/25
- [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv,
Richard Henderson <=
- [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage, Richard Henderson, 2023/03/25
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX, Richard Henderson, 2023/03/25
- [PATCH v6 02/25] target/riscv: Add a general status enum for extensions, Richard Henderson, 2023/03/25