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[PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_B
From: |
Richard Henderson |
Subject: |
[PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT |
Date: |
Sat, 25 Mar 2023 03:54:15 -0700 |
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/internals.h | 6 ++++--
target/riscv/cpu_helper.c | 2 +-
target/riscv/op_helper.c | 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b55152a7dc..7b63c0f1b6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,13 +27,15 @@
* - S 0b001
* - S+SUM 0b010
* - M 0b011
- * - HLV/HLVX/HSV adds 0b100
+ * - U+2STAGE 0b100
+ * - S+2STAGE 0b101
+ * - S+SUM+2STAGE 0b110
*/
#define MMUIdx_U 0
#define MMUIdx_S 1
#define MMUIdx_S_SUM 2
#define MMUIdx_M 3
-#define MMU_HYP_ACCESS_BIT (1 << 2)
+#define MMU_2STAGE_BIT (1 << 2)
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9bb84be4e1..888f7ae0ef 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -605,7 +605,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
- return mmu_idx & MMU_HYP_ACCESS_BIT;
+ return mmu_idx & MMU_2STAGE_BIT;
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 0f81645adf..81362537b6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x,
uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
- return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
+ return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
--
2.34.1
- [PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers, (continued)
- [PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers, Richard Henderson, 2023/03/25
- [PATCH v6 22/25] target/riscv: Don't modify SUM with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/03/25
- [PATCH v6 12/25] target/riscv: Introduce mmuidx_sum, Richard Henderson, 2023/03/25
- [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/03/25
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/03/25
- [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop, Richard Henderson, 2023/03/25
- [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT,
Richard Henderson <=
- [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/03/25
- [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv, Richard Henderson, 2023/03/25
- [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage, Richard Henderson, 2023/03/25
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX, Richard Henderson, 2023/03/25