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[PATCH for-8.1 15/17] target/riscv: add RVG
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 15/17] target/riscv: add RVG |
Date: |
Wed, 8 Mar 2023 17:19:23 -0300 |
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7a5d202069..7be6a86305 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -274,6 +274,9 @@ static uint32_t
riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg)
if (cfg->ext_j) {
ext |= RVJ;
}
+ if (cfg->ext_g) {
+ ext |= RVG;
+ }
return ext;
}
@@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg,
cfg->ext_u = misa_ext & RVU;
cfg->ext_h = misa_ext & RVH;
cfg->ext_j = misa_ext & RVJ;
+ cfg->ext_g = misa_ext & RVG;
}
static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 529d8044c4..013a1389d6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,6 +82,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVJ RV('J')
+#define RVG RV('G')
/* Privileged specification version */
--
2.39.2
- [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), (continued)
- [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 15/17] target/riscv: add RVG,
Daniel Henrique Barboza <=
- [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 17/17] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/08
- Re: [PATCH for-8.1 00/17] centralize CPU extensions logic, Daniel Henrique Barboza, 2023/03/09