[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 00/22] Sixth RISC-V PR for 8.0
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/22] Sixth RISC-V PR for 8.0 |
Date: |
Tue, 7 Mar 2023 14:33:09 +0000 |
On Mon, 6 Mar 2023 at 22:04, Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0:
>
> configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46
> +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306
>
> for you to fetch changes up to 47fc340010335bc2549bc1f07e5fd85d86a2b9f9:
>
> MAINTAINERS: Add entry for RISC-V ACPI (2023-03-06 11:35:08 -0800)
>
> ----------------------------------------------------------------
> Sixth RISC-V PR for 8.0
>
> * Support for the Zicbiom, ZCicboz, and Zicbop extensions.
> * OpenSBI has been updated to version 1.2, see
> <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for
> the release notes.
> * Support for setting the virtual address width (ie, sv39/sv48/sv57) on
> the command line.
> * Support for ACPI on RISC-V.
>
> ----------------------------------------------------------------
> Sorry for the flurry of late pull requests, but we had a few stragglers
> (ACPI due to reviews and OpenSBI due to the CI failures, the others I'd
> largely just missed). I don't intend on sending anything else for the
> soft freeze, this is already well past late enough for me ;)
>
> I'm not exactly sure what happened, but this tag managed to pass CI
> <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797833683> despite
> me not really doing anything to fix the timeouts -- hopefully that was
> just a result of me having gotten unlucky or missing a larger timeout in
> my fork, but sorry if I've managed to screw something up.
>
> I have no merge conflicts and the tests are passing locally. I've got a
> CI run here
> <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797922220>, but I
> figured I'd just send this now given that I had one pass from just the
> tag.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, (continued)
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, Palmer Dabbelt, 2023/03/06
- [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/03/06
- [PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState, Palmer Dabbelt, 2023/03/06
- [PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields, Palmer Dabbelt, 2023/03/06
- [PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI, Palmer Dabbelt, 2023/03/06
- [PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT, Palmer Dabbelt, 2023/03/06
- [PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure, Palmer Dabbelt, 2023/03/06
- [PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI, Palmer Dabbelt, 2023/03/06
- [PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables, Palmer Dabbelt, 2023/03/06
- [PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table, Palmer Dabbelt, 2023/03/06
- Re: [PULL 00/22] Sixth RISC-V PR for 8.0,
Peter Maydell <=