Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble

[Palmer Dabbelt]

On Fri, 17 Feb 2023 07:14:59 PST (-0800), ivan.klokov@syntacore.com wrote:
> Due to typo in opcode list, ctzw is disassembled as clzw instruction.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
> ---
>  disas/riscv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ddda687c13..d0639cd047 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1644,7 +1644,7 @@ const rv_opcode_data opcode_data[] = {
>      { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
>      { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
>      { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> -    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> +    { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
>      { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
>      { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
>      { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },

Thanks, this is queue up on riscv-to-apply.next -- I think I managed to 
get all the reviews and such from the mailing list, it got a bit 
confused.

Here's what I've got:

commit 270629024df1f9f4e704ce8325f958858c5cbff7
gpg: Signature made Sun 05 Mar 2023 12:43:52 PM PST
gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
gpg:                issuer "palmer@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [ultimate]
gpg:                 aka "Palmer Dabbelt <palmer@rivosinc.com>" [ultimate]
Author: Ivan Klokov <ivan.klokov@syntacore.com>
Date:   Fri Feb 17 18:14:59 2023 +0300

   disas/riscv Fix ctzw disassemble
   
   Due to typo in opcode list, ctzw is disassembled as clzw instruction.
   
   Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
   Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
   Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
   Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
   Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
   Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..54455aaaa8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
    { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
    { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },